CN101489128A - JPEG2000 pipeline arithmetic encoding method and circuit - Google Patents
JPEG2000 pipeline arithmetic encoding method and circuit Download PDFInfo
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Abstract
A JPEG2000 pipeline arithmetic coding method and a circuit belongs to the picture compression technique field, wherein the arithmetic coding is finished through four grade pipeline, the circuit comprises a context state table query updating module, a probability estimate query module, an A register updating module, a C register updating module and a byte output module respectively forming the four grade pipeline, the context state table query updating module is connected to the probability estimate query module, the probability estimate query module is connected to the A register updating module, the A register updating module is respectively connected to the context updating module and the C register updating module, an the C register updating module is connected to the byte output module. The invention method can improve the coding efficiency, simplify the circuit structure, occupy less area and reduce the cost.
Description
(1) technical field
The present invention relates to a kind of JPEG2000 pipeline arithmetic encoding method and circuit, belong to the Image Compression field.
(2) background technology
JPE62000 is the still image coding algorithm of latest generation, and organizing definite designation by iso standardization is IS015444, has been used in a plurality of fields such as the Internet, image transmission.JPEG2000 adopts with DWT and is transformed to main multiresolution coding, simultaneously, adopt EBCOT (Embedded Block Coder with Optimized Truncation), i.e. the embedded block encoding algorithm that optimization is blocked is to satisfy requirements such as resolution flexible, quality scalability, random access and processing.
EBCOT Tier-1 is made up of Bit-Plane Encoding and arithmetic encoder two parts the coding of wavelet coefficient among the JPEG2000.This arithmetic coding is a kind of entropy coding, and it depends on some " feature " (" context " just cited below) of coding.Bit-Plane Encoding provides input context (CX) and data to be compressed (D) for arithmetic encoder.So this arithmetic encoder is called again based on contextual binary arithmetic coding, its overall coding flow process is: at first based on context mark CX finds out the probability index Index and the big probability symbol M PS (may be 0 or 1) of the small probability symbol of this context correspondence in context table, utilize this probability index in the probability Estimation table, to find out the probability Qe of corresponding LPS then, next whether be that the value of MPS and Qe is encoded according to D, generate compression bit stream.
JPEG2000 standard specified in more detail the flow process that realizes of arithmetic encoder carry out because the flow process that is provided in the standard is serial, be fit to software more and realize that execution speed is relatively slow.When realizing, need the data of could encoding of a plurality of cycles, inefficiency according to normal process with hardware.Existing arithmetic coding hardware implementation method is though reach certain requirement on the high-speed real-time processing requirements; Owing to the complexity of algorithm itself, it consumes more on resource is used simultaneously, and cost is higher.As publication number is that CN1675842, name are called the example for this reason of applying for a patent promptly of ' method and apparatus of arithmetic coding '.Though what have has carried out local optimum, does not provide whole solution, publication number is that CN1953548, name are called applying for a patent of ' system and the method thereof of accelerating the arithmetic coding processing speed ' and promptly belong to this kind situation.
(3) summary of the invention
For overcome prior art defective and deficiency, the invention provides a kind of JPEG2000 pipeline arithmetic encoding method and circuit, to solve the problem that occurs in the high-speed real-time image compression process.
A kind of JPEG2000 pipeline arithmetic encoding method is finished arithmetic coding through the level Four streamline, it is characterized in that step is as follows:
1, first order streamline: be implemented under the current context CX, the inquiry and the renewal of the probability Estimation value of data D to be compressed, it is input as context CX, data D to be compressed and renormalization signal Renorm; Context CX inquires about the CX state table and obtains probability Estimation table index Index and big probability symbol mps, and they are used for reading the probability Estimation table respectively and judge that next stage is carried out big probability encoding or small probability is encoded; Renormalization signal Renorm then be used for the sign whether the context state table is upgraded; Situation for continuous input same context CX, need CX is delayed time one-period with a register, if first CX causes renormalization (producing signal Renorm), index is directly delivered to the probability Estimation table to the NextState that upgrades by MUX so, no longer removes to read the CX state table; The CX state table then still upgrades; Whether the external output probability estimated value of this level production line Qe and judgement band packed data D are the small probability symbol selection signal mps_sel of small probability symbol gained.
2, second level streamline: realize the renewal of interval register A, it is input as probability Estimation value Qe, leading remainder LZ and judges whether band packed data D is the small probability symbol selection signal mps_sel of small probability symbol gained; If small probability symbol, then A=Qe; Otherwise A=A-Qe; In cataloged procedure, if interval register A less than 0x8000, then needs to carry out renormalization (Renormalize) operation, export renormalization signal Renorm simultaneously, to upgrade the context state table, guarantee that probability is greater than or equal to 0 x 8000 at interval; This level production line is externally exported renormalization signal Renorm.
3, third level streamline: realize the renewal of code registers C, it is input as probability Estimation value Qe and judges whether band packed data D is the small probability symbol selection signal mps_sel of small probability symbol gained; It need carry out synchronous renormalization (Renormalize) operation with interval register A, if the small probability symbol, then C remains unchanged; Otherwise C=C+Qe; The external dateout C_result value of this level production line.
4, fourth stage streamline: realize byte-extraction and output, when C register shift value more than or equal to 27 the time, if when needing output two byte OutH, OutL OutH or OutL byte to equal 0xFF, need after this byte, insert character ' 0 ' in the residue character; When C register shift value less than 27 more than or equal to 19 the time, need byte OutL of output, if when the OutL byte equals 0xFF, need after this byte, insert character ' 0 ' in the residue character; When C register shift value does not have byte output less than 19 the time.The external output encoder byte of this module OutL and (or) OutH.
The employed circuit of a kind of above-mentioned JPEG2000 pipeline arithmetic encoding method, comprising context state table inquiry update module, probability Estimation enquiry module, A-register update module, C register update module and byte output module, serves as the main first order flow line circuit of forming with context status table update module and probability Estimation enquiry module wherein; With A-register update module, C register update module and byte output module serve as main constitute respectively successively second and third, the level Four flow line circuit, it is characterized in that the level Four flow line circuit is connected successively, be that context state table inquiry update module is connected with the probability Estimation enquiry module, the probability Estimation enquiry module is connected with the A-register update module, the A-register update module is connected with C register update module, C register update module connects the byte output module, and the A-register update module is connected with the updating context module.
Described first order flow line circuit also comprise data selector M1 and M2, data comparator, register, exclusive-OR operator and and arithmetic unit, wherein context state table inquiry update module comprises the context state table; The probability Estimation enquiry module comprises the probability Estimation table; This level production line is input as context CX, data D to be compressed and renormalization signal Renorm; Context state table input data are context CX, renormalization signal Renorm, register output and data selector M2 output, and output connects exclusive-OR operator and data selector M1 input respectively; The big probability symbol M of the output ps of data D to be compressed and context state table inquiry update module is connected to exclusive-OR operator and exports mps_sel as input/output terminal as this level production line; Data selector M1 input connect the output of state table hereinafter probability Estimation table index Index, with the output of arithmetic unit output and data selector M2; The output of probability Estimation table input termination data selector M1, the input of output termination data selector M2 and as the output Qe of this level production line, LZ; The data comparator input connects hereinafter CX and register output, output termination and arithmetic unit; With data comparator output of arithmetic unit input termination and renormalization signal Renorm, output termination data selector M1.This module is to second level streamline output probability value Qe, leading remainder LZ and judge whether band packed data D is the mps_sel of small probability symbol gained.
Described context state table is to use the RAM of 19*8 to realize.Context CX is that RAM reads the address, renormalization signal Renorm is that RAM writes enable signal, the register output is that RAM write address, data selector M2 output are the RAM data input pin, and exclusive-OR operator and data selector M1 input are the RAM data output end.
Described probability Estimation table is to use the ROM of 47*40 to realize.The output of data selector M1 is the ROM address, the output Qe of the input of data selector M2 and this level production line, and LZ is the ROM dateout.
Described second level flow line circuit comprises exclusive-OR operator, subtracter block S1 and S2, doubly takes advantage of module, leading zero detection module, inverter, data selector and barrel shift register; This level production line is input as waterline output probability value Qe, leading remainder LZ and judges whether band packed data D is the small probability symbol selection signal mps_sel of small probability symbol gained; Exclusive-OR operator input termination small probability symbol is selected the output of signal mps_sel and subtracter block S1, and exclusive-OR operator is exported the input of termination data selector and selected signal flag_sel as the output interval of this level production line; Subtracter block S1 input is for doubly taking advantage of module (its input is probable value Qe) output and A-register output, and subtracter block S1 output is the exclusive-OR operator input; Subtracter block S2 input is A-register output and probable value Qe, and output connects data selector; The data selector input is probable value Qe, subtracter block S2 output and exclusive-OR operator output, and the data selector output connects leading zero detection module, inverter and barrel shift register; Leading zero detection module input is that the data selector output is the highest two, leading remainder LZ, small probability symbol selection signal mps_sel, the output displacement numerical value Nshift of output termination barrel shift register input and this level production line; The inverter input is a data selector output highest order, and output is renormalization signal Renorm; Barrel shift register input is data selector output, leading zero detection module output, barrel shift register output termination register A input.This level production line is selected signal flag_sel and displacement numerical value Nshift to first order streamline output renormalization signal Renorm to the streamline output interval exchange of back.
Described times is taken advantage of module is a lt shift register.
Described leading zero detection module is made up of data selector and decoder.Decoder input termination data selector output is the highest two, decoder output termination data selector input; The data selector input meets leading remainder LZ, judges signal mps_sel and decoder output that the data selector output is this module output.
The register that can in a clock cycle, realize rapid traverse that described barrel shift register is made up of combinational logic.
Described third level flow line circuit comprises that C register update module realizes the renewal of register C, and its circuit structure is identical with second level pipelined circuit.Flag_sel selects the numerical value that needs shift operation by MUX with the interval selection signal, delivers to the barrel shift register, and C is shifted.Displacement numerical value is sent updating value Nshift by second level streamline.This module need be to fourth stage streamline output register C_result value.
Described fourth stage streamline also comprises adder Module A1 and A2, mask module, counter, barrel shift register module, subtracter block and byte-extraction module; The mask module input is C_result and displacement numerical value Nshift, output termination barrel shift register input; Adder Module A1 input is displacement numerical value Nshift, output termination subtracter block input; Adder Module A2 input termination register module output and barrel shift register output, adder Module A2 output termination byte output module; Barrel shift register input termination mask module output sum counter output; Subtracter block input termination adder A1 and byte-extraction module output, subtracter block output termination counter input; Counter input termination subtracter output, counter output connects adder Module A1 input and barrel shift register module input; The byte-extraction module input connects adder Module A1 output and adder Module A2 output, byte-extraction module output termination subtracter block input, register input and the output of this level production line OutL, OutH.
Described mask module is promptly only got the highest Nshift position, and the residue low data is shielded.C_result and high Nshift position are that 1 remaining bit is 0 data and obtain.
Described byte output module is made up of data comparator C1 and C2, byte output control module.Data comparator C1 input termination adder Module A1 output and numeral 27, output termination byte output control module input; Data comparator C2 input termination adder Module A1 output and numeral 19, output termination byte output control module input.When the CT value more than or equal to 27 the time, need output two byte OutH, OutL, if when OutH or OutL byte equal 0xFF, need after this byte, insert character ' 0 ' in the residue character; When CT less than 27 more than or equal to 19 the time, need byte OutL of output, if the OutL byte when 0xFF, need be inserted character ' 0 ' in the residue character after this byte; When CT does not have byte output less than 19 the time.The external output encoder byte of this module OutL and (or) OutH.
Context state table inquiry update module and probability Estimation enquiry module have been formed first order streamline in the foregoing circuit, the A-register update module is formed second level streamline, C register update module is formed third level streamline, and byte output module etc. are formed fourth stage streamline.This method has been carried out abbreviation and improvement to the normal process among the JPEG2000, realizes to be more suitable for hardware circuit.The mode that has proposed combinational logic and look-up table combination is carried out the leading zero-bit testing circuit of new logic and A-register more in advance under the continuous CX state, solve the problem in the processes such as the renewal of context (CX) state table, normalization and byte output, improved code efficiency.Simultaneously, the algorithm of a plurality of critical paths is optimized, improved the operating frequency of system.The present invention is applicable in high speed JPEG 2000 image compression systems.
The invention has the beneficial effects as follows:
1, the mode that the present invention proposes combinational logic and look-up table combination is carried out more new logic, the leading zero-bit testing circuit of A-register in advance under the continuous CX state, and uses byte output buffer technology, and byte output is finished in one-period.Shorten the time-delay of critical path, improved code efficiency.
2, the present invention has adapted to the application scenario of image compression high speed data rate, can be operated on the higher frequency, by realizing, can obtain to satisfy the demand of high speed operation on the frequency that this module can be operated in 112MHz at the FP6A of AlteraEP2C35F series.
3, design improvement of the present invention complicated logic determines in the standard, physical circuit has been carried out abbreviation, make circuit structure simple, area occupied is less, realize that at the FPGA of AlteraEP2C35F series the result shows, this device has only taken 536 among this FPGA33216 LE, 1728 bytes in storage resources 33216 bytes.
(4) Figure of description
Fig. 1 is the arithmetic coding circuit block diagram.
Wherein, 1, context state table inquiry update module; 2, probability Estimation enquiry module; 3, A-register update module; 4, C register update module; 5, byte output module.
Fig. 2 is a first order pipelined circuit schematic diagram.
Wherein, 6 context state tables inquiry update module; 7, data selector M1 and M2; 8, exclusive-OR operator; 9, probability Estimation enquiry module; 10 and arithmetic unit; 11, data comparator.
Fig. 3 is second level pipelined circuit schematic diagram (third level pipelined circuit figure is identical therewith).
Wherein, 12, exclusive-OR operator; 13, doubly take advantage of module; 14, subtracter block S1 and S2; 15, inverter; 16, leading zero detection module; 17, barrel shift register; 18, data selector.
Fig. 4 is a fourth stage pipelined circuit schematic diagram.
Wherein, 19, adder Module A1 and A2; 20, counter; 21, mask module; 22, subtracter block; 23, byte-extraction module; 24, barrel shift register module.
Fig. 5 is an arithmetic coding method FB(flow block) of the present invention, and wherein, 25-28 has represented each step of this method in order.
Wherein, 25, first order streamline; 26, second level streamline; 27, third level streamline; 28, fourth stage streamline.
(5) embodiment
The invention will be further described below in conjunction with accompanying drawing and embodiment, but be not limited thereto.
Embodiment 1:(method embodiment)
A kind of JPEG2000 pipeline arithmetic encoding method as shown in Figure 5, is finished arithmetic coding through the level Four streamline, it is characterized in that step is as follows:
25, first order streamline: be implemented under the current context CX, the inquiry and the renewal of the probability Estimation value of data D to be compressed, it is input as context CX, data D to be compressed and renormalization signal Renorm; Context CX inquires about the CX state table and obtains probability Estimation table index Index and big probability symbol mps, and they are used for reading the probability Estimation table respectively and judge that next stage is carried out big probability encoding or small probability is encoded; Renormalization signal Renorm then be used for the sign whether the context state table is upgraded; Situation for continuous input same context CX, need CX is delayed time one-period with a register, if first CX causes renormalization (producing signal Renorm), index is directly delivered to the probability Estimation table to the NextState that upgrades by MUX so, no longer removes to read the CX state table; The CX state table then still upgrades; Whether the external output probability estimated value of this level production line Qe and judgement band packed data D are the small probability symbol selection signal mps_sel of small probability symbol gained.
26, second level streamline: realize the renewal of interval register A, it is input as probability Estimation value Qe, leading remainder LZ and judges whether band packed data D is the small probability symbol selection signal mps_sel of small probability symbol gained; If small probability symbol, then A=Qe; Otherwise A=A-Qe; In cataloged procedure, if interval register A less than 0 x 8000, then needs to carry out renormalization (Renormalize) operation, export renormalization signal Renorm simultaneously, to upgrade the context state table, guarantee that probability is greater than or equal to 0 x 8000 at interval.This level production line is externally exported renormalization signal Renorm.
27, third level streamline: realize the renewal of code registers C, it is input as probability Estimation value Qe and judges whether band packed data D is the small probability symbol selection signal mps_sel of small probability symbol gained; It need carry out synchronous renormalization (Renormalize) operation with interval register A, if the small probability symbol, then C remains unchanged; Otherwise C=C+Qe; The external dateout C_result value of this level production line.
28, fourth stage streamline: realize byte-extraction and output, when C register shift value more than or equal to 27 the time, need output two byte OutH, OutL,, need after this byte, insert character ' 0 ' in the residue character if when OutH or OutL byte equal 0 x FF; When C register shift value less than 27 more than or equal to 19 the time, need byte OutL of output, if when the OutL byte equals 0 x FF, need after this byte, insert character ' 0 ' in the residue character; When C register shift value does not have byte output less than 19 the time.The external output encoder byte of this module OutL and (or) OutH.
Embodiment 2:(circuit embodiments)
The employed circuit of a kind of above-mentioned JPEG2000 pipeline arithmetic encoding method, as shown in Figure 1, comprising context state table inquiry update module 1, probability Estimation enquiry module 2, A-register update module 3, C register update module 4 and byte output module 5, serves as the main first order flow line circuit of forming with context status table update module 1 and probability Estimation enquiry module 2 wherein; With A-register update module 3, C register update module 4 and byte output module 5 serve as main constitute respectively successively second and third, the level Four flow line circuit, it is characterized in that the level Four flow line circuit is connected successively, be that context state table inquiry update module 1 is connected probability Estimation enquiry module 2 and is connected A-register update module 3 with A-register update module 3 and is connected with C register update module 4 with probability Estimation enquiry module 2, C register update module 4 connects byte output module 5, and A-register update module 3 is connected with updating context module 1.
As shown in Figure 2, first order flow line circuit also comprise data selector 7 be M1 and M2, data comparator 11, register, exclusive-OR operator 8 and with arithmetic unit 10, wherein context state table inquiry update module 6 comprises the context state table; Probability Estimation enquiry module 9 comprises the probability Estimation table; This level production line is input as context CX, data D to be compressed and renormalization signal Renorm; Context state table input data are context CX, renormalization signal Renorm, register output and data selector M2 output, and output connects exclusive-OR operator and data selector M1 input respectively; The big probability symbol M of the output ps of data D to be compressed and context state table inquiry update module 6 is connected to exclusive-OR operator 8 and exports mps_sel as input/output terminal as this level production line; Data selector M1 input connect the output of state table hereinafter probability Estimation table index Index, with the output of arithmetic unit 10 outputs and data selector M2; The output of probability Estimation table input termination data selector M1, the input of output termination data selector M2 and as the output Qe of this level production line, LZ; Data comparator 11 inputs connect hereinafter CX and register output, output termination and arithmetic unit 10; With arithmetic unit 10 input termination data comparators 11 output and renormalization signal Renorm, output termination data selector M1.This module is to second level streamline output probability value Qe, leading remainder LZ and judge whether band packed data D is the mps_sel of small probability symbol gained.
As shown in Figure 3, second level flow line circuit comprises that exclusive-OR operator 12, subtracter block 14 are S1 and S2, doubly take advantage of module 13, leading zero detection module 16, inverter 15, data selector 18 and barrel shift register 17; This level production line is input as waterline output probability value Qe, leading remainder LZ and judges whether band packed data D is the small probability symbol selection signal mps_sel of small probability symbol gained; Exclusive-OR operator 12 input termination small probability symbols are selected the output of signal mps_sel and subtracter block S1, and exclusive-OR operator 12 is exported the input of termination data selectors 18 and selected signal flag_sel as the output interval of this level production line; Subtracter block S1 input is for doubly taking advantage of module 13 (its input is probable value Qe) output and A-register output, and subtracter block S1 output is exclusive-OR operator 12 inputs; Subtracter block S2 input is A-register output and probable value Qe, and output connects data selector 18; Data selector 18 inputs are probable value Qe, subtracter block S2 output and exclusive-OR operator 12 outputs, and data selector 18 outputs connect leading zero detection module 16, inverter 15 and barrel shift register 17; Leading zero detection module 16 inputs are that data selector 18 outputs are the highest two, leading remainder LZ, small probability symbol selection signal mps_sel, the output displacement numerical value Nshift of output termination barrel shift register 17 inputs and this level production line; Inverter 15 inputs are data selector 18 output highest orders, and output is renormalization signal Renorm; Barrel shift register 17 inputs are data selector 18 outputs, leading zero detection module 16 outputs, barrel shift register 17 output termination register A inputs.This level production line is selected signal flag_sel and displacement numerical value Nshift to first order streamline output renormalization signal Renorm to the streamline output interval of back.
Described leading zero detection module 16 is made up of data selector and decoder, and decoder input termination data selector output is the highest two, decoder output termination data selector input; The data selector input meets leading remainder LZ, judges signal mps_sel and decoder output that the data selector output is this module output.
Described third level flow line circuit comprises that C register update module 4 realizes the renewal of register C, and its circuit structure is identical with second level pipelined circuit.
As shown in Figure 4, fourth stage streamline comprises that also adder Module 19 is A1 and A2, mask module 21, counter 20, barrel shift register module 24, subtracter block 22, register and byte-extraction module 23, mask module 21 inputs are C_result and Nshift, output termination barrel shift register 24 inputs; Adder Module A1 input is Nshift, output termination subtracter block 22 inputs; Adder Module A2 input termination register output and barrel shift register 24 outputs, adder Module A2 output termination byte-extraction module 23; Barrel shift register 24 input termination mask modules 21 output sum counters 20 outputs; Subtracter block 22 input termination adder A1 and byte-extraction module 23 outputs, subtracter block 22 output termination counters 20 inputs; Counter 20 input termination subtracter block 22 outputs, counter 20 output termination adder Module A1 input and barrel shift register module 24 inputs; Byte-extraction module 23 input termination adder Module A1 output and adder Module A2 outputs, byte-extraction module 23 output termination subtracter block 22 inputs, register input and the output of this level production line OutL, OutH.
Described byte output module is made up of data comparator C1 and C2, byte output control module, data comparator C1 input termination adder Module A1 output and numeral 27, output termination byte output control module input; Data comparator C2 input termination adder Module A1 output and numeral 19, output termination byte output control module input.
Claims (8)
1, a kind of JPEG2000 pipeline arithmetic encoding method is finished arithmetic coding through the level Four streamline, it is characterized in that step is as follows:
1) first order streamline: be implemented under the current context CX, the inquiry and the renewal of the probability Estimation value of data D to be compressed, it is input as context CX, data D to be compressed and renormalization signal Renorm; Context CX inquires about the CX state table and obtains probability Estimation table index Index and big probability symbol mps, and they are used for reading the probability Estimation table respectively and judge that next stage is carried out big probability encoding or small probability is encoded; Renormalization signal Renorm then be used for the sign whether the context state table is upgraded; Situation for continuous input same context CX, need CX is delayed time one-period with a register,, produce signal Renorm if first CX causes renormalization, index is directly delivered to the probability Estimation table to the NextState that upgrades by MUX so, no longer removes to read the CX state table; The CX state table then still upgrades;
2) second level streamline: realize the renewal of interval register A, it is input as probability Estimation value Qe, leading remainder LZ and judges whether data D to be compressed is the small probability symbol selection signal mps_sel of small probability symbol gained; If small probability symbol, then A=Qe; Otherwise A=A-Qe; In cataloged procedure, if interval register A less than 0x8000, then needs to carry out the renormalization operation, export renormalization signal Renorm simultaneously, to upgrade the context state table, guarantee that probability is greater than or equal to 0x8000 at interval;
3) third level streamline: realize the renewal of code registers C, it is input as probability Estimation value Qe and judges whether data D to be compressed is the small probability symbol selection signal mps_sel of small probability symbol gained; It need carry out synchronous renormalization operation with interval register A, if the small probability symbol, then C remains unchanged; Otherwise C=C+Qe; The external dateout C_result value of this level production line;
4) fourth stage streamline: realize byte-extraction and output, when C register shift value more than or equal to 27 the time, need output two byte OutH, OutL,, need after this byte, insert character ' 0 ' in the residue character if when OutH or OutL byte equal 0xFF; When C register shift value less than 27 more than or equal to 19 the time, need byte OutL of output, if when the OutL byte equals 0xFF, need after this byte, insert character ' 0 ' in the residue character; When C register shift value does not have byte output less than 19 the time.
2, the employed circuit of a kind of JPEG2000 pipeline arithmetic encoding method as claimed in claim 1, comprising context state table inquiry update module, probability Estimation enquiry module, A-register update module, C register update module and byte output module, serves as the main first order flow line circuit of forming with context status table update module and probability Estimation enquiry module wherein; With A-register update module, C register update module and byte output module serve as main constitute respectively successively second and third, the level Four flow line circuit, it is characterized in that the level Four flow line circuit is connected successively, be that context state table inquiry update module is connected with the probability Estimation enquiry module, the probability Estimation enquiry module is connected with the A-register update module, the A-register update module is connected with C register update module, C register update module connects the byte output module, and the A-register update module is connected with the updating context module.
3, circuit as claimed in claim 2, it is characterized in that described first order flow line circuit also comprise data selector M1 and M2, data comparator, register, exclusive-OR operator and and arithmetic unit, wherein context state table inquiry update module comprises the context state table; The probability Estimation enquiry module comprises the probability Estimation table; This level production line is input as context CX, data D to be compressed and renormalization signal Renorm; Context state table input data are context CX, renormalization signal Renorm, register output and data selector M2 output, and output connects exclusive-OR operator and data selector M1 input respectively; The big probability symbol M of the output ps of data D to be compressed and context state table inquiry update module is connected to exclusive-OR operator as input, and output is as this level production line output mps_sel; Data selector M1 input connect the output of state table hereinafter probability Estimation table index Index, with the output of arithmetic unit output and data selector M2; The output of probability Estimation table input termination data selector M1, the input of output termination data selector M2 and as the output Qe of this level production line, LZ; The data comparator input connects hereinafter CX and register output, output termination and arithmetic unit; With data comparator output of arithmetic unit input termination and renormalization signal Renorm, output termination data selector M1.
4, circuit as claimed in claim 2 is characterized in that described second level flow line circuit comprises exclusive-OR operator, subtracter block S1 and S2, doubly takes advantage of module, leading zero detection module, inverter, data selector and barrel shift register; This level production line is input as waterline output probability value Qe, leading remainder LZ and judges whether band packed data D is the small probability symbol selection signal mps_sel of small probability symbol gained; Exclusive-OR operator input termination small probability symbol is selected the output of signal mps_sel and subtracter block S1, and exclusive-OR operator is exported the input of termination data selector and selected signal flag_sel as the output interval of this level production line; Subtracter block S1 input is for doubly taking advantage of module (its input is probable value Qe) output and A-register output, and subtracter block S1 output is the exclusive-OR operator input; Subtracter block S2 input is A-register output and probable value Qe, and output connects data selector; The data selector input is probable value Qe, subtracter block S2 output and exclusive-OR operator output, and the data selector output connects leading zero detection module, inverter and barrel shift register; Leading zero detection module input is that the data selector output is the highest two, leading remainder LZ, small probability symbol selection signal mps_sel, the output displacement numerical value Nshift of output termination barrel shift register input and this level production line; The inverter input is a data selector output highest order, and output is renormalization signal Renorm; Barrel shift register input is data selector output, leading zero detection module output, barrel shift register output termination register A input.
5, the second level as claimed in claim 4 flow line circuit, it is characterized in that described leading zero detection module is made up of data selector and decoder, decoder input termination data selector output is the highest two, decoder output termination data selector input; The data selector input meets leading remainder LZ, judges signal mps_sel and decoder output that the data selector output is this module output.
6, circuit as claimed in claim 2 is characterized in that described third level pipelined circuit is identical with the described second level of claim 4 pipelined circuit.
7, circuit as claimed in claim 2 is characterized in that described fourth stage streamline also comprises adder Module A1 and A2, mask module, counter, barrel shift register module, subtracter block and byte-extraction module; The mask module input is C_result and displacement numerical value Nshift, output termination barrel shift register input; Adder Module A1 input is displacement numerical value Nshift, output termination subtracter block input; Adder Module A2 input termination register module output and barrel shift register output, adder Module A2 output termination byte output module; Barrel shift register input termination mask module output sum counter output; Subtracter block input termination adder A1 and byte-extraction module output, subtracter block output termination counter input; Counter input termination subtracter output, counter output connects adder Module A1 input and barrel shift register module input; The byte-extraction module input connects adder Module A1 output and adder Module A2 output, byte-extraction module output termination subtracter block input, register input and the output of this level production line OutL, OutH.
8, circuit as claimed in claim 2 is characterized in that described byte output module is made up of data comparator C1 and C2, byte output control module.Data comparator C1 input termination adder Module A1 output and numeral 27, output termination byte output control module input; Data comparator C2 input termination adder Module A1 output and numeral 19, output termination byte output control module input.
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| CN101848387A (en) * | 2010-03-19 | 2010-09-29 | 西安电子科技大学 | Method for determining arithmetic encoding probability interval value based on JPEG (Joint Photographic Experts Group) 2000 standard |
| CN101771879B (en) * | 2010-01-28 | 2011-08-17 | 清华大学 | Parallel normalized coding realization circuit based on CABAC and coding method |
| CN102176750A (en) * | 2011-03-10 | 2011-09-07 | 西安电子科技大学 | High-performance adaptive binary arithmetic encoder |
| CN101848311B (en) * | 2010-02-21 | 2011-09-28 | 哈尔滨工业大学 | JPEG2000 EBCOT encoder based on Avalon bus |
| CN102348111A (en) * | 2010-07-30 | 2012-02-08 | 国家卫星气象中心 | Data compression structure identification code used for stationary weather satellite data broadcasting |
| US9450606B1 (en) | 2015-10-01 | 2016-09-20 | Seagate Technology Llc | Data matching for hardware data compression |
| CN107093162A (en) * | 2017-04-28 | 2017-08-25 | 天津大学 | A kind of MQ encoders applied to JPEG2000 |
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- 2009-01-19 CN CN 200910013661 patent/CN101489128A/en active Pending
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101771879B (en) * | 2010-01-28 | 2011-08-17 | 清华大学 | Parallel normalized coding realization circuit based on CABAC and coding method |
| CN101848311B (en) * | 2010-02-21 | 2011-09-28 | 哈尔滨工业大学 | JPEG2000 EBCOT encoder based on Avalon bus |
| CN101848387A (en) * | 2010-03-19 | 2010-09-29 | 西安电子科技大学 | Method for determining arithmetic encoding probability interval value based on JPEG (Joint Photographic Experts Group) 2000 standard |
| CN102348111A (en) * | 2010-07-30 | 2012-02-08 | 国家卫星气象中心 | Data compression structure identification code used for stationary weather satellite data broadcasting |
| CN102176750A (en) * | 2011-03-10 | 2011-09-07 | 西安电子科技大学 | High-performance adaptive binary arithmetic encoder |
| US9450606B1 (en) | 2015-10-01 | 2016-09-20 | Seagate Technology Llc | Data matching for hardware data compression |
| CN107093162A (en) * | 2017-04-28 | 2017-08-25 | 天津大学 | A kind of MQ encoders applied to JPEG2000 |
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