CN101489128A - JPEG2000 pipeline arithmetic encoding method and circuit - Google Patents

JPEG2000 pipeline arithmetic encoding method and circuit Download PDF

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CN101489128A
CN101489128A CN 200910013661 CN200910013661A CN101489128A CN 101489128 A CN101489128 A CN 101489128A CN 200910013661 CN200910013661 CN 200910013661 CN 200910013661 A CN200910013661 A CN 200910013661A CN 101489128 A CN101489128 A CN 101489128A
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output
register
input
output terminal
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马磊
李运田
刘江
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SHANDONG SHANDA OUMA SOFTWARE CO Ltd
Shandong University
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SHANDONG SHANDA OUMA SOFTWARE CO Ltd
Shandong University
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Abstract

一种JPEG2000流水线算术编码方法和电路，属图像压缩技术领域，经过四级流水线完成算术编码，其电路包括上下文状态表查询更新模块和概率估计查询模块、A寄存器更新模块、C寄存器更新模块、字节输出模块，分别构成四级流水线电路，上下文状态表查询更新模块与概率估计查询模块连接，概率估计查询模块与A寄存器更新模块连接，A寄存器更新模块分别与上下文更新模块和C寄存器更新模块连接，C寄存器更新模块连接字节输出模块。本发明方法可提高编码效率，电路结构简化，占用面积较少，可减少成本。

Figure 200910013661

A JPEG2000 pipeline arithmetic coding method and circuit, which belong to the technical field of image compression, complete the arithmetic coding through a four-stage pipeline, and the circuit includes a context state table query update module, a probability estimation query module, an A register update module, a C register update module, word Section output modules, which respectively constitute a four-stage pipeline circuit, the context state table query update module is connected with the probability estimation query module, the probability estimation query module is connected with the A register update module, and the A register update module is respectively connected with the context update module and the C register update module , the C register update module is connected to the byte output module. The method of the invention can improve coding efficiency, simplify circuit structure, occupy less area and reduce cost.

Figure 200910013661

Description

A kind of JPEG2000 pipeline arithmetic encoding method and circuit
(1) technical field
The present invention relates to a kind of JPEG2000 pipeline arithmetic encoding method and circuit, belong to the Image Compression field.
(2) background technology
JPE62000 is the still image coding algorithm of latest generation, and organizing definite designation by iso standardization is IS015444, has been used in a plurality of fields such as the Internet, image transmission.JPEG2000 adopts with DWT and is transformed to main multiresolution coding, simultaneously, adopt EBCOT (Embedded Block Coder with Optimized Truncation), i.e. the embedded block encoding algorithm that optimization is blocked is to satisfy requirements such as resolution flexible, quality scalability, random access and processing.
EBCOT Tier-1 is made up of Bit-Plane Encoding and arithmetic encoder two parts the coding of wavelet coefficient among the JPEG2000.This arithmetic coding is a kind of entropy coding, and it depends on some " feature " (" context " just cited below) of coding.Bit-Plane Encoding provides input context (CX) and data to be compressed (D) for arithmetic encoder.So this arithmetic encoder is called again based on contextual binary arithmetic coding, its overall coding flow process is: at first based on context mark CX finds out the probability index Index and the big probability symbol M PS (may be 0 or 1) of the small probability symbol of this context correspondence in context table, utilize this probability index in the probability Estimation table, to find out the probability Qe of corresponding LPS then, next whether be that the value of MPS and Qe is encoded according to D, generate compression bit stream.
JPEG2000 standard specified in more detail the flow process that realizes of arithmetic encoder carry out because the flow process that is provided in the standard is serial, be fit to software more and realize that execution speed is relatively slow.When realizing, need the data of could encoding of a plurality of cycles, inefficiency according to normal process with hardware.Existing arithmetic coding hardware implementation method is though reach certain requirement on the high-speed real-time processing requirements; Owing to the complexity of algorithm itself, it consumes more on resource is used simultaneously, and cost is higher.As publication number is that CN1675842, name are called the example for this reason of applying for a patent promptly of ' method and apparatus of arithmetic coding '.Though what have has carried out local optimum, does not provide whole solution, publication number is that CN1953548, name are called applying for a patent of ' system and the method thereof of accelerating the arithmetic coding processing speed ' and promptly belong to this kind situation.
(3) summary of the invention
For overcome prior art defective and deficiency, the invention provides a kind of JPEG2000 pipeline arithmetic encoding method and circuit, to solve the problem that occurs in the high-speed real-time image compression process.
A kind of JPEG2000 pipeline arithmetic encoding method is finished arithmetic coding through the level Four streamline, it is characterized in that step is as follows:
1, first order streamline: be implemented under the current context CX, the inquiry and the renewal of the probability Estimation value of data D to be compressed, it is input as context CX, data D to be compressed and renormalization signal Renorm; Context CX inquires about the CX state table and obtains probability Estimation table index Index and big probability symbol mps, and they are used for reading the probability Estimation table respectively and judge that next stage is carried out big probability encoding or small probability is encoded; Renormalization signal Renorm then be used for the sign whether the context state table is upgraded; Situation for continuous input same context CX, need CX is delayed time one-period with a register, if first CX causes renormalization (producing signal Renorm), index is directly delivered to the probability Estimation table to the NextState that upgrades by MUX so, no longer removes to read the CX state table; The CX state table then still upgrades; Whether the external output probability estimated value of this level production line Qe and judgement band packed data D are the small probability symbol selection signal mps_sel of small probability symbol gained.
2, second level streamline: realize the renewal of interval register A, it is input as probability Estimation value Qe, leading remainder LZ and judges whether band packed data D is the small probability symbol selection signal mps_sel of small probability symbol gained; If small probability symbol, then A=Qe; Otherwise A=A-Qe; In cataloged procedure, if interval register A less than 0x8000, then needs to carry out renormalization (Renormalize) operation, export renormalization signal Renorm simultaneously, to upgrade the context state table, guarantee that probability is greater than or equal to 0 x 8000 at interval; This level production line is externally exported renormalization signal Renorm.
3, third level streamline: realize the renewal of code registers C, it is input as probability Estimation value Qe and judges whether band packed data D is the small probability symbol selection signal mps_sel of small probability symbol gained; It need carry out synchronous renormalization (Renormalize) operation with interval register A, if the small probability symbol, then C remains unchanged; Otherwise C=C+Qe; The external dateout C_result value of this level production line.
4, fourth stage streamline: realize byte-extraction and output, when C register shift value more than or equal to 27 the time, if when needing output two byte OutH, OutL OutH or OutL byte to equal 0xFF, need after this byte, insert character ' 0 ' in the residue character; When C register shift value less than 27 more than or equal to 19 the time, need byte OutL of output, if when the OutL byte equals 0xFF, need after this byte, insert character ' 0 ' in the residue character; When C register shift value does not have byte output less than 19 the time.The external output encoder byte of this module OutL and (or) OutH.
The employed circuit of a kind of above-mentioned JPEG2000 pipeline arithmetic encoding method, comprising context state table inquiry update module, probability Estimation enquiry module, A-register update module, C register update module and byte output module, serves as the main first order flow line circuit of forming with context status table update module and probability Estimation enquiry module wherein; With A-register update module, C register update module and byte output module serve as main constitute respectively successively second and third, the level Four flow line circuit, it is characterized in that the level Four flow line circuit is connected successively, be that context state table inquiry update module is connected with the probability Estimation enquiry module, the probability Estimation enquiry module is connected with the A-register update module, the A-register update module is connected with C register update module, C register update module connects the byte output module, and the A-register update module is connected with the updating context module.
Described first order flow line circuit also comprise data selector M1 and M2, data comparator, register, exclusive-OR operator and and arithmetic unit, wherein context state table inquiry update module comprises the context state table; The probability Estimation enquiry module comprises the probability Estimation table; This level production line is input as context CX, data D to be compressed and renormalization signal Renorm; Context state table input data are context CX, renormalization signal Renorm, register output and data selector M2 output, and output connects exclusive-OR operator and data selector M1 input respectively; The big probability symbol M of the output ps of data D to be compressed and context state table inquiry update module is connected to exclusive-OR operator and exports mps_sel as input/output terminal as this level production line; Data selector M1 input connect the output of state table hereinafter probability Estimation table index Index, with the output of arithmetic unit output and data selector M2; The output of probability Estimation table input termination data selector M1, the input of output termination data selector M2 and as the output Qe of this level production line, LZ; The data comparator input connects hereinafter CX and register output, output termination and arithmetic unit; With data comparator output of arithmetic unit input termination and renormalization signal Renorm, output termination data selector M1.This module is to second level streamline output probability value Qe, leading remainder LZ and judge whether band packed data D is the mps_sel of small probability symbol gained.
Described context state table is to use the RAM of 19*8 to realize.Context CX is that RAM reads the address, renormalization signal Renorm is that RAM writes enable signal, the register output is that RAM write address, data selector M2 output are the RAM data input pin, and exclusive-OR operator and data selector M1 input are the RAM data output end.
Described probability Estimation table is to use the ROM of 47*40 to realize.The output of data selector M1 is the ROM address, the output Qe of the input of data selector M2 and this level production line, and LZ is the ROM dateout.
Described second level flow line circuit comprises exclusive-OR operator, subtracter block S1 and S2, doubly takes advantage of module, leading zero detection module, inverter, data selector and barrel shift register; This level production line is input as waterline output probability value Qe, leading remainder LZ and judges whether band packed data D is the small probability symbol selection signal mps_sel of small probability symbol gained; Exclusive-OR operator input termination small probability symbol is selected the output of signal mps_sel and subtracter block S1, and exclusive-OR operator is exported the input of termination data selector and selected signal flag_sel as the output interval of this level production line; Subtracter block S1 input is for doubly taking advantage of module (its input is probable value Qe) output and A-register output, and subtracter block S1 output is the exclusive-OR operator input; Subtracter block S2 input is A-register output and probable value Qe, and output connects data selector; The data selector input is probable value Qe, subtracter block S2 output and exclusive-OR operator output, and the data selector output connects leading zero detection module, inverter and barrel shift register; Leading zero detection module input is that the data selector output is the highest two, leading remainder LZ, small probability symbol selection signal mps_sel, the output displacement numerical value Nshift of output termination barrel shift register input and this level production line; The inverter input is a data selector output highest order, and output is renormalization signal Renorm; Barrel shift register input is data selector output, leading zero detection module output, barrel shift register output termination register A input.This level production line is selected signal flag_sel and displacement numerical value Nshift to first order streamline output renormalization signal Renorm to the streamline output interval exchange of back.
Described times is taken advantage of module is a lt shift register.
Described leading zero detection module is made up of data selector and decoder.Decoder input termination data selector output is the highest two, decoder output termination data selector input; The data selector input meets leading remainder LZ, judges signal mps_sel and decoder output that the data selector output is this module output.
The register that can in a clock cycle, realize rapid traverse that described barrel shift register is made up of combinational logic.
Described third level flow line circuit comprises that C register update module realizes the renewal of register C, and its circuit structure is identical with second level pipelined circuit.Flag_sel selects the numerical value that needs shift operation by MUX with the interval selection signal, delivers to the barrel shift register, and C is shifted.Displacement numerical value is sent updating value Nshift by second level streamline.This module need be to fourth stage streamline output register C_result value.
Described fourth stage streamline also comprises adder Module A1 and A2, mask module, counter, barrel shift register module, subtracter block and byte-extraction module; The mask module input is C_result and displacement numerical value Nshift, output termination barrel shift register input; Adder Module A1 input is displacement numerical value Nshift, output termination subtracter block input; Adder Module A2 input termination register module output and barrel shift register output, adder Module A2 output termination byte output module; Barrel shift register input termination mask module output sum counter output; Subtracter block input termination adder A1 and byte-extraction module output, subtracter block output termination counter input; Counter input termination subtracter output, counter output connects adder Module A1 input and barrel shift register module input; The byte-extraction module input connects adder Module A1 output and adder Module A2 output, byte-extraction module output termination subtracter block input, register input and the output of this level production line OutL, OutH.
Described mask module is promptly only got the highest Nshift position, and the residue low data is shielded.C_result and high Nshift position are that 1 remaining bit is 0 data and obtain.
Described byte output module is made up of data comparator C1 and C2, byte output control module.Data comparator C1 input termination adder Module A1 output and numeral 27, output termination byte output control module input; Data comparator C2 input termination adder Module A1 output and numeral 19, output termination byte output control module input.When the CT value more than or equal to 27 the time, need output two byte OutH, OutL, if when OutH or OutL byte equal 0xFF, need after this byte, insert character ' 0 ' in the residue character; When CT less than 27 more than or equal to 19 the time, need byte OutL of output, if the OutL byte when 0xFF, need be inserted character ' 0 ' in the residue character after this byte; When CT does not have byte output less than 19 the time.The external output encoder byte of this module OutL and (or) OutH.
Context state table inquiry update module and probability Estimation enquiry module have been formed first order streamline in the foregoing circuit, the A-register update module is formed second level streamline, C register update module is formed third level streamline, and byte output module etc. are formed fourth stage streamline.This method has been carried out abbreviation and improvement to the normal process among the JPEG2000, realizes to be more suitable for hardware circuit.The mode that has proposed combinational logic and look-up table combination is carried out the leading zero-bit testing circuit of new logic and A-register more in advance under the continuous CX state, solve the problem in the processes such as the renewal of context (CX) state table, normalization and byte output, improved code efficiency.Simultaneously, the algorithm of a plurality of critical paths is optimized, improved the operating frequency of system.The present invention is applicable in high speed JPEG 2000 image compression systems.
The invention has the beneficial effects as follows:
1, the mode that the present invention proposes combinational logic and look-up table combination is carried out more new logic, the leading zero-bit testing circuit of A-register in advance under the continuous CX state, and uses byte output buffer technology, and byte output is finished in one-period.Shorten the time-delay of critical path, improved code efficiency.
2, the present invention has adapted to the application scenario of image compression high speed data rate, can be operated on the higher frequency, by realizing, can obtain to satisfy the demand of high speed operation on the frequency that this module can be operated in 112MHz at the FP6A of AlteraEP2C35F series.
3, design improvement of the present invention complicated logic determines in the standard, physical circuit has been carried out abbreviation, make circuit structure simple, area occupied is less, realize that at the FPGA of AlteraEP2C35F series the result shows, this device has only taken 536 among this FPGA33216 LE, 1728 bytes in storage resources 33216 bytes.
(4) Figure of description
Fig. 1 is the arithmetic coding circuit block diagram.
Wherein, 1, context state table inquiry update module; 2, probability Estimation enquiry module; 3, A-register update module; 4, C register update module; 5, byte output module.
Fig. 2 is a first order pipelined circuit schematic diagram.
Wherein, 6 context state tables inquiry update module; 7, data selector M1 and M2; 8, exclusive-OR operator; 9, probability Estimation enquiry module; 10 and arithmetic unit; 11, data comparator.
Fig. 3 is second level pipelined circuit schematic diagram (third level pipelined circuit figure is identical therewith).
Wherein, 12, exclusive-OR operator; 13, doubly take advantage of module; 14, subtracter block S1 and S2; 15, inverter; 16, leading zero detection module; 17, barrel shift register; 18, data selector.
Fig. 4 is a fourth stage pipelined circuit schematic diagram.
Wherein, 19, adder Module A1 and A2; 20, counter; 21, mask module; 22, subtracter block; 23, byte-extraction module; 24, barrel shift register module.
Fig. 5 is an arithmetic coding method FB(flow block) of the present invention, and wherein, 25-28 has represented each step of this method in order.
Wherein, 25, first order streamline; 26, second level streamline; 27, third level streamline; 28, fourth stage streamline.
(5) embodiment
The invention will be further described below in conjunction with accompanying drawing and embodiment, but be not limited thereto.
Embodiment 1:(method embodiment)
A kind of JPEG2000 pipeline arithmetic encoding method as shown in Figure 5, is finished arithmetic coding through the level Four streamline, it is characterized in that step is as follows:
25, first order streamline: be implemented under the current context CX, the inquiry and the renewal of the probability Estimation value of data D to be compressed, it is input as context CX, data D to be compressed and renormalization signal Renorm; Context CX inquires about the CX state table and obtains probability Estimation table index Index and big probability symbol mps, and they are used for reading the probability Estimation table respectively and judge that next stage is carried out big probability encoding or small probability is encoded; Renormalization signal Renorm then be used for the sign whether the context state table is upgraded; Situation for continuous input same context CX, need CX is delayed time one-period with a register, if first CX causes renormalization (producing signal Renorm), index is directly delivered to the probability Estimation table to the NextState that upgrades by MUX so, no longer removes to read the CX state table; The CX state table then still upgrades; Whether the external output probability estimated value of this level production line Qe and judgement band packed data D are the small probability symbol selection signal mps_sel of small probability symbol gained.
26, second level streamline: realize the renewal of interval register A, it is input as probability Estimation value Qe, leading remainder LZ and judges whether band packed data D is the small probability symbol selection signal mps_sel of small probability symbol gained; If small probability symbol, then A=Qe; Otherwise A=A-Qe; In cataloged procedure, if interval register A less than 0 x 8000, then needs to carry out renormalization (Renormalize) operation, export renormalization signal Renorm simultaneously, to upgrade the context state table, guarantee that probability is greater than or equal to 0 x 8000 at interval.This level production line is externally exported renormalization signal Renorm.
27, third level streamline: realize the renewal of code registers C, it is input as probability Estimation value Qe and judges whether band packed data D is the small probability symbol selection signal mps_sel of small probability symbol gained; It need carry out synchronous renormalization (Renormalize) operation with interval register A, if the small probability symbol, then C remains unchanged; Otherwise C=C+Qe; The external dateout C_result value of this level production line.
28, fourth stage streamline: realize byte-extraction and output, when C register shift value more than or equal to 27 the time, need output two byte OutH, OutL,, need after this byte, insert character ' 0 ' in the residue character if when OutH or OutL byte equal 0 x FF; When C register shift value less than 27 more than or equal to 19 the time, need byte OutL of output, if when the OutL byte equals 0 x FF, need after this byte, insert character ' 0 ' in the residue character; When C register shift value does not have byte output less than 19 the time.The external output encoder byte of this module OutL and (or) OutH.
Embodiment 2:(circuit embodiments)
The employed circuit of a kind of above-mentioned JPEG2000 pipeline arithmetic encoding method, as shown in Figure 1, comprising context state table inquiry update module 1, probability Estimation enquiry module 2, A-register update module 3, C register update module 4 and byte output module 5, serves as the main first order flow line circuit of forming with context status table update module 1 and probability Estimation enquiry module 2 wherein; With A-register update module 3, C register update module 4 and byte output module 5 serve as main constitute respectively successively second and third, the level Four flow line circuit, it is characterized in that the level Four flow line circuit is connected successively, be that context state table inquiry update module 1 is connected probability Estimation enquiry module 2 and is connected A-register update module 3 with A-register update module 3 and is connected with C register update module 4 with probability Estimation enquiry module 2, C register update module 4 connects byte output module 5, and A-register update module 3 is connected with updating context module 1.
As shown in Figure 2, first order flow line circuit also comprise data selector 7 be M1 and M2, data comparator 11, register, exclusive-OR operator 8 and with arithmetic unit 10, wherein context state table inquiry update module 6 comprises the context state table; Probability Estimation enquiry module 9 comprises the probability Estimation table; This level production line is input as context CX, data D to be compressed and renormalization signal Renorm; Context state table input data are context CX, renormalization signal Renorm, register output and data selector M2 output, and output connects exclusive-OR operator and data selector M1 input respectively; The big probability symbol M of the output ps of data D to be compressed and context state table inquiry update module 6 is connected to exclusive-OR operator 8 and exports mps_sel as input/output terminal as this level production line; Data selector M1 input connect the output of state table hereinafter probability Estimation table index Index, with the output of arithmetic unit 10 outputs and data selector M2; The output of probability Estimation table input termination data selector M1, the input of output termination data selector M2 and as the output Qe of this level production line, LZ; Data comparator 11 inputs connect hereinafter CX and register output, output termination and arithmetic unit 10; With arithmetic unit 10 input termination data comparators 11 output and renormalization signal Renorm, output termination data selector M1.This module is to second level streamline output probability value Qe, leading remainder LZ and judge whether band packed data D is the mps_sel of small probability symbol gained.
As shown in Figure 3, second level flow line circuit comprises that exclusive-OR operator 12, subtracter block 14 are S1 and S2, doubly take advantage of module 13, leading zero detection module 16, inverter 15, data selector 18 and barrel shift register 17; This level production line is input as waterline output probability value Qe, leading remainder LZ and judges whether band packed data D is the small probability symbol selection signal mps_sel of small probability symbol gained; Exclusive-OR operator 12 input termination small probability symbols are selected the output of signal mps_sel and subtracter block S1, and exclusive-OR operator 12 is exported the input of termination data selectors 18 and selected signal flag_sel as the output interval of this level production line; Subtracter block S1 input is for doubly taking advantage of module 13 (its input is probable value Qe) output and A-register output, and subtracter block S1 output is exclusive-OR operator 12 inputs; Subtracter block S2 input is A-register output and probable value Qe, and output connects data selector 18; Data selector 18 inputs are probable value Qe, subtracter block S2 output and exclusive-OR operator 12 outputs, and data selector 18 outputs connect leading zero detection module 16, inverter 15 and barrel shift register 17; Leading zero detection module 16 inputs are that data selector 18 outputs are the highest two, leading remainder LZ, small probability symbol selection signal mps_sel, the output displacement numerical value Nshift of output termination barrel shift register 17 inputs and this level production line; Inverter 15 inputs are data selector 18 output highest orders, and output is renormalization signal Renorm; Barrel shift register 17 inputs are data selector 18 outputs, leading zero detection module 16 outputs, barrel shift register 17 output termination register A inputs.This level production line is selected signal flag_sel and displacement numerical value Nshift to first order streamline output renormalization signal Renorm to the streamline output interval of back.
Described leading zero detection module 16 is made up of data selector and decoder, and decoder input termination data selector output is the highest two, decoder output termination data selector input; The data selector input meets leading remainder LZ, judges signal mps_sel and decoder output that the data selector output is this module output.
Described third level flow line circuit comprises that C register update module 4 realizes the renewal of register C, and its circuit structure is identical with second level pipelined circuit.
As shown in Figure 4, fourth stage streamline comprises that also adder Module 19 is A1 and A2, mask module 21, counter 20, barrel shift register module 24, subtracter block 22, register and byte-extraction module 23, mask module 21 inputs are C_result and Nshift, output termination barrel shift register 24 inputs; Adder Module A1 input is Nshift, output termination subtracter block 22 inputs; Adder Module A2 input termination register output and barrel shift register 24 outputs, adder Module A2 output termination byte-extraction module 23; Barrel shift register 24 input termination mask modules 21 output sum counters 20 outputs; Subtracter block 22 input termination adder A1 and byte-extraction module 23 outputs, subtracter block 22 output termination counters 20 inputs; Counter 20 input termination subtracter block 22 outputs, counter 20 output termination adder Module A1 input and barrel shift register module 24 inputs; Byte-extraction module 23 input termination adder Module A1 output and adder Module A2 outputs, byte-extraction module 23 output termination subtracter block 22 inputs, register input and the output of this level production line OutL, OutH.
Described byte output module is made up of data comparator C1 and C2, byte output control module, data comparator C1 input termination adder Module A1 output and numeral 27, output termination byte output control module input; Data comparator C2 input termination adder Module A1 output and numeral 19, output termination byte output control module input.

Claims (8)

1、一种JPEG2000流水线算术编码方法，经过四级流水线完成算术编码，其特征在于步骤如下：1, a kind of JPEG2000 assembly line arithmetic coding method, complete arithmetic coding through four stages of pipelines, it is characterized in that the steps are as follows: 1)第一级流水线：实现在当前上下文CX下，待压缩数据D的概率估计值的查询和更新，其输入为上下文CX、待压缩数据D和重整化信号Renorm；上下文CX查询CX状态表得到概率估计表索引Index和大概率符号mps，它们分别用来读取概率估计表和判断下一阶段进行大概率编码或者小概率编码；重整化信号Renorm则用来标识是否对上下文状态表进行更新；对于连续输入相同上下文CX的情况，需对CX用一个寄存器延时一周期，如果第一个CX引发重整化，产生信号Renorm，那么索引直接通过多路选择器把更新的下一状态送到概率估计表，不再去读CX状态表；CX状态表则依旧进行更新；1) The first-level pipeline: realize the query and update of the probability estimate value of the data to be compressed D under the current context CX, and its input is the context CX, the data to be compressed D and the renormalization signal Renorm; the context CX queries the CX state table Obtain the probability estimation table index Index and the high probability symbol mps, which are used to read the probability estimation table and judge the high probability coding or small probability coding in the next stage; the renormalization signal Renorm is used to identify whether to perform Update; for the case of continuous input of the same context CX, it is necessary to use a register to delay CX for one cycle. If the first CX triggers renormalization and generates a signal Renorm, then the index directly passes through the multiplexer to update the next state Send to the probability estimation table, no longer read the CX status table; the CX status table is still updated; 2)第二级流水线：实现间隔寄存器A的更新，其输入为概率估计值Qe、前导零数LZ和判断待压缩数据D是否为小概率符号所得的小概率符号选择信号mps_sel；如果是小概率符号，则A＝Qe；否则A＝A-Qe；在编码过程中，如果间隔寄存器A小于0x8000，则需要进行重整化操作，同时输出重整化信号Renorm，以更新上下文状态表，保证概率间隔大于或者等于0x8000；2) The second-stage pipeline: realize the update of the interval register A, whose input is the probability estimation value Qe, the leading zero LZ and the small probability symbol selection signal mps_sel for judging whether the data D to be compressed is a small probability symbol; if it is a small probability symbol, then A=Qe; otherwise A=A-Qe; in the encoding process, if the interval register A is less than 0x8000, a renormalization operation is required, and the renormalization signal Renorm is output at the same time to update the context state table to ensure the probability The interval is greater than or equal to 0x8000; 3)第三级流水线：实现编码寄存器C的更新，其输入为概率估计值Qe和判断待压缩数据D是否为小概率符号所得的小概率符号选择信号mps_sel；它需要与间隔寄存器A进行同步的重整化操作，如果是小概率符号，则C保持不变；否则C＝C+Qe；本级流水线对外输出数据C_result值；3) The third-stage pipeline: realize the update of the encoding register C, whose input is the probability estimation value Qe and the small-probability symbol selection signal mps_sel for judging whether the data to be compressed D is a small-probability symbol; it needs to be synchronized with the interval register A For the renormalization operation, if it is a small probability symbol, then C remains unchanged; otherwise, C=C+Qe; the current-level pipeline outputs the data C_result value; 4)第四级流水线：实现字节提取和输出，当C寄存器移位值大于等于27时，需要输出两个字节OutH、OutL，如果OutH或者OutL字节等于0xFF时，需要在该字节后插入字符‘0’到剩余字符中；当C寄存器移位值小于27大于等于19时，需要输出一个字节OutL，如果OutL字节等于0xFF时，需要在该字节后插入字符‘0’到剩余字符中；当C寄存器移位值小于19时无字节输出。4) The fourth-level pipeline: to achieve byte extraction and output. When the shift value of the C register is greater than or equal to 27, two bytes OutH and OutL need to be output. If the OutH or OutL byte is equal to 0xFF, it needs to be in the byte Then insert the character '0' into the remaining characters; when the C register shift value is less than 27 and greater than or equal to 19, you need to output a byte OutL, if the OutL byte is equal to 0xFF, you need to insert the character '0' after this byte to the remaining characters; no bytes are output when the C register shift value is less than 19. 2、一种如权利要求1所述的JPEG2000流水线算术编码方法所使用的电路，包括上下文状态表查询更新模块、概率估计查询模块、A寄存器更新模块、C寄存器更新模块和字节输出模块，其中以上下文状态表查询更新模块与概率估计查询模块为主组成第一级流水线电路；以A寄存器更新模块、C寄存器更新模块和字节输出模块为主依次分别构成第二、三、四级流水线电路，其特征在于四级流水线电路依次相连接，即上下文状态表查询更新模块与概率估计查询模块连接，概率估计查询模块与A寄存器更新模块连接，A寄存器更新模块和C寄存器更新模块连接，C寄存器更新模块连接字节输出模块，且A寄存器更新模块与上下文更新模块连接。2. A circuit used by the JPEG2000 pipeline arithmetic coding method as claimed in claim 1, comprising a context state table query update module, a probability estimation query module, an A register update module, a C register update module and a byte output module, wherein The first-stage pipeline circuit is mainly composed of the context state table query update module and the probability estimation query module; the second, third, and fourth-stage pipeline circuits are respectively composed of the A register update module, the C register update module and the byte output module. , which is characterized in that the four-stage pipeline circuit is connected in turn, that is, the context state table query update module is connected with the probability estimation query module, the probability estimation query module is connected with the A register update module, the A register update module is connected with the C register update module, and the C register The update module is connected to the byte output module, and the A register update module is connected to the context update module. 3、如权利要求2所述的电路，其特征在于所述的第一级流水线电路还包括数据选择器M1和M2、数据比较器、寄存器、异或运算器和与运算器，其中上下文状态表查询更新模块包括上下文状态表；概率估计查询模块包括概率估计表；本级流水线输入为上下文CX、待压缩数据D和重整化信号Renorm；上下文状态表输入数据为上下文CX、重整化信号Renorm、寄存器输出端和数据选择器M2输出端，输出分别连接异或运算器和数据选择器M1输入端；待压缩数据D与上下文状态表查询更新模块的输出大概率符号Mps连接到异或运算器作为输入，输出端作为本级流水线输出mps_sel；数据选择器M1输入端接上下文状态表输出的概率估计表索引Index、与运算器输出端和数据选择器M2的输出端；概率估计表输入端接数据选择器M1的输出端，输出端接数据选择器M2的输入和作为本级流水线的输出Qe，LZ；数据比较器输入接上下文CX和寄存器输出端，输出端接与运算器；与运算器输入端接数据比较器输出和重整化信号Renorm，输出端接数据选择器M1。3. The circuit according to claim 2, characterized in that said first-stage pipeline circuit also includes data selectors M1 and M2, data comparators, registers, XOR operators and AND operators, wherein the context state table The query update module includes the context state table; the probability estimation query module includes the probability estimation table; the input of the pipeline at this stage is the context CX, the data to be compressed D and the renormalization signal Renorm; the input data of the context state table is the context CX and the renormalization signal Renorm , the output end of the register and the output end of the data selector M2, and the outputs are respectively connected to the XOR operator and the input end of the data selector M1; the output high probability symbol Mps of the data D to be compressed and the query update module of the context state table is connected to the XOR operator As an input, the output terminal is used as the pipeline output mps_sel of the current stage; the input terminal of the data selector M1 is connected to the index Index of the probability estimation table output by the context state table, the output terminal of the AND operator and the output terminal of the data selector M2; the input terminal of the probability estimation table is connected The output terminal of the data selector M1, the output terminal is connected to the input of the data selector M2 and the output Qe, LZ as the pipeline of this stage; the input of the data comparator is connected to the context CX and the output terminal of the register, and the output terminal is connected to the AND operator; the AND operator The input terminal is connected to the output of the data comparator and the renormalization signal Renorm, and the output terminal is connected to the data selector M1. 4、如权利要求2所述的电路，其特征在于所述的第二级流水线电路包括异或运算器、减法器模块S1和S2、倍乘模块、前导零检测模块、反相器、数据选择器和桶形移位寄存器；本级流水线输入为水线输出概率值Qe、前导零数LZ和判断带压缩数据D是否为小概率符号所得的小概率符号选择信号mps_sel；异或运算器输入端接小概率符号选择信号mps_sel和减法器模块S1的输出端，异或运算器输出端接数据选择器的输入端和作为本级流水线的输出区间选择信号flag_sel；减法器模块S1输入端为倍乘模块(其输入端为概率值Qe)输出端和A寄存器输出端，减法器模块S1输出端为异或运算器输入端；减法器模块S2输入端为A寄存器输出端和概率值Qe，输出端连接数据选择器；数据选择器输入端为概率值Qe、减法器模块S2输出端和异或运算器输出端，数据选择器输出端连接前导零检测模块、反相器和桶形移位寄存器；前导零检测模块输入端为数据选择器输出端最高两位、前导零数LZ、小概率符号选择信号mps_sel，输出端接桶形移位寄存器输入端和本级流水线的输出移位数值Nshift；反相器输入端为数据选择器输出端最高位，输出端为重整化信号Renorm；桶形移位寄存器输入端为数据选择器输出端、前导零检测模块输出端，桶形移位寄存器输出端接寄存器A输入端。4. The circuit according to claim 2, characterized in that said second-stage pipeline circuit includes an XOR operator, subtractor modules S1 and S2, a multiplication module, a leading zero detection module, an inverter, and a data selection device and barrel shift register; the pipeline input of this stage is the pipeline output probability value Qe, the leading zero LZ and the small probability symbol selection signal mps_sel obtained by judging whether the compressed data D is a small probability symbol; the input terminal of the XOR operator Connect the small probability symbol selection signal mps_sel and the output terminal of the subtracter module S1, the output terminal of the XOR operator is connected to the input terminal of the data selector and the output interval selection signal flag_sel as the output interval of the pipeline at this stage; the input terminal of the subtracter module S1 is multiplication Module (its input end is the probability value Qe) output end and the A register output end, the subtractor module S1 output end is the XOR operator input end; The subtracter module S2 input end is the A register output end and the probability value Qe, the output end Connect the data selector; the input of the data selector is the probability value Qe, the output of the subtractor module S2 and the output of the XOR operator, and the output of the data selector is connected to the leading zero detection module, the inverter and the barrel shift register; The input terminal of the leading zero detection module is the highest two digits of the output terminal of the data selector, the leading zero number LZ, and the small probability symbol selection signal mps_sel, and the output terminal is connected to the input terminal of the barrel shift register and the output shift value Nshift of the pipeline at this stage; The input terminal of the phaser is the highest bit of the output terminal of the data selector, and the output terminal is the renormalization signal Renorm; the input terminal of the barrel shift register is the output terminal of the data selector, the output terminal of the leading zero detection module, and the output terminal of the barrel shift register Connect to register A input. 5、如权利要求4所述的第二级流水线电路，其特征在于所述前导零检测模块是由数据选择器和解码器组成，解码器输入端接数据选择器输出端最高两位，解码器输出端接数据选择器输入端；数据选择器输入接前导零数LZ、判断信号mps_sel和解码器输出端，数据选择器输出端即本模块输出端。5. The second-stage pipeline circuit as claimed in claim 4, characterized in that said leading zero detection module is composed of a data selector and a decoder, the input terminal of the decoder is connected to the highest two digits of the output terminal of the data selector, and the decoder The output terminal is connected to the input terminal of the data selector; the input terminal of the data selector is connected to the leading zero LZ, the judgment signal mps_sel and the output terminal of the decoder, and the output terminal of the data selector is the output terminal of this module. 6、如权利要求2所述的电路，其特征在于所述的第三级流水线电路结构与权利要求4所述的第二级流水线电路结构相同。6. The circuit according to claim 2, characterized in that the structure of the third-stage pipeline circuit is the same as that of the second-stage pipeline circuit according to claim 4. 7、如权利要求2所述的电路，其特征在于所述的第四级流水线还包括加法器模块A1和A2、掩码模块、计数器、桶形移位寄存器模块、减法器模块和字节提取模块；掩码模块输入端为C_result和移位数值Nshift，输出端接桶形移位寄存器输入端；加法器模块A1输入端为移位数值Nshift，输出端接减法器模块输入端；加法器模块A2输入端接寄存器模块输出端和桶形移位寄存器输出端，加法器模块A2输出端接字节输出模块；桶形移位寄存器输入端接掩码模块输出端和计数器输出端；减法器模块输入端接加法器A1和字节提取模块输出端，减法器模块输出端接计数器输入端；计数器输入端接减法器输出端，计数器输出端接加法器模块A1输入端和桶形移位寄存器模块输入端；字节提取模块输入端接加法器模块A1输出端和加法器模块A2输出端，字节提取模块输出端接减法器模块输入端、寄存器输入端以及本级流水线输出OutL、OutH。7. The circuit according to claim 2, characterized in that said fourth stage pipeline also includes adder modules A1 and A2, mask module, counter, barrel shift register module, subtractor module and byte extraction Module; the input end of the mask module is C_result and the shift value Nshift, and the output end is connected to the input end of the barrel shift register; the input end of the adder module A1 is the shift value Nshift, and the output end is connected to the input end of the subtractor module; the adder module The input terminal of A2 is connected to the output terminal of the register module and the output terminal of the barrel shift register, the output terminal of the adder module A2 is connected to the byte output module; the input terminal of the barrel shift register is connected to the output terminal of the mask module and the output terminal of the counter; the subtractor module The input terminal is connected to the adder A1 and the output terminal of the byte extraction module, the output terminal of the subtractor module is connected to the input terminal of the counter; the input terminal of the counter is connected to the output terminal of the subtractor, and the output terminal of the counter is connected to the input terminal of the adder module A1 and the barrel shift register module Input terminal; the input terminal of the byte extraction module is connected to the output terminal of the adder module A1 and the output terminal of the adder module A2, and the output terminal of the byte extraction module is connected to the input terminal of the subtractor module, the input terminal of the register and the outputs OutL and OutH of the pipeline of this stage. 8、如权利要求2所述的电路，其特征在于所述字节输出模块由数据比较器C1和C2、字节输出控制模块组成。数据比较器C1输入端接加法器模块A1输出端和数字27，输出端接字节输出控制模块输入端；数据比较器C2输入端接加法器模块A1输出端和数字19，输出端接字节输出控制模块输入端。8. The circuit according to claim 2, characterized in that the byte output module is composed of data comparators C1 and C2, and a byte output control module. The input terminal of the data comparator C1 is connected to the output terminal of the adder module A1 and the number 27, and the output terminal is connected to the input terminal of the byte output control module; the input terminal of the data comparator C2 is connected to the output terminal of the adder module A1 and the number 19, and the output terminal is connected to the byte Output control module input.
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Cited By (7)

* Cited by examiner, † Cited by third party
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CN101848387A (en) * 2010-03-19 2010-09-29 西安电子科技大学 Method for determining arithmetic encoding probability interval value based on JPEG (Joint Photographic Experts Group) 2000 standard
CN101771879B (en) * 2010-01-28 2011-08-17 清华大学 Parallel normalized coding realization circuit based on CABAC and coding method
CN102176750A (en) * 2011-03-10 2011-09-07 西安电子科技大学 High-performance adaptive binary arithmetic encoder
CN101848311B (en) * 2010-02-21 2011-09-28 哈尔滨工业大学 JPEG2000 EBCOT encoder based on Avalon bus
CN102348111A (en) * 2010-07-30 2012-02-08 国家卫星气象中心 Data compression structure identification code used for stationary weather satellite data broadcasting
US9450606B1 (en) 2015-10-01 2016-09-20 Seagate Technology Llc Data matching for hardware data compression
CN107093162A (en) * 2017-04-28 2017-08-25 天津大学 A kind of MQ encoders applied to JPEG2000

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101771879B (en) * 2010-01-28 2011-08-17 清华大学 Parallel normalized coding realization circuit based on CABAC and coding method
CN101848311B (en) * 2010-02-21 2011-09-28 哈尔滨工业大学 JPEG2000 EBCOT encoder based on Avalon bus
CN101848387A (en) * 2010-03-19 2010-09-29 西安电子科技大学 Method for determining arithmetic encoding probability interval value based on JPEG (Joint Photographic Experts Group) 2000 standard
CN102348111A (en) * 2010-07-30 2012-02-08 国家卫星气象中心 Data compression structure identification code used for stationary weather satellite data broadcasting
CN102176750A (en) * 2011-03-10 2011-09-07 西安电子科技大学 High-performance adaptive binary arithmetic encoder
US9450606B1 (en) 2015-10-01 2016-09-20 Seagate Technology Llc Data matching for hardware data compression
CN107093162A (en) * 2017-04-28 2017-08-25 天津大学 A kind of MQ encoders applied to JPEG2000

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