CN100555879C - A kind of encoder apparatus of LDPC sign indicating number and coding method - Google Patents

A kind of encoder apparatus of LDPC sign indicating number and coding method Download PDF

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CN100555879C
CN100555879C CNB2007101197958A CN200710119795A CN100555879C CN 100555879 C CN100555879 C CN 100555879C CN B2007101197958 A CNB2007101197958 A CN B2007101197958A CN 200710119795 A CN200710119795 A CN 200710119795A CN 100555879 C CN100555879 C CN 100555879C
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generator matrix
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CN101114834A (en
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张晓林
赵岭
张展
张超
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Beihang University
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Abstract

The invention discloses a kind of encoder apparatus and coding method of LDPC sign indicating number, it is by cutting apart the generator matrix of various code checks, generator matrix after will cutting apart then effectively is stored in the memory, when coding, information bit to be encoded is by the memory buffer of plurality of small blocks, and by bit output, the generator matrix good with prior storage carries out multiplying, then the operation result between each bit is sued for peace, after the multiplying of all information bits and all generator matrix pieces is finished, check digit is just obtained, and parallel output to output unit and finish computing.Use encoder apparatus provided by the invention and coding method, can encode, be specially adapted to the design of the LDPC code coder in the Digital TV broadcasting standard for terrestrial single LDPC sign indicating number of planting code check and various code rate.

Description

A kind of encoder apparatus of LDPC sign indicating number and coding method
Technical field
The invention belongs to the communications field, relate to a kind of designing technique of encoder, particularly a kind of encoder apparatus of LDPC sign indicating number and coding method.
Background technology
The LDPC sign indicating number, full name Low Density Parity Check Code, i.e. low density parity check code.In present existing chnnel coding, the LDPC sign indicating number has demonstrated the anti-error performance near shannon limit (Shannon ' s limit) in some cases, compare with the Turbo code that is long code equally, the error code flat bed of LDPC sign indicating number (error floor) appears at very low error rate zone, and the wrong code word probability that can't detect be one extremely low very near 0 value; Most elements of the parity check matrix H of LDPC sign indicating number are " 0 ", and this i.e. the name origin of " low-density ", and such characteristic can be deciphered it by the interpretation method that simply is easy to realize, has high practical value.Owing to above some reason, make LDPC become research and the focus of using in recent years, for example: the digital TV ground transmission standard of second generation satellite digital TV video broadcast standards (DVB-S2) and China is all used the chnnel coding of LDPC sign indicating number as core.Yet, at home and abroad, most literature research be the interpretation method and the structure of LDPC sign indicating number, research coding structure document less.
On the other hand, satisfy requirements of different users, in some communication system, also adopt the chnnel coding of various code rate in order to adapt to different environment, for example, the digital TV ground transmission standard of China has just adopted the LDPC code word of 0.4,0.6,0.8 3 kinds of code checks as chnnel coding.And document " error correction/encoding method that is used for ground digital television broadcast " application number 200510086226.5 discloses the error correction/encoding method in the digital TV ground transmission standard.
But above-mentioned document only is the data stream format that discloses error correction coding, and not proposing one can be for the complete structure and the method that realize, and based on this, this paper has provided a kind of encoder and coding method of LDPC sign indicating number.
Summary of the invention
The object of the present invention is to provide a kind of encoder apparatus and coding method of LDPC sign indicating number, the generator matrix information of the LDPC sign indicating number of the various code checks that needs are encoded is stored in the memory of circuit in advance, when coding, the address information of reading by selection memory, just can be with the generator matrix information output of required code check, and with the input information bit carry out matrix multiplication operation, thereby finish coding.The present invention can encode to the LDPC sign indicating number of 0.4,0.6 and 0.8 3 kind of code check in the Digital Television ground transmission standard.Select corresponding code check and import the information to be encoded of LDPC sign indicating number, with regard to the exportable LDPC code stream that meets the digital TV ground transmission standard-required.
A kind of LDPC code encoding device provided by the invention comprises: encoder is mainly gathered by input-buffer unit ISU, generator matrix memory cell GMSU set, matrix multiplication operation unit MMU, output buffers unit OSU and the logic control element LCU composition that above each several part is controlled.Input-buffer unit ISU is used for the information bit of the input under the various code checks is carried out buffer memory; Generator matrix memory cell GMSU is used to store the information of the generator matrix of various rate codewords correspondences; Matrix multiplication operation unit MMU is used to finish the information bit of input and the multiplying of generator matrix; Output buffers unit OSU is used for check digit and information bit behind the coding are stored; Logic control element LCU is used for writing and read the address, the switching of the built-in storage unit that reads address and control output buffers unit OSU of control generator matrix memory cell GMSU according to user-selected Rate Control input-buffer unit ISU.
During coding, according to user-selected code check, under the control of logic control element LCU, information bit to be encoded is deposited among the input-buffer unit ISU, through the register cache information position among the input-buffer unit ISU, this information bit outputs to from input-buffer unit ISU among matrix multiplication operation unit MMU set and the output buffers unit OSU.According to user-selected code check, under the control of logic control element LCU, generator matrix memory cell GMSU set generates generator polynomial, and the generator polynomial of the needed correspondence of will encoding outputs in the matrix multiplication operation unit MMU set from generator matrix memory cell GMSU set.Matrix multiplication operation unit MMU is to carrying out matrix multiplication operation from the information bit of input-buffer unit ISU output and the matrix information of exporting from generator matrix memory cell GMSU, the result of the computing needed check digit of encoding exactly, these check digit are by the parallel output buffers unit OSU that outputs to.In output buffers unit OSU, the information bit from input-buffer unit ISU output is put in order with the check digit of exporting from matrix multiplication operation unit MMU, constitute a complete code word output.
Described generator matrix memory cell GMSU set comprises 12 identical generator matrix memory cell altogether, wherein k GMSU unit is used to store all generator polynomials of individual and (24+k) the individual row piece of k of generator matrix of 0.4 code check, (12+k), store k and all generator polynomials of (12+k) individual row piece of the generator matrix of 0.6 code check, store all generator polynomials of k row piece of the generator matrix of 0.8 code check, wherein 1≤k≤11.Especially, the 12 GMSU unit is used to store all generator polynomials of the 12nd and the 24th row piece of the generator matrix of 0.4 code check, stores all generator polynomials of the 12nd row piece of the generator matrix of 0.6 code check;
Described matrix multiplication operation unit MMU set comprises 12 identical matrix multiplication operation unit altogether, and is corresponding with the number of generator matrix memory cell.
Described input-buffer unit ISU comprises: the buffer memory unit set comprises that three identical sizes are that 2048 bits, bit wide are 1 memory, so the size of buffer memory unit set is 6144 bits.The information bit of input is connected to the input of three memories in the buffer memory unit set simultaneously; Also comprise a data selector unit, it is input as the data output end of three memories in the buffer, and the data selector unit is exported the data of memory successively according to the order of information bit, constitutes continuous message bit stream.
Described generator matrix memory cell GMSU comprises: first memory block, second memory block, the 3rd memory block, the 4th memory block, the 5th memory block, the 6th memory block.First to the 3rd memory block is used to store the generator matrix information of 0.4 code check, and the 4th and the 5th memory block is used to store the generator matrix information of 0.6 code check, and the 6th memory block is used to store the generator matrix information of 0.8 code check.In when coding, select the difference of code check and coding process according to the user, under the control of LCU, will the encode generator matrix information of needed correspondence of GMSU is exported.
Described matrix multiplication operation unit MMU comprises: shift register cell, and length is 127 bits, is used for depositing from GMSU reading generator matrix information; First arithmetic element set, comprise altogether identical 127 with door, the generator matrix information after the displacement that the information bit that is used to finish input and shift register cell are exported is carried out multiplying; Register cell, length is 127 bits, is used to deposit the output result of second arithmetic element set; Second arithmetic element set comprises 127 identical XOR gate altogether, is used to finish the summation operation of the output of the output of first arithmetic element and register cell.
Described shift register cell is with the generator polynomial g of corresponding GMSU output I, jDeposit in wherein, respectively with the door carry out binary multiplication what first arithmetic element was gathered, i.e. phase and computing from the information bit of input-buffer unit ISU output and each bit of shift register cell simultaneously; An input that respectively is connected respectively to each XOR gate of second arithmetic element set of first arithmetic element set with the output of door, finish with register cell in the binary addition of each data, be XOR, the result of XOR is deposited in the register cell.
Described output buffers unit OSU comprises: the register cell set, and its output to the register cell of MMU unit is deposited, and length is 127 bits; The data selector unit, it is input as the output of the data selector unit of the output of register cell and aforesaid ISU; First memory, size are 8192 bits, and bit wide is 1, are used to store the output of data selector unit; Second memory, size are 8192 bits, and bit wide is 1, are used to store the output of data selector unit; Described first memory is identical with second memory, and first memory and second memory formation ping-pong operation mode.
A kind of encoder encodes method of LDPC sign indicating number has following steps:
Step 1: input information position buffer memory
According to user-selected code check, (for 0.4 code check, N is 3048 from the 1st clock cycle to N clock cycle; For 0.6 code check, N is 4572; For 0.8 code check, N is 6096), information bit to be encoded is imported among the input-buffer unit ISU by bit.From the 2nd clock cycle to N+1 clock cycle, the information bit of the 1st clock cycle to N clock cycle is by order output by turn from ISU.
Step 2: matrix generator polynomial output
With step 1 side by side, from the 2nd clock cycle to N+1 clock cycle, according to user-selected code check, the output from generator matrix memory cell GMSU set successively of the generator polynomial of generator matrix.
Step 3: matrix multiplication operation
With step 1 side by side, from the 2nd clock cycle to N+1 clock cycle, MMU set in matrix multiplication operation unit is carried out matrix multiplication operation with the information bit of input-buffer unit ISU output and the generator matrix of generator matrix memory cell GMSU set output, obtains needed check digit.
Step 4: output information buffer memory
With step 1 side by side, the 2nd to N+1 clock cycle, the information bit of input-buffer unit ISU output outputs to the MMU unit on the one hand and participates in computing, information bit is input among the output buffers unit OSU on the other hand.
Concrete, the 2nd to N+1 clock cycle, the memory that the data selector unit among the OSU is selected the information bit of input to be exported to the back level is stored.
N+1 clock cycle, all MMU have finished third step, obtain check digit vector p 1To p 12, and output to the register cell set of OSU, and at this moment, the register pair p in the register cell set 1To p 12Deposit.In 127 clock cycle subsequently, promptly N+2 clock be to N+128 clock, p 1By first register serial output, the data output with first register of register cell set is selected in the data selector unit, in 127 clock cycle then, and p 2By second register serial output, the data output with second register of register cell set is selected in the data selector unit, and the rest may be inferred, to (N+1+127 * 12) the individual clock cycle, and p 1To p 12All exported and be deposited in first memory or the second memory by serial.
If user-selected code check is 0.8, pass through above 4 steps so, whole cataloged procedure finishes.
If user-selected code check is 0.6, to finish whole cataloged procedure so, need again execution in step 1 to step 4, with preceding once different be: in step 1, owing to do not have the information bit input, so do not need information bit is carried out buffer memory, only need canned data position order output successively before; In step 2, the generator matrix unit need be exported the data in the 5th memory block in the GMSU unit in proper order.So far, 0.6 code check cataloged procedure finishes.
If user-selected code check is 0.4, to finish whole cataloged procedure so, need again execution in step 1 to arrive twice of step 4, different is, in second time implementation: similar with 0.6 code check, in step 1, only need will before the order output successively of canned data position; In step 2, the generator matrix unit need be exported the data in second memory block in the GMSU unit in proper order.In implementation for the third time, in step 1, only need will before the order output successively of canned data position; In step 2, the generator matrix unit need be exported the data in the 3rd memory block in the GMSU unit in proper order.So far, 0.4 code check cataloged procedure finishes.
When needs are encoded next time, repeat above process, the memory that different is in the OSU that step 4 is used is the preceding memory that once not have use in described first memory and the second memory, formation ping-pong operation mode.
In sum, use encoder apparatus provided by the invention and coding method, can encode the LDPC sign indicating number of various code rate.
The invention has the advantages that:
(1) announced a concrete enforceable LDPC coder structure;
(2) the generator matrix information of different code check correspondences is deposited in generator matrix memory cell GMSU set among the present invention, select different addresses by logic control element, the present invention can encode to the LDPC sign indicating number of different code checks.
Description of drawings
Fig. 1 is the used generator matrix schematic diagram of LDPC coding involved in the present invention;
Example of multi code Rate of Chinese character LDPC encoder that Fig. 2 designs for the present invention;
Fig. 3 is the example of input-buffer unit ISU among the present invention;
Fig. 4 is the example of generator matrix memory cell GMSU among the present invention;
Fig. 5 is the example of matrix multiplication operation unit MMU among the present invention;
Fig. 6 is the example of output buffers unit OSU among the present invention;
Fig. 7 is the flow chart of ldpc decoder fgs encoder method of the present invention.
Among the figure: 1. input-buffer unit 101. set of memory cells
101a.ramA 101b.ramB 101c.ramC 102. data selector unit
2. matrix memory cell GMSU gathers 201. first GMSU
202. the 12 GMSU of the 11 GMSU 212. of second GMSU 211.
201a. the first memory block 201b., the second memory block 201c. the 3rd memory block
201d. the 4th memory block 201e. the 5th memory block 201f. the 6th memory block
3. matrix multiplication unit MMU gathers 301. first MMU
302. the 12 MMU of the 11 MMU 312. of second MMU 311.
301a. shift register cell 301b. first arithmetic element set 301c. second arithmetic element set
301d. register cell 4. output buffers unit OSU 401. register cells set
402. data selector unit 403. first memories, 404. second memories
4001. first register, 4002. second registers, 5. logic control element LCU
Embodiment
The present invention is described in further detail below in conjunction with drawings and Examples.
The present invention can encode to the LDPC sign indicating number of 0.4,0.6 and 0.8 3 kind of code check in the Digital Television ground transmission standard.The information to be encoded of input LDPC sign indicating number and corresponding code check are with regard to the LDPC code stream of exportable standard.Solved the problem that the hardware resource of encoding under the multi code Rate of Chinese character consumes too much or code rate reduces.
The generator matrix of the LDPC sign indicating number that is used for present embodiment is at first described.Generator matrix abbreviates the G matrix as, in the digital TV ground transmission standard form of the generator matrix of the LDPC sign indicating number of three kinds of used code checks as shown in Figure 1, wherein, I is the unit matrix of a b * b, O is the null matrix of a b * b, B I, j(1≤i≤k, 1≤j≤c) is the cyclic determinant of a b * b.We are with B I, jFirst the row vectorial g I, jThe called after generator polynomial, obviously, g I, jLength be b, so, B I, jSecond row can by first the row cyclic shift obtain, and the like, B I, jEach provisional capital can obtain by the lastrow cyclic shift.So, B I, jCan be by g I, jDetermine.In the digital TV ground transmission standard, the parameter of the generator matrix of 0.4,0.6,0.8 3 kinds of code checks is as follows:
Table 1LDPC code word generator matrix parameter
Figure C20071011979500111
The principle of coding is then described.According to Fig. 1 as can be known, the G correspondence be the form of systematic code, the code word behind the coding is made of information bit and check digit two parts, information bit is extraneous input, can directly obtain, so, only need try to achieve check digit and get final product.The knowledge relevant according to chnnel coding, the check digit of the required generation of encoding can be by the information bit of input and the B among the G I, jMultiply each other and obtain.That is:
Figure C20071011979500112
Wherein, B 1First B for G I, jThe row piece, B 2Second B for G I, jThe row piece, and the like, B cC B for G I, jThe row piece.If p also is divided into the vector that several length are b, promptly establish: p=[p 1, p 2..., p c], so,, have for 1≤j≤c:
p j＝mB j
So check digit can be by the B of information bit and generator matrix I, jPiece multiplies each other and obtains.
Describe a kind of LDPC code encoding device of the present invention below in detail:
As shown in Figure 2, encoder comprises following part in the present embodiment: input-buffer unit ISU1; Generator matrix memory cell GMSU set 2 comprises 12 generator matrix memory cell GMSU altogether, is respectively GMSU201 to GMSU212; Matrix multiplication operation unit MMU set 3 comprises 12 matrix multiplication operation unit MMU altogether, is respectively MMU301 to MMU311, MMU312; Output buffers unit OSU4; And the logic control element LCU5 that above each several part is controlled.
During coding, according to user-selected code check, under the control of logic control element LCU5, information bit to be encoded is deposited among the input-buffer unit ISU1, through the register cache information position among the input-buffer unit ISU1, this information bit outputs to from input-buffer unit ISU1 among matrix multiplication operation unit MMU set 2 and the output buffers unit OSU4.According to user-selected code check, under the control of logic control element LCU5, matrix memory cell GMSU set 2 generates generator polynomial, and the generator polynomial of the needed correspondence of will encoding outputs in the matrix multiplication operation unit MMU set 3 from matrix memory cell GMSU set 2.Matrix multiplication operation unit MMU301 to MMU311, MMU312 are to carrying out matrix multiplication operation from the information bit of input-buffer unit ISU1 output and the matrix information of exporting from matrix memory cell GMSU201 to GMSU212, the result of the computing needed check digit of encoding exactly, these check digit are by the parallel output buffers unit OSU4 that outputs to.In output buffers unit OSU4, the information bit from input-buffer unit ISU1 output is put in order with the check digit of exporting from matrix multiplication operation unit MMU301 to MMU311, MMU312, constitute a complete code word output.
As shown in Figure 3, be the cellular construction of the used input-buffer unit ISU1 of present embodiment.ISU1 comprises, set of memory cells 101, and it is 2048 bits by three identical sizes, bit wide is that 1 memory ramA101a, ramB101b and ramC101c forms, so the size of described set of memory cells 101 is 6144 bits; ISU1 also comprises data selector unit 102, and it has 3 input items.
Above-mentioned set of memory cells is according to the difference of user-selected code check, information bit to input is stored, for 0.4 code check, the length of the needed information bit of encoding each time is 3048 bits, so the information bit of input takies preceding 3048 bits of this 6144 bit storage space; For 0.6 code check, the length of the needed information bit of encoding each time is 4512 bits, so the information bit of input takies preceding 4512 bits of this 6144 bit storage space; For 0.8 code check, the length of the needed information bit of encoding each time is 6096 bits, so the information bit of input takies preceding 6096 bits of this 6144 bit storage space.The information bit of input is connected to the input of three memory cells in the set of memory cells 101 simultaneously;
The data output end that is input as three memories in the set of memory cells 101 of above-mentioned data selector unit 102, data selector unit 102 is exported the data of ramA101a, ramB101b and ramC101c successively according to the order of information bit, constitutes continuous message bit stream and exports to follow-up unit.
The generator matrix memory cell that encoder of the present invention is described below is GMSU.
As shown in Figure 4, the cellular construction figure of the generator matrix memory cell GMSU2 that present embodiment is used, GMSU201 all adopts this structure to GMSU 212, is the structure of GMSU201 unit shown in the figure.
Above-mentioned GMSU201 unit comprises: the first memory block 201a, the second memory block 201b, the 3rd memory block 201c, the 4th memory block 201d, the 5th memory block 201e, the 6th memory block 201f.The generator matrix information that the first memory block 201a, the second memory block 201b and the 3rd memory block 201c are used to store 0.4 code check; The generator matrix information that the 4th memory block 201d and the 5th memory block 201e are used to store 0.6 code check, the 6th memory block 201f is used to store the generator matrix information of 0.8 code check.The bit wide of GMSU is 127 bits.
Concrete, for the GMSU201 unit, the first memory block 201a stores the 1st B of the generator matrix of 0.4 code check I, jRow piece B 1All generator polynomial g I, 1(1≤i≤24), the second memory block 201b stores the 13rd B of the generator matrix of 0.4 code check I, jRow piece B 13All generator polynomial g I, 13(1≤i≤24), the 3rd memory block 201c stores the 25th B of the generator matrix of 0.4 code check I, jRow piece B 25All generator polynomial g I, 25(1≤i≤24); The 4th memory block 201d stores the 1st B of the generator matrix of 0.6 code check I, jRow piece B 1All generator polynomial g I, 1(1≤i≤36), the 5th memory block 201e stores the 13rd B of the generator matrix of 0.6 code check I, jRow piece B 13All generator polynomial g I, 13(1≤i≤36); The 6th memory block 201f stores the 1st B of the generator matrix of 0.8 code check I, jRow piece B 1All generator polynomial g I, 1(1≤i≤48).
In like manner, for the GMSU202 unit, the 2nd B of the generator matrix of first storage area stores, 0.4 code check of GMSU202 unit I, jRow piece B 2All generator polynomial g I, 2(1≤i≤24), the 14th B of the generator matrix of second storage area stores, 0.4 code check I, jRow piece B 14All generator polynomial g I, 14(1≤i≤24), the 26th B of the generator matrix of the 3rd storage area stores 0.4 code check I, jRow piece B 26All generator polynomial g I, 26(1≤i≤24); The 2nd B of the generator matrix of the 4th storage area stores 0.6 code check I, jRow piece B 2All generator polynomial g I, 2(1≤i≤36), the 14th B of the generator matrix of the 5th storage area stores 0.6 code check I, jRow piece B 14All generator polynomial g I, 14(1≤i≤36); The 2nd B of the generator matrix of the 6th storage area stores 0.8 code check I, jRow piece B 2All generator polynomial g I, 2(1≤i≤48).
The rest may be inferred, for the GMSU211 unit, and the 11st B of the generator matrix of first storage area stores, 0.4 code check of GMSU211 unit I, jRow piece B 11All generator polynomial g I, 11(1≤i≤24), the 23rd B of the generator matrix of second storage area stores, 0.4 code check I, jRow piece B 23All generator polynomial g I, 23(1≤i≤24), the 35th B of the generator matrix of the 3rd storage area stores 0.4 code check I, jRow piece B 35All generator polynomial g I, 35(1≤i≤24); The 11st B of the generator matrix of the 4th storage area stores 0.6 code check I, jRow piece B 11All generator polynomial g I, 11(1≤i≤36), the 23rd B of the generator matrix of the 5th storage area stores 0.6 code check I, jRow piece B 23All generator polynomial g I, 23(1≤i≤36); The 11st B of the generator matrix of the 6th storage area stores 0.8 code check I, jRow piece B 11All generator polynomial g I, 11(1≤i≤48).
Especially, for the GMSU212 unit, the 12nd B of the generator matrix of first storage area stores, 0.4 code check of GMSU212 unit I, jRow piece B 12All generator polynomial g I, 12(1≤i≤24), the 24th B of the generator matrix of second storage area stores, 0.4 code check I, jRow piece B 24All generator polynomial g I, 24(1≤i≤24), the 3rd memory block keeps; The 12nd B of the generator matrix of the 4th storage area stores 0.6 code check I, jRow piece B 12All generator polynomial g I, 12(1≤i≤36), the 5th memory block keeps; The 6th memory block keeps.
According to the process of user-selected code check and coding, the logic control element 5 of encoder can provide the address of reading of generator matrix memory cell 2, and generator polynomial is wherein read, and is used for coding.
As shown in Figure 5, be the cellular construction of the used matrix multiplication unit MMU3 of present embodiment, MMU all adopts this structure to MMU 312 in Unit 301.
Concrete, for the MMU301 unit, comprising: shift register cell 301a, length is 127 bits, is used for depositing the generator matrix information of reading from GMSU201; The multiplying of the generator matrix information after the displacement that first arithmetic element set 301b, the information bit that is used to finish input and shift register cell 301a export; Second arithmetic element set 301c is used to finish the summation operation of the output of the output of first arithmetic element set 301b and register cell 301d; Register cell 301d, length is 127 bits, is used to deposit the output result of second arithmetic element set 301c.
Shift register cell 301a is with the generator polynomial g of corresponding GMSU201 output I, jDeposit in wherein, carry out binary multiplication with door, i.e. phase and computing from each bit of the information bit of ISU1 input and shift register cell 301a in each of first arithmetic element set 301b simultaneously; Simultaneously, each of first arithmetic element set 301b is connected to the input that second arithmetic element is gathered each XOR gate of 301c with the output of door, finish with register cell 301d in the binary addition of each data, i.e. XOR, the result of XOR deposits among the register cell 301d.
As shown in Figure 6, be the cellular construction of the used output buffers unit OSU4 of present embodiment.
Described OSU4 comprises: register cell set 401, comprise 12 register cells altogether, and length is 127 bits; Data selector unit 402 has 13 input items, is the output of the data selector unit 102 of the output of 12 registers in the register cell set 401 and described ISU1; OSU4 also comprises first memory 403, and size is 8192 bits, and bit wide is 1, second memory 404, and size is 8192 bits, bit wide is 1.The output of first memory 403 and second memory 404 storage data selection unit 402, and output encoder result, first memory unit 403 constitutes the ping-pong operation mode with second memory 404, when promptly first memory 403 being carried out write operation, second memory 404 is carried out read operation, otherwise, when second memory 404 is carried out write operation, first memory 403 is carried out read operation.
The coding method of a kind of LDPC code coder of the present invention, as shown in Figure 7
Step 1: input information position buffer memory
According to user-selected code check, (for 0.4 code check, N is 3048 from the 1st clock cycle to N clock cycle; For 0.6 code check, N is 4572; For 0.8 code check, N is 6096), information bit to be encoded is input among the input-buffer unit ISU1 by bit, and, be connected to three memory 101a simultaneously, on 101b and the 101c, when the bit-order of importing is between 1～2048, under the control of logic control element 5, these information bits are written among the memory 101a, when the bit-order of importing is between 2048～4096, under the control of logic control element 5, these information bits are written among the memory 101b, when the bit-order of importing was between 4096～6096, under the control of logic control element 5, these information bits were written among the memory 101c.
From the 2nd clock cycle to N+1 clock cycle, information bit is exported to memory 101c successively from memory 101a, and when the output order was between 1～2048, information bit was exported from memory 101a, simultaneously, data selector unit 102 is with the data output of memory 101a; When the output order was between 2048～4096, information bit is 102 outputs from the data selector unit, and simultaneously, data selector unit 102 is with the data output of memory 101b; When the output order was between 4096～6096, information bit was from memory 101c output, and simultaneously, data selector unit 102 is with the data output of memory 101c.
Step 2, the output of matrix generator polynomial
With step 1 side by side, from the 2nd clock cycle to N+1 clock cycle, according to user-selected code check, the output from generator matrix memory set 2 successively of the generator polynomial of generator matrix.
Concrete, if the code check that the user selects is 0.4, i.e. the 128th clock from the 2nd clock to subsequently 126 clock cycle so, generator matrix memory cell 201 will be stored in the 1st data g in first memory block to generator matrix memory cell 212 1,1To g 1,12Output.Back to back 127 clock cycle i.e. 255 clocks of the 129th clock to the, and generator matrix memory cell 201 will be stored in the 2nd data g in first memory block to generator matrix memory cell 212 2,1To g 2,12Output.The rest may be inferred, and 127 clock cycle to the end i.e. the individual clock of (N+1-126) individual clock to the (N+1), and generator matrix memory cell 201 will be stored in first memory block last, i.e. the 24th data g to generator matrix memory cell 212 24,1To g 24,12Output.
If the code check that the user selects is 0.6, i.e. the 128th clock from the 2nd clock to subsequently 126 clock cycle so, generator matrix memory cell 201 will be stored in the 1st data g in the 4th memory block to generator matrix memory cell 212 1,1To g 1,12Output.Back to back 127 clock cycle, i.e. 255 clocks of the 129th clock to the, generator matrix memory cell 201 will be stored in the 2nd data g in the 4th memory block to generator matrix memory cell 212 2,1To g 2,12Output.The rest may be inferred, 127 clock cycle to the end, i.e. and the individual clock of (N+1-126) individual clock to the (N+1), generator matrix memory cell 201 will be stored in the 4th memory block last, i.e. the 36th data g to generator matrix memory cell 212 36,1To g 36,12Output.
If the code check that the user selects is 0.8, so from the 2nd clock to subsequently 126 clock cycle, i.e. the 128th clock, generator matrix memory cell 201 will be stored in the 1st data g in the 6th memory block to generator matrix memory cell 211 1,1To g 1,11Output.Back to back 127 clock cycle, i.e. 255 clocks of the 129th clock to the, generator matrix memory cell 201 will be stored in the 2nd data g in the 6th memory block to generator matrix memory cell 211 2,1To g 2,11Output.The rest may be inferred, and 127 clock cycle to the end i.e. the individual clock of (N+1-126) individual clock to the (N+1), and generator matrix memory cell 201 will be stored in the 6th memory block last, i.e. the 48th data g to generator matrix memory cell 211 48,1To g 48,11Output.
Step 3, matrix multiplication operation
With step 1 side by side, from the 2nd clock cycle to N+1 clock cycle, matrix multiplication unit MMU3 set is carried out matrix multiplication operation with the information bit of input-buffer unit ISU1 output and the generator matrix of generator matrix memory cell GMSU2 set output, obtains needed check digit.
Concrete, be example with MMU 301, at the 2nd clock, MMU 301 is with the generator polynomial g of GMSU 201 outputs 1,1Deposit among the shift register 301a, simultaneously, finish following actions m1: carrying out binary multiplication from information bit and each bit of shift register 301a of ISU1 input is mutually and computing; Simultaneously, first arithmetic element set 301b outputs to second arithmetic element set 301c, and the binary addition of finishing with register cell 301d is an XOR, and the result of XOR deposits among the register cell 301d, and the m1 that so far moves finishes.In 126 clock cycle subsequently, shift register 301a carries out right cyclic shift successively, and with the input information bit execution m1.Ensuing 127 clock cycle, i.e. 255 clocks of the 129th clock to the, at the 129th clock, MMU301 is with the generator polynomial g of GMSU201 output 1,2Deposit among the shift register 301a, execution m1 simultaneously, at the 130th clock to 255 clock, shift register 301a carries out right cyclic shift successively, and with the information bit execution m1 of input.The rest may be inferred, is N+1 clock to a last clock, and MMU301 finishes the multiplying of the matrix information of all information bits and GMSU 201 outputs, obtains first check digit vector p 1, i.e. the 1st to the 127th check bit.
With MMU 301 simultaneously, MMU 302 to MMU311, MMU 312 finish the 301 similar computings with MMU, obtain p respectively 2To p 12, i.e. the 128th to 1524 check bit.Certainly, for 0.8 code check, p 12Invalid.
Step 4, the output information buffer memory
With step 1 simultaneously, the 2nd to N+1 clock cycle, the information bit of input-buffer unit ISU1 output outputs to matrix multiplication operation unit MMU3 set participation computing on the one hand, information bit is outputed among the output buffers unit OSU4 on the other hand.
Concrete, the 2nd to N+1 clock cycle, the first memory 403 that data selector 402 is selected the information bit of input to be exported to the back level is stored.
As shown in Figure 6, N+1 clock cycle, MMU 301 to MMU 312 finishes third step, obtains check digit vector p 1To p 12, and output to the register cell set 401 of output buffers unit OSU4, and at this moment, the register pair p in the register cell set 401 1To p 12Deposit.In 127 clock cycle subsequently, promptly N+2 clock be to N+128 clock, p 1By first register cell, 4001 serials output, the data output with first register cell 4001 is selected in data selector unit 402, in 127 clock cycle then, and p 2By second register cell, 4002 serials output, the data output with second register cell 4002 is selected in data selector unit 402, and the rest may be inferred, (N+1+127 * 12) individual clock cycle, p 12By the 12 register cell 4012 serials output, the data output with the 12 register cell 4012 is selected in data selector unit 402; So far, p 1Or p 12All exported and deposit in by serial in first memory 403 or the second memory 404.
If user-selected code check is 0.8, pass through above 4 steps so, whole cataloged procedure finishes.
If user-selected code check is 0.6, to finish whole cataloged procedure so, need again execution in step 1 to step 4, with preceding once different be: in step 1, owing to do not have the information bit input, so do not need information bit is carried out buffer memory, only need canned data position order output successively before; In step 2, generator matrix unit GMSU201 need export the data in the 5th memory block in proper order to generator matrix unit GMSU 212; In step 4, p 1To p 12All exported by serial, but p 12Invalid.So far, 0.6 code check cataloged procedure finishes.
If user-selected code check is 0.4, to finish whole cataloged procedure so, need again execution in step 1 to arrive twice of step 4, different is, in second time implementation: similar with 0.6 code check, in step 1, only need will before the order output successively of canned data position; In step 2, generator matrix unit GMSU201 need export the data in second memory block in proper order to generator matrix unit GMSU 212.In implementation for the third time, in step 1, only need will before the order output successively of canned data position; In step 2, generator matrix unit GMSU201 need export the data in the 3rd memory block in proper order to generator matrix unit GMSU 212; In step 4, p 1To p 12All exported by serial, but p 12Invalid.So far, 0.4 code check cataloged procedure finishes.
When needs are encoded next time, repeat above process, the second memory that different is in the OSU1 that step 4 is used is 404 rather than first memory 403, second memory is 404 and first memory 403 alternations, thereby realizes ping-pong operation.

Claims (10)

1, a kind of encoder apparatus of LDPC sign indicating number, it is characterized in that: mainly by input-buffer unit ISU, generator matrix memory cell GMSU set, matrix multiplication operation unit MMU set, output buffers unit OSU and the logic control element LCU composition that above each several part is controlled;
Input-buffer unit ISU is used for the information bit of the input under the various code checks is carried out buffer memory;
Generator matrix memory cell GMSU set is used to store the information of the generator matrix of various rate codewords correspondences;
MMU set in matrix multiplication operation unit is used to finish the information bit of input and the multiplying of generator matrix;
Output buffers unit OSU is used for check digit and information bit behind the coding are stored;
Logic control element LCU, be used for writing and read the address according to user-selected Rate Control input-buffer unit ISU, the switching of reading the memory cell in address and the control output buffers unit OSU of control generator matrix memory cell GMSU set, the switching of described memory cell is meant, when an end-of-encode, in the time of need encoding, the memory cell in the OSU switches next time;
During coding, according to user-selected code check, under the control of logic control element LCU, information bit to be encoded is deposited among the input-buffer unit ISU, through the register cache information position among the input-buffer unit ISU, this information bit outputs to from input-buffer unit ISU among matrix multiplication operation unit MMU set and the output buffers unit OSU; According to user-selected code check, under the control of logic control element LCU, generator matrix memory cell GMSU set generates generator polynomial, and the generator polynomial of the needed correspondence of will encoding outputs in the matrix multiplication operation unit MMU set from generator matrix memory cell GMSU set; Matrix multiplication operation unit MMU is to carrying out matrix multiplication operation from the information bit of input-buffer unit ISU output and the matrix information of exporting from generator matrix memory cell GMSU, the result of the computing needed check digit of encoding exactly, these check digit are by the parallel output buffers unit OSU that outputs to; In output buffers unit OSU, the information bit from input-buffer unit ISU output is put in order with the check digit of exporting from matrix multiplication operation unit MMU, constitute a complete code word output.
2, the encoder apparatus of a kind of LDPC sign indicating number according to claim 1, it is characterized in that: described generator matrix memory cell GMSU set comprises 12 identical generator matrix memory cell altogether, wherein k GMSU unit is used to store all generator polynomials of individual and (24+k) the individual row piece of k of generator matrix of 0.4 code check, (12+k), store k and all generator polynomials of (12+k) individual row piece of the generator matrix of 0.6 code check, store all generator polynomials of k row piece of the generator matrix of 0.8 code check, wherein 1≤k≤11; The 12nd GMSU unit is used to store all generator polynomials of the 12nd and the 24th row piece of the generator matrix of 0.4 code check, stores all generator polynomials of the 12nd row piece of the generator matrix of 0.6 code check.
3, the encoder apparatus of a kind of LDPC sign indicating number according to claim 1 is characterized in that: described matrix multiplication operation unit MMU set, comprise 12 identical matrix multiplication operation unit altogether, and corresponding with the number of generator matrix memory cell.
4, the encoder apparatus of a kind of LDPC sign indicating number according to claim 1 is characterized in that: described input-buffer unit ISU comprises:
The buffer memory unit set comprises that three identical sizes are 2048 bits, and bit wide is 1 a memory, and the size of described buffer memory unit set is 6144 bits, and the information bit of input is connected to the input of three memories in the buffer memory unit set simultaneously;
The data selector unit, it is input as the data output end of three memories in the buffer, and the data selector unit is exported the data of memory successively according to the order of information bit, constitutes continuous message bit stream.
5, the encoder apparatus of a kind of LDPC sign indicating number according to claim 1 and 2 is characterized in that: described generator matrix memory cell GMSU comprises: first memory block, second memory block, the 3rd memory block, the 4th memory block, the 5th memory block, the 6th memory block; First to the 3rd memory block is used to store the generator matrix information of 0.4 code check, and the 4th and the 5th memory block is used to store the generator matrix information of 0.6 code check, and the 6th memory block is used to store the generator matrix information of 0.8 code check; In when coding, select the difference of code check and coding process according to the user, under the control of LCU, will the encode generator matrix information of needed correspondence of generator matrix memory cell GMSU is exported.
6, the encoder apparatus of a kind of LDPC sign indicating number according to claim 1 is characterized in that: described matrix multiplication operation unit MMU comprises:
Shift register cell, length is 127 bits, is used for depositing from generator matrix memory cell GMSU reading generator matrix information;
First arithmetic element set, comprise altogether identical 127 with door, be used to finish the generator matrix information multiplying after the displacement of output of the information bit of input and shift register cell;
Register cell, length is 127 bits, is used to deposit the output result of second arithmetic element set;
Second arithmetic element set comprises 127 identical XOR gate altogether, is used to finish the summation operation of the output of the output of first arithmetic element and register cell.
7, the encoder apparatus of a kind of LDPC sign indicating number according to claim 6 is characterized in that: the shift register cell of described matrix multiplication operation unit MMU is with the generator polynomial g of corresponding generator matrix memory cell GMSU output I, jDeposit in wherein, respectively with the door carry out binary multiplication what first arithmetic element was gathered, i.e. phase and computing from the information bit of input-buffer unit ISU output and each bit of shift register cell simultaneously; An input that respectively is connected respectively to each XOR gate of second arithmetic element set of first arithmetic element set with the output of door, finish with register cell in the binary addition of each data, be XOR, the result of XOR is deposited in the register cell.
8, the encoder apparatus of a kind of LDPC sign indicating number according to claim 4 is characterized in that: described output buffers unit OSU comprises:
The register cell set, its output to the register cell of MMU unit is deposited, and length is 127 bits;
The data selector unit, it is input as the output of data selector unit among the output of register cell and the described input-buffer unit ISU;
First memory, size are 8192 bits, and bit wide is 1, are used to store the output of data selector unit;
Second memory, size are 8192 bits, and bit wide is 1, are used to store the output of data selector unit;
Described first memory is identical with second memory, and first memory and second memory formation ping-pong operation mode.
9, a kind of coding method that is applied to the encoder apparatus of the described LDPC sign indicating number of claim 1 has following steps:
Step 1: input information position buffer memory
According to user-selected code check, from the 1st clock cycle to N clock cycle, for 0.4 code check, N is 3048; For 0.6 code check, N is 4572; For 0.8 code check, N is 6096, and information bit to be encoded is imported among the input-buffer unit ISU by bit; From the 2nd clock cycle to N+1 clock cycle, the information bit of the 1st clock cycle to N clock cycle is by order output by turn from ISU;
Step 2: matrix generator polynomial output
With step 1 side by side, from the 2nd clock cycle to N+1 clock cycle, according to user-selected code check, the output from generator matrix memory cell GMSU set successively of the generator polynomial of generator matrix;
Step 3: matrix multiplication operation
With step 1 side by side, from the 2nd clock cycle to N+1 clock cycle, MMU set in matrix multiplication operation unit is carried out matrix multiplication operation with the information bit of input-buffer unit ISU output and the generator matrix of generator matrix memory cell GMSU set output, obtains needed check digit;
Step 4: output information buffer memory
With step 1 side by side, the 2nd to N+1 clock cycle, the information bit of input-buffer unit ISU output outputs to matrix multiplication operation unit MMU on the one hand and participates in computing, on the other hand information bit is input among the output buffers unit OSU;
The 2nd to N+1 clock cycle, the memory that the data selector unit among the OSU is selected the information bit of input to be exported to the back level is stored;
N+1 clock cycle, all MMU have finished third step, obtain check digit vector p 1To p 12, and output to the register cell set of OSU, and at this moment, the register pair p in the register cell set 1To p 12Deposit; In 127 clock cycle subsequently, promptly N+2 clock be to N+128 clock, p 1By first register serial output, the data output with first register of register cell set is selected in the data selector unit, in 127 clock cycle then, and p 2By second register serial output, the data output with second register of register cell set is selected in the data selector unit, and the rest may be inferred, to (N+1+127 * 12) the individual clock cycle, and p 1To p 12All exported and be deposited in first memory or the second memory by serial;
If user-selected code check is 0.8, pass through above 4 steps so, whole cataloged procedure finishes;
If user-selected code check is 0.6, to finish whole cataloged procedure so, need again execution in step one to step 4, with preceding once different be: in step 1, owing to do not have the information bit input, so do not need information bit is carried out buffer memory, only need canned data position order output successively before; In step 2, the generator matrix unit need be exported the data in the 5th memory block among the generator matrix memory cell GMSU in proper order; In step 4, p 1To p 12All exported by serial, but p 12Invalid; So far, 0.6 code check cataloged procedure finishes;
If user-selected code check is 0.4, to finish whole cataloged procedure so, need again execution in step one to arrive twice of step 4, different is, in second time implementation: similar with 0.6 code check, in step 1, only need will before the order output successively of canned data position; In step 2, the generator matrix unit need be exported the data in second memory block among the generator matrix memory cell GMSU in proper order; In implementation for the third time, in step 1, only need will before the order output successively of canned data position; In step 2, the generator matrix unit need be exported the data in the 3rd memory block among the generator matrix memory cell GMSU in proper order; In step 4, p 1To p 12All exported by serial, but p 12Invalid; So far, 0.4 code check cataloged procedure finishes.
10, the coding method of a kind of LDPC sign indicating number according to claim 9, it is characterized in that: when needs are encoded next time, repeat the described process of claim 9, the memory that different is in the OSU that step 4 is used is the preceding memory that once not have use in described first memory and the second memory, formation ping-pong operation mode.
CNB2007101197958A 2007-07-31 2007-07-31 A kind of encoder apparatus of LDPC sign indicating number and coding method Expired - Fee Related CN100555879C (en)

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