CN101489135B - Encoder convenient for LDPC long code implementation on FPGA and encoding method - Google Patents
Encoder convenient for LDPC long code implementation on FPGA and encoding method Download PDFInfo
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Abstract
The invention relates to a coder for conveniently implementing a LDPC long code in an FPGA and a coding method. A LDPC coding module receives uncoded data output from a ping-pong buffer group input module and a check matrix output from a Synchronous Dynamic Random Access Memory (SDRAM) check matrix group module, obtains a parity matrix check code after a coding operation, outputs the code to a coding output buffer module for a code rate match, transmits the matched parity matrix check code with a certain length to an interleaving module in the LDPC for a bit combination and a bit interleave and outputs the interleaved coding data. The technical scheme of the invention has advantages of less hardware source, low design complexity, high operation frequency, easy implementation and high reliability, and flexibly implements different application environment demands according to the actual utilization demands and the hardware source conditions.
Description
Technical field
The present invention relates to the digital multimedia broadcast (dmb) via satellite field, particularly relate to encoder and coding method that a kind of convenient for LDPC long code is realized at FPGA.
Background technology
Digital broadcasting has characteristics such as wide coverage, signal volume are big, therefore, and as an important component part of ICT industry, in the national information infrastructure construction, realize having critical role in universal service and the national information security strategy.
In the broadcast channel transmission, transmission medium and other signal source can be introduced a series of influence to signal, and decline, distortion and interference etc. can appear in signal, thereby cause error code, by links such as chnnel coding interweave, can greatly reduce the error rate.
Present mobile multimedia broadcast system carries out video flowing outer encode, interweaves outward, encodes in the LDPC, interweaves in the bit etc. and carries out signal encoding; The interior decoding of LDPC can be corrected some mistakes that outer decoding can't be corrected during decoding.
The DVB-S2 employing Bose-Chaudhuri-Hocquenghem Code of encoding outward, interior coding also are to use the LDPC coding, inside and outside to interweave all be to adopt Bit Interleave.LDPC has extraordinary characteristics: approach very much the performance of shannon limit, and decoding is simple, practicable parallel work-flow is easy to carry out theory analysis and research.
Chinese patent " chnnel coding in a kind of Mobile Multimedia Broadcasting and deinterleaving method " (patent No. is 200610149782.0), the utilization advantage of LDPC algorithm in the communications field done the explanation and some and the concrete relevant declarative description of operation environment of some algorithms, LDPC importance and realization complexity in chnnel coding have been described, but this patent is carried out high complexity and Structured Design to the LDPC check matrix, causes specific implementation and promotes the use difficulty.
Summary of the invention
The frequency height, realize simple, high reliability features.
The object of the invention is achieved by following technical solution:
The encoder that a kind of convenient for LDPC long code is realized at FPGA, it is characterized in that comprising coding controller, ping-pong buffers grouping input module, interleaving block and interior interleaver memory in SDRAM check matrix grouping module, LDPC coding module, coding output buffer module, the LDPC, wherein:
Ping-pong buffers grouping input module: comprise two buffer modules, the data to be encoded A that one of them module stores receives, the data to be encoded B that another module output simultaneously need be encoded;
SDRAM check matrix grouping module: be used for reading the check matrix of FLASH memory and storing; Instruction according to the LDPC coding module is transferred to the LDPC coding module with required check matrix;
The LDPC coding module: be used to receive from the check matrix of SDRAM check matrix grouping module output and the data to be encoded B that exports from ping-pong buffers grouping input module, the computing of encoding obtains parity matrix check code sequence;
Coding output buffer module is used to receive the parity matrix check code sequence from the output of LDPC coding module, and carries out the check code coupling with the bit rate of coding controller output, the parity matrix check code after the output coupling;
Interleaving block in the LDPC: be used to receive the parity matrix check code after the coupling of coding output buffer module output and the data to be encoded B of the computing of not encoding, carrying out bit merges, carry out Bit Interleave according to the interior interleaving data in the interior interleaver memory again, and export the coded data after interweaving;
In the look-up table that interweaves: be used to store interior interleaving data;
Coding controller: ping-pong buffers grouping input module is imported control; SDRAM check matrix grouping module is carried out unloading control; To the control of encoding of LDPC coding module; Coding output buffer module is carried out the bit rate input; Interleaving block in the LDPC is exported control.
In the encoder that FPGA realizes, SDRAM check matrix grouping module comprises SDRAM data-interface, sdram controller and check matrix address control unit at above-mentioned convenient for LDPC long code, wherein:
SDRAM data-interface: storage check matrix;
Sdram controller: read the check matrix in the FLASH memory, and with the verification matrix stores in the SDRAM data-interface; Instruction according to the check matrix address control unit is transferred to the LDPC coding module with the check matrix in the SDRAM data-interface;
The check matrix address control unit: receive the instruction of LDPC coding module, the check matrix that the control sdram controller reads in the SDRAM data-interface is transferred to the LDPC coding module.
In the encoder that FPGA realizes, coding output buffer module comprises check matrix memory and check code o controller at above-mentioned convenient for LDPC long code, wherein:
Check matrix memory: receive from the parity matrix check code sequence of LDPC coding module output, and the parity matrix check code of certain-length is exported to interleaving block in the LDPC according to the instruction of check code o controller;
Check code o controller: the length of controlling parity matrix check code sequence according to the bit rate of coding controller output.
In the encoder that FPGA realizes, interleaving block comprises interleaver memory and LDPC bit interleaver in the LDPC in the LDPC at above-mentioned convenient for LDPC long code, wherein:
Interleaver memory in the LDPC: receive the parity matrix check code of data to be encoded B and the output of coding output buffer module, form bit and merge;
The LDPC bit interleaver: read the coded data after bit merges in the interleaver memory in the LDPC, and the coded data after according to the interior interleaving data in the interior look-up table that interweaves bit being merged carries out Bit Interleave, and the coded data of output after interweaving.
In the encoder that FPGA realizes, the check matrix in the FLASH memory obtains as follows at above-mentioned convenient for LDPC long code:
(1) column weight that sets in advance the HS-LDPC sign indicating number is fixed as 3, generates the check matrix with three sub matrixs;
(2) code length and the row according to the HS-LDPC sign indicating number is heavy, and the sub matrix that will have the check matrix of three sub matrixs generates some block check submatrixs;
(3) heavily be worth divided by the row of described HS-LDPC sign indicating number according to described syndrome matrix code length and obtain a unit check matrix;
(4) described unit check matrix is carried out cyclic shift in all sub matrixs after, obtain the check matrix in the FLASH memory.
In the encoder that FPGA realizes, realize that Methods for Coding is at above-mentioned convenient for LDPC long code in the LDPC coding module: the described data to be encoded B that multiplication unit will import and carry out parallel multiplication and accumulate computing obtaining operation result z from the check matrix of SDRAM check matrix grouping module output; Z is input to first resolves the unit, resolve unit solving equation U*y=z according to first and separate computing, obtain solving result y; Y is sent to second resolves the unit, resolve unit solving equation L*Xp=y according to second and resolve, obtain having the parity matrix check code Xp of parity information; Wherein U is a upper triangular matrix, and L is a lower triangular matrix.
A kind of convenient for LDPC long code comprises the steps: in the coding method that FPGA realizes
(1) computing of encoding obtains the parity matrix check code according to data to be encoded and data to be encoded corresponding check matrix;
(2) described parity matrix check code and bit rate are carried out the coupling of check code, obtain the parity matrix check code of certain-length;
(3) data to be encoded with the parity matrix check code of certain-length in the step (2) and the computing of not encoding carry out the bit merging, obtain amalgamation result;
(4) according to interior interleaving data described amalgamation result is carried out Bit Interleave, the coded data after obtaining interweaving.
The present invention compared with prior art has following advantage:
(1) present most of LDPC matrix all is a long code, and not only complicated but also account for very much resource with common static table searching, technical solution of the present invention can easily realize the LDPC encoding function, and it is few to reach resource, and design is complicated low, the hardware characteristics that frequency of operation is high.
(2) ping-pong buffers of the present invention is to design according to handling time-delay and rate-matched, need not related operation, has and realizes that simply operand is few, reliability height, the characteristics that required hardware resource is few.
(3) LDPC processing speed of the present invention be the frequency that depends on work clock, SDRAM literacy the time of adding up and in the interweave degree of depth and the width of look-up table LUT, therefore can realize different applied environment demands flexibly according to practice demand and hardware resource situation.
Description of drawings
Fig. 1 realizes the workflow diagram of coding method for encoder of the present invention;
Fig. 2 is a SDRAM check matrix grouping module structure chart of the present invention;
Fig. 3 realizes the workflow diagram of coding for LDPC coding module of the present invention;
Fig. 4 exports the buffer module structure chart for the present invention encodes;
Fig. 5 is interleaving block structure chart in the LDPC of the present invention;
Fig. 6 is a coding controller workflow diagram of the present invention.
Embodiment
The present invention is described in further detail below in conjunction with the drawings and specific embodiments:
Be illustrated in figure 1 as encoder of the present invention and realize the workflow diagram of coding method, encoder comprises coding control unit, ping-pong buffers grouping input module as shown in Figure 1, in SDRAM check matrix grouping module, LDPC coding module, coding output buffer module, the LDPC interleaving block and in the look-up table that interweaves, ping-pong buffers grouping input module wherein, comprise two buffer modules, the data to be encoded A that one of them module is used for receiving stores, and another module is carried out coded data B output with needs simultaneously.
Be illustrated in figure 2 as the structure chart of SDRAM check matrix grouping module of the present invention, SDRAM check matrix grouping module is used for reading the check matrix of FLASH memory and storing, and according to the instruction of LDPC coding module required check matrix is transferred to the LDPC coding module.Wherein SDRAM check matrix grouping module comprises SDRAM data-interface, sdram controller and check matrix address control unit, SDRAM data-interface storage check matrix, sdram controller reads the check matrix in the FLASH memory, and with the verification matrix stores in sdram interface, and the check matrix in the sdram interface is transferred to the LDPC coding module according to the instruction of check matrix address control unit; The check matrix address control unit receives the instruction of LDPC coding module, and the check matrix that control SDRAM controller reads in the sdram interface is transferred to the LDPC coding module.
The LDPC coding module receives from the check matrix of SDRAM check matrix grouping module output and the data to be encoded B that exports from the ping-pong buffers grouping module, the computing of encoding obtains parity matrix check code sequence, the specific coding method is: whole cataloged procedure comprises a multiplication unit, first resolves unit and second resolves the unit, wherein two are resolved unit process be converted to a look-up table by equivalence when specific implementations, and multiplication unit carries out parallel multiplication and the accumulation computing obtains operation result z with the data to be encoded B of input with from the check matrix of SDRAM check matrix grouping module output; Z is input to first resolves the unit, U*y=z separates computing according to the first module solving equation, obtains solving result y; Y is sent to second resolves the unit, resolve, obtain having the parity matrix check code Xp of parity information according to the second unit solving equation L*Xp=y; Wherein U is a upper triangular matrix, and L is a lower triangular matrix, is illustrated in figure 3 as the workflow diagram that LDPC coding module of the present invention is realized coding.
Be illustrated in figure 4 as the present invention's output buffer module structure chart of encoding, coding output buffer module is used to receive the parity matrix check code sequence from the output of LDPC coding module, obtain the parity matrix check code of certain-length according to the bit rate of coding controller output, and described parity matrix check code exported to interleaving block in the LDPC, coding output buffer module comprises check matrix memory and check code o controller as seen from Figure 4, wherein the check matrix memory is used to receive the parity matrix check code sequence from the output of LDPC coding module, and according to the parity matrix check code of the instruction of check code o controller output certain-length, the check code o controller is then controlled the length of parity matrix check code sequence according to the bit rate of coding controller output, for example when bit rate is 1/2, the check code sequence is that the coded data of 1152 repetitions constitutes 4608 information bits, when bit rate was 3/4, the check code sequence was that the coded data of 576 repetitions constitutes 2304 information bits.
Be illustrated in figure 5 as interleaving block structure chart in the LDPC of the present invention, interleaving block is used to receive the data to be encoded B that has the parity matrix check code of certain-length and the computing of not encoding after the coupling of coding output buffer module output in the LDPC, carrying out bit merges, again according in the interior interleaving data that interweaves in the look-up table carry out Bit Interleave, and the coded data of output after interweaving, interleaving block comprises interleaver memory and LDPC bit interleaver in the LDPC in the LDPC as seen from Figure 5, wherein the parity matrix check code after the coupling that the interior interleaver memory of LDPC receives data to be encoded B and the output buffer module of encoding is exported forms bit and merges; The LDPC bit interleaver reads the coded data after the bit merging in the interior interleaver memory of LDPC, and according to the interior interleaving data in the interior look-up table that interweaves described coded data is carried out Bit Interleave, and exports the coded data after interweaving.In the interleaving data in the look-up table stores that interweaves, in the LDPC interleaving block according in the look-up table that interweaves finish Bit Interleave.
Be illustrated in figure 6 as coding controller workflow diagram of the present invention, the work of above-mentioned each module of coding controller control comprises ping-pong buffers grouping input module is imported control; SDRAM check matrix grouping module is carried out unloading control; To the control of encoding of LDPC coding module; Coding output buffer module is carried out the bit rate input; Interleaving block in the LDPC is exported control.As seen from Figure 6, it at first carries out check matrix unloading processing coding control, and detection check matrix unloading state, after unloading is finished, carry out the storage of ping-pong buffer module data, and detection cache module state, if satisfy coding requirement, the notice coding module is encoded, is encoded and exports buffer module reception parity check code sequence and detect detection check code length state, if export the parity check code sequence after satisfying yardage rate length requirement, interweave in Bit data after interleaving block will merge in LDPC carries out, and export the back result that interweaves.
The concrete workflow of encoder of the present invention is as described in step (1)-(5):
(1) coding controller is imported control to ping-pong buffers grouping input module, and ping-pong buffers grouping input module receives data to be encoded A and exports data to be encoded B;
(2) under the unloading control of coding controller, SDRAM check matrix grouping module reads the check matrix in the FLASH memory, and commentaries on classics is stored among the SDRAM;
(3) under the coding control of coding controller, the LDPC coding module receives from the check matrix of SDRAM check matrix grouping module output and the data to be encoded B that exports from the ping-pong buffers grouping module, and the computing of encoding obtains parity matrix check code sequence;
(4) coding is exported the parity matrix check code sequence in the buffer module receiving step (3), and mates the parity matrix check code that obtains certain-length with the bit rate of coding controller output;
(5) coding controller will be exported control signal and be transferred to interleaving block in the LDPC, interleaving block receives the parity matrix check code of the certain-length of exporting buffer module output from encoding and the data to be encoded B of the computing of not encoding in the LDPC, carrying out bit merges, the look-up table that interweaves in the basis again carries out Bit Interleave, and exports the coded data after interweaving.
Adopt among the present invention a kind of " the LDPC sign indicating number of highly structural ", be expressed as the HS-LDPC sign indicating number.The HS-LDPC sign indicating number is based on the code Design of on the basis of LDPC sign indicating number check matrix H being carried out highly structural.Encoder specific implementation method comprises following four steps among the present invention: step 1, check matrix produces, utilize the code check of the HS-LDPC sign indicating number that the check matrix generation unit in the encoder sets in advance, column weight and row heavily value generate a parity matrix, column weight with the HS-LDPC sign indicating number when specifically preferred is fixed as 3, generate a check matrix with three sub matrixs, code length and row according to the HS-LDPC sign indicating number is heavy then, the sub matrix of described check matrix is generated some block check submatrixs, then heavily be worth divided by the row of described HS-LDPC sign indicating number and obtain a unit check matrix according to described syndrome matrix code length, at last described verification unit matrix is carried out a check matrix of cyclic shift in all sub matrixs, this process can realize by Matlab structure, leaves in this check matrix in the FLASH memory in advance then and use when coding controller can be read the data in the FLASH memory in the SDRAM check matrix grouping module for coding before the computing of encoding;
Step 2, under coding controller control, from ping-pong buffers grouping input module, read the computing of encoding of data to be encoded piece B and corresponding check matrix, whole cataloged procedure comprises that a multiplication unit, first resolves unit and second and resolves the unit, and wherein two are resolved unit process be converted to a look-up table by equivalence when specific implementation.Described multiplication unit carries out parallel multiplication and accumulation computing with the data to be encoded B and the corresponding check matrix of input.
Step 3, then the operation result z in the step 2 is input to first resolves the unit, and U*y=z separates computing according to the first module solving equation, and wherein y is the solving result of this unit; Then y is sent to second and resolves the unit, resolve, obtain having the parity matrix check code Xp of parity information according to the second unit solving equation L*Xp=y, wherein U and L be on/lower triangular matrix, idiographic flow is as shown in Figure 3.
Step 2 and step 3 process realize in the LDPC coding module.
Step 4 is carried out the bit merging with described parity matrix information bit data Xp and input data (the data to be encoded B among Fig. 1), and with its result data output, the process of resolving realizes in the interleaving block in LDPC, and the look-up table that interweaves in the reference.
Be a specific embodiment of the present invention below:
The input of LDPC encoder is with the 20M clock, the data of 16 bit widths, and lowest order is the data to be encoded symbol of importing at first, and data to be encoded are that unit imports with the LDPC block to be encoded, and each coding is all imported 15 complete blocks to be encoded continuously; To 1/2 code check (4608 is LDPC encoding blocks), the input data length is 15*4608/16=4320 (word); To 3/4 code check (6912 is LDPC encoding blocks), the input data length is 15*6912/16=6480 (word); The implementation procedure explanation, with 1/2 code check is example, each LDPC data to be encoded piece has the 15*4608 bit, ping-pong buffers module grouping input module, receive according to per 4608 bit groupings, when first grouping finishes receiving, switch to another input buffering and continue to receive data, ping-pong buffers module grouping input module, require successively and line output 128 bits are encoded according to the coding digit rate, the coding arithmetic section adopts the 80MHz system clock, the check matrix that the LDPC coding module begins to receive buffered data and read the output in the SDRAM check matrix grouping module after switching buffering carries out simple and computing, XOR and simple table look-up realize the computing of LDPC coding, calculate LDPC Parity Check Bits result with parity matrix check matrix information, obtain the check bit of this grouping, carry out exporting to interleaving block in the LDPC after the code rate coupling through coding output buffer module, check bit and data to be encoded that the interior interleaving block of LDPC will have parity matrix information splice, the look-up table that interweaves in the last basis is realized interweaving in the LDPC piece by tabling look-up, and the output of will encoding.
Technical solution of the present invention has successfully been used on CMMB broadcast channel modulator and has been tested by relevant broadcasting and TV.
The above; only be the embodiment of the best of the present invention, but protection scope of the present invention is not limited thereto, anyly is familiar with those skilled in the art in the technical scope that the present invention discloses; the variation that can expect easily or replacement all should be encompassed within protection scope of the present invention.
The content that is not described in detail in the specification of the present invention belongs to this area professional and technical personnel's known technology.
Claims (6)
1. the encoder realized at FPGA of a convenient for LDPC long code, it is characterized in that comprising coding controller, ping-pong buffers grouping input module, in SDRAM check matrix grouping module, LDPC coding module, coding output buffer module, the LDPC interleaving block and in the look-up table that interweaves, wherein:
Ping-pong buffers grouping input module: comprise two buffer modules, the data to be encoded A that one of them module stores receives, the data to be encoded B that another module output simultaneously need be encoded;
SDRAM check matrix grouping module: be used for reading the check matrix of FLASH memory and storing; Instruction according to the LDPC coding module is transferred to the LDPC coding module with check matrix;
LDPC coding module: be used to receive from the check matrix of SDRAM check matrix grouping module output and the data to be encoded B that exports from ping-pong buffers grouping input module, the computing of encoding obtains parity matrix check code sequence, the LDPC coding module comprises that multiplication unit, first resolves unit and second and resolves the unit
The method of computing of wherein encoding is as follows:
The described data to be encoded B that multiplication unit will be imported and carry out parallel multiplication and the accumulation computing obtains operation result z from the check matrix of SDRAM check matrix grouping module output; Z is input to first resolves the unit, resolve unit solving equation U according to first
*Y=z separates computing, obtains solving result y; Y is sent to second resolves the unit, resolve unit solving equation L according to second
*Xp=y resolves, and obtains having the parity matrix check code Xp of parity information; Wherein U is a upper triangular matrix, and L is a lower triangular matrix;
Coding output buffer module: be used to receive parity matrix check code sequence from the output of LDPC coding module, obtain having the parity matrix check code of certain-length according to the bit rate of coding controller output, and described parity matrix check code is exported to interleaving block in the LDPC;
Interleaving block in the LDPC: be used to receive from the parity matrix check code of coding output buffer module output and the data to be encoded B of the computing of not encoding, carrying out bit merges, again according in the interior interleaving data that interweaves in the look-up table carry out Bit Interleave, and the coded data of output after interweaving;
In the look-up table that interweaves: be used to store interior interleaving data;
Coding controller: ping-pong buffers grouping input module is imported control; SDRAM check matrix grouping module is carried out unloading control; To the control of encoding of LDPC coding module; Coding output buffer module is carried out the bit rate input; Interleaving block in the LDPC is exported control.
2. the encoder that a kind of convenient for LDPC long code according to claim 1 is realized at FPGA, it is characterized in that: described SDRAM check matrix grouping module comprises SDRAM data-interface, sdram controller and check matrix address control unit, wherein:
SDRAM data-interface: storage check matrix;
Sdram controller: read the check matrix in the FLASH memory, and with the verification matrix stores in the SDRAM data-interface; Instruction according to the check matrix address control unit is transferred to the LDPC coding module with the check matrix in the SDRAM data-interface;
The check matrix address control unit: receive the instruction of LDPC coding module, the check matrix that the control sdram controller reads in the SDRAM data-interface is transferred to the LDPC coding module.
3. a kind of convenient for LDPC long code according to claim 1 is characterized in that at the encoder that FPGA realizes: described coding output buffer module comprises check matrix memory and check code o controller, wherein:
Check matrix memory: receive from the parity matrix check code sequence of LDPC coding module output, and the parity matrix check code of certain-length is exported to interleaving block in the LDPC according to the instruction of check code o controller;
Check code o controller: the length of controlling parity matrix check code sequence according to the bit rate of coding controller output.
4. a kind of convenient for LDPC long code according to claim 1 is characterized in that at the encoder that FPGA realizes: interleaving block comprises interleaver memory and LDPC bit interleaver in the LDPC in the described LDPC, wherein:
Interleaver memory in the LDPC: receive the parity matrix check code of data to be encoded B and the output of coding output buffer module, form bit and merge;
The LDPC bit interleaver: read the coded data after bit merges in the interleaver memory in the LDPC, and the coded data after according to the interior interleaving data in the interior look-up table that interweaves described bit being merged carries out Bit Interleave, and the coded data of output after interweaving.
5. a kind of convenient for LDPC long code according to claim 1 is characterized in that at the encoder that FPGA realizes the check matrix in the described FLASH memory obtains as follows:
(1) column weight that sets in advance the HS-LDPC sign indicating number is fixed as 3, generates the check matrix with three sub matrixs;
(2) code length and the row according to the HS-LDPC sign indicating number is heavy, and described sub matrix with check matrix of three sub matrixs is generated some block check submatrixs;
(3) heavily be worth divided by the row of described HS-LDPC sign indicating number according to described syndrome matrix code length and obtain a unit check matrix;
(4) described unit check matrix is carried out cyclic shift in all sub matrixs after, obtain the check matrix in the FLASH memory.
6. a convenient for LDPC long code is characterized in that comprising the steps: in the coding method that FPGA realizes
(1) computing of encoding obtains the parity matrix check code according to data to be encoded and data to be encoded corresponding check matrix,
The method of computing of wherein encoding is as follows:
Multiplication unit is with data to be encoded and check matrix carries out parallel multiplication and the accumulation computing obtains operation result z; Z is input to first resolves the unit, resolve unit solving equation U according to first
*Y=z separates computing, obtains solving result y; Y is sent to second resolves the unit, resolve unit solving equation L according to second
*Xp=y resolves, and obtains having the parity matrix check code Xp of parity information; Wherein U is a upper triangular matrix, and L is a lower triangular matrix;
(2) described parity matrix check code and bit rate are carried out the coupling of check code, obtain the parity matrix check code of certain-length;
(3) data to be encoded with the parity matrix check code of certain-length described in the step (2) and the computing of not encoding carry out the bit merging, obtain amalgamation result;
(4) according to interior interleaving data described amalgamation result is carried out Bit Interleave, the coded data after obtaining interweaving.
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| CN102882633A (en) * | 2011-07-14 | 2013-01-16 | 北京同方吉兆科技有限公司 | Implementation method for CMMB (China Mobile Multimedia Broadcasting) byte interleaving and RS (Reed-solomon) codes in digital wireless signal transmission system |
| CN104868971B (en) * | 2014-02-20 | 2019-12-13 | 上海数字电视国家工程研究中心有限公司 | interleaving mapping method and de-interleaving de-mapping method of LDPC code words |
| CN106209115B (en) * | 2016-06-29 | 2019-09-20 | 深圳忆联信息系统有限公司 | A kind of data processing method and electronic equipment |
| CN109391365B (en) * | 2017-08-11 | 2021-11-09 | 华为技术有限公司 | Interleaving method and device |
| KR102450664B1 (en) * | 2017-09-11 | 2022-10-04 | 지티이 코포레이션 | Method and apparatus for processing LDPC coded data |
| CN108988988B (en) * | 2018-06-29 | 2020-05-19 | 华中科技大学 | RCM (Radar Cross-correlation) encoder and encoding method based on two-stage lookup table of quasi-cyclic matrix |
| TWI677878B (en) * | 2018-10-12 | 2019-11-21 | 慧榮科技股份有限公司 | Encoder and associated encoding method and flash memory controller |
| CN109495115B (en) * | 2018-11-01 | 2022-08-09 | 哈尔滨工业大学 | LDPC decoder based on FPGA and decoding method |
| CN110830048B (en) * | 2019-11-14 | 2021-10-12 | 天津大学 | Error correction method for constructing full-diversity LDPC code based on parity check matrix decomposition |
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