WO2016127853A1

WO2016127853A1 - Encoding device and encoding method for two-dimensional product codes based on extended hamming codes

Info

Publication number: WO2016127853A1
Application number: PCT/CN2016/073141
Authority: WO
Inventors: 张萌; 李保申; 李红; 郭仲亚; 黄成�; 田茜
Original assignee: 东南大学
Priority date: 2015-02-11
Filing date: 2016-02-02
Publication date: 2016-08-18
Also published as: CN104601180B; CN104601180A

Abstract

An encoding device and an encoding method for two-dimensional product codes based on extended hamming codes. The encoding device comprises: an information input cache module, an encoding information storage circuit module, a subcode encoding logical circuit module and an encoding control circuit module. The subcode encoding logical circuit module comprises a reconfigurable row code encoding arithmetic circuit and a reconfigurable column code encoding arithmetic circuit. In the device, a register block is used for information storage, an encoding arithmetic circuit module is then used for two-dimensional product encoding, and an encoding control circuit module is used for controlling each time sequence to implement synchronization of row and column encoding and generation of twin check bits during output of encoding information, so that an encoding delay is greatly reduced, and the throughput of an encoding circuit is increased.

Description

Two-dimensional product code coding device and coding method based on extended Hamming code

Technical field

The invention relates to the field of design and implementation of a digital signal processing system and an error correction coding technology in communication data transmission, in particular to a two-dimensional product code coding apparatus and an encoding method based on an extended Hamming code.

Background technique

Wireless communication is to process the message to be sent in some form, and the information to be transmitted is reliably and accurately transmitted to the receiver through the antenna radio frequency technology. The reliability and accuracy of sending information transmission has always been the goal pursued by wireless communication technology. The error correction coding technique is a technique for performing a certain mathematical operation on the original transmission information in order to improve the transmission reliability of the wireless communication system and reduce the interference of channel noise. The error correction coding is also called channel coding. At the transmitting end, a certain amount of check symbols are added after the original information symbol transmitted according to a certain mathematical algorithm, and the information code is implemented by the receiving end according to the corresponding decoding algorithm by using the check code word. The error detection and correction of the word improves the transmission accuracy of the original information symbol. In the error correction coding technique, the codeword to be transmitted is an information codeword, and the codeword added after being encoded is a check codeword, which is also called redundant information. The purpose of error correction coding is to exchange the highest error correction performance and coding gain with a minimum coding cost to improve the efficiency and reliability of system transmission.

The product code is an error correction code with excellent error correction performance. The product code was proposed by Elias in 1954. It is the first error correction code that can achieve error-free transmission at non-zero code rate after Shannon Information Theory proposes. Due to the hardware level at the time, its application was limited. In 1998, Pyndiah et al. proposed a soft input soft output decoding algorithm for linear block codes based on Chase algorithm and applied it to product code decoding. It has excellent error correction performance and low algorithm complexity, which lays a solid theoretical foundation for the wide application of product codes.

The product code has attracted the attention of many researchers at home and abroad with its excellent error correction performance and low coding and decoding complexity. The United States, Japan, and some European countries have applied product code technology to satellite communications. Companies such as AHA, ALTERA, and XINLNX in the United States have developed flexible coded product code encoding and decoding chips. There is no dedicated chip in this field in China. Product code technology is an important technology in current digital communication, which has caused great concern in the communication industry.

The product code can be divided into two-dimensional, three-dimensional and multi-dimensional product codes according to the number of sub-codes, and the two-dimensional product code is mainly used in practical applications. When the product code is encoded, it is performed in the manner of row and column coding. Therefore, the product code encoder requires a buffer dedicated to store the original information and the encoded information, and finally encodes and outputs. The product code can be divided into a plurality of types according to the type of the subcode, such as a subcode of an RS code, an LDPC code, an extended Hamming code, or a combination of two codes. The coding delay of the product code is a major technical problem in hardware design. Therefore, improving coding efficiency and reducing coding delay while reducing hardware consumption are important items to be studied.

The product code adopts the method of row and column coding in coding, which means that for the two-dimensional product code composed of different subcodes, the encoding has to go through two processes of row and column, and the encoding delay is large; meanwhile, the hardware design of the traditional encoding circuit In the information storage, the read/write memory RAM is used for data information storage and reading. The RAM is divided into two ports and a single port RAM, and the double port reading and writing can be performed at the same time, but only one address bit information can be read at a time, so A product code encoder using RAM storage has a large delay. When the amount of storage is large, the hardware consumption of the register and the RAM is the same, so the register set can be used in the hardware design to realize the storage and reading of the data. It has great advantages in terms of throughput.

Summary of the invention

OBJECT OF THE INVENTION In order to solve the problem of large coding delay in the prior art, the present invention provides a two-dimensional product code encoding apparatus and an encoding method based on an extended Hamming code, which are used for storing and reading data by using a register group. According to the code word parameter of the product code, the size and number of the register are set, and the corresponding timing scheduling algorithm is combined to realize the synchronization of the row and column coding, shortening the coding delay and improving the coding circuit throughput rate.

Technical Solution: In order to achieve the above object, an apparatus for encoding a two-dimensional product code based on an extended Hamming code includes: an information input buffer module, an encoding control circuit module, an encoding information storage circuit module, and a subcode encoding logic circuit module, The information input buffer module is configured to store the encoded original information by using the FIFO memory and output the encoded data stream to the encoded information storage circuit module, and simultaneously output a code enable signal to the encoding control circuit module; the encoding control circuit module, And a method for starting a counter inside the circuit after the code enable signal is valid, and controlling the code information storage circuit module by using a selector control signal and an address control signal in a clock cycle, and finally outputting the coded information and the code output The code information storage circuit module is configured to store the encoded data stream in the clock cycle, and then use the subcode encoding logic circuit according to the selector control signal and the address control signal The module performs subcode encoding and the number of bits of information The stream and check bit data streams are supplied to the encoding control circuit module for outputting the encoded information.

The encoding information storage circuit module includes: four selectors, information bits containing k k bits, according to an encoding rule of the extended Hamming code, the size and the number of the register are determined. Register information register register group, row check register set of row check register containing k nk bits, column check register set of column check register containing k nk bits, double check with nk nk bits A double check register set of registers, the input of each register set being coupled to the output of the corresponding selector, where n is the length of the encoded information subcode and k is the length of the information bit data.

The calculation of the time series scheduling is performed according to the length of the coded information and the number of check bits, and the count range of the internal counter of the code control circuit module is 1 to n+2k.

The subcode encoding logic circuit module includes:

a reconfigurable line code encoding operation circuit, configured to perform extended Hamming code encoding on the line information data stream stored by the coded information storage circuit module, and feed back the encoded line check data stream to the coded information storage circuit module Store

a reconfigurable column code encoding operation circuit, configured to perform extended Hamming code encoding on the column information data stream stored by the encoded information storage circuit module, and feed back the encoded column check data stream to the encoded information storage circuit module Store

The reconfigurable column code encoding operation circuit and the reconfigurable line code encoding operation circuit adopt the same circuit structure.

Correspondingly, the present invention also provides a two-dimensional product code encoding method based on an extended Hamming code, the method comprising the following steps:

(1) The information input buffer module uses the FIFO memory to store the encoded original information and outputs the encoded data stream to the encoded information storage circuit module, and simultaneously outputs the encoding enable signal to the encoding control circuit module;

(2) the encoding control circuit module starts a counter inside the circuit after the encoding enable signal is valid, and controls the subcode encoding logic circuit module by using a selector control signal and an address control signal in a clock cycle;

(3) the coded information storage circuit module stores the encoded data stream in the clock cycle, and then performs subcode coding using the subcode encoding logic circuit module according to the selector control signal and the address control signal. And storing the obtained check bit information, and transmitting the information bit data stream and the check bit data stream to the encoding control circuit module.

(4) The encoding control circuit module obtains complete encoding information according to the information bit data stream and the parity bit data stream, and outputs the encoded output enable signal.

The counting range of the internal counter of the encoding control circuit module is 1 to n+2k, where n is the length of the encoded information, and k is the length of the information bit data.

The code information storage circuit module includes: a selector, an information bit register group, a row check register group, a column check register group, and a double check register group, and each register group is respectively connected with a corresponding selector. The subcode encoding logic circuit module includes a reconfigurable row code encoding operation circuit and a reconfigurable column code encoding operation circuit, and the encoding information storage circuit module in step (3) performs data storage and subcode in the clock cycle. The delivery of the code and data stream includes the following steps:

Count value is 1 to k: information bit registration in which the encoded data stream is sequentially stored in the coded information storage circuit module In the device group, the information bit register group includes k k-bit information bit registers;

The count value is k+1~2*k: the data stored in the information bit register group is sequentially sent to the reconfigurable line code encoding operation circuit as a line information data stream to obtain row check bit data, and the data is obtained. The row check data is sequentially stored in the row check register group, and the row check register group includes k row check registers of the nk bits; at the same time, the bit data of the information bit register group is sequentially changed from the highest bit to the lowest bit. The bit is set to the highest bit, and the same bit of the information bit register k is the lowest bit. The same bit is combined and sent to the reconfigurable column code encoding operation circuit as a column information data stream to be encoded. Detecting bit data, and sequentially storing the column check bit data into a column check register group, wherein the column check register set includes k column check registers of nk bits;

The count value is 2*k+1~n+k: the highest bit to the lowest bit of the column check register group are sent to the reconstructed line code encoding operation circuit as a row information data stream every time, and the obtained The row information data stream is sequentially stored in a double check register set, and the double check register set includes nk nk bit double check registers;

At the same time, in this counting range, the output of the encoded information is synchronously performed, and the data stored in the information bit register and the data stored in the corresponding row check register are used as the upper bits as the upper bits and merged into one n-bit code. Data is sent to the encoding control circuit module, and the encoding control circuit module outputs encoding information, and the encoding output enable is enabled;

The count value is n+k+1~n+2*k: in the counting range n+k+1~2*k, the encoding information in the encoded information storage circuit module is continuously output; in the counting range 2*k +1~3*k, the output coded information is the parallel n-bit data formed by the data in the information bit register and the data in the row check register; in the counting range 3*k+1~n+2*k The output encoded information is a parallel n-bit data formed by combining the data in the column check register and the double check register.

Advantageous Effects: The two-dimensional product code encoding apparatus and encoding method based on extended Hamming code of the present invention use a register set instead of a RAM memory for data storage and reading, thereby avoiding data storage and reading by RAM. At the same time, according to the codeword parameters of the product code, the size and number of the register are set, and the corresponding timing scheduling algorithm is combined to realize the synchronization of the row and column coding, shortening the coding delay, and realizing the double The synchronization of the coding and coding outputs further shortens the delay of the entire coding control process and improves the coding circuit throughput.

DRAWINGS

1 is a schematic diagram of a frame of a wireless communication system;

2 is a schematic diagram of an encoding matrix of a two-dimensional product code;

3 is a diagram of a two-dimensional product code encoding apparatus based on an extended Hamming code according to the present invention;

4 is a diagram of a two-dimensional product code encoding apparatus based on (8, 4) extended Hamming code in the embodiment;

FIG. 5 is a timing chart of a product code storage matrix and a code output of a product code based on a (8, 4) extended Hamming code in the embodiment.

detailed description

The present invention will be further described below in conjunction with the embodiments.

In FIG. 1, the transmitting end of the wireless communication system first performs channel coding on the original signal of the source, performs modulation mapping, and performs digital-to-analog conversion, and finally uses the antenna to transmit the radio frequency signal, and the antenna of the receiving end receives the radio frequency signal, and then performs the modulus. The conversion and demodulation mapping are performed, and finally the channel decoding is performed to finally obtain the transmitted signal information. In the present invention, only the channel coding part, that is, the product code coding in the figure, is used, and the extended Hamming code is used as the subcode for encoding.

For a two-dimensional product code whose subcodes are the same extended Hamming code, when encoding, assume that the subcode codeword parameter is (n, k, d), where n = 2 ^m , m is a positive integer, k = n - 1-m, indicating the number of information bits, d=4 indicates the minimum code distance, which is a fixed value, and m is more than 2 in practical applications. Since the extended Hamming code is also a kind of linear block code, its encoding can be completed by the generator matrix, and the original information to be encoded is first grouped, and each group of k bits is denoted as S, then the information after S encoding is N=S. *G, G is the generator matrix, and N is the n-bit coded information containing the check bits.

After the subcode is encoded, the original k bit length is changed to n bit length. When the code code word is composed, the k bit original information is placed in front, followed by the (n-k) bit check information. Therefore, for a two-dimensional product code composed of an extended Hamming code whose subcode parameter is (n, k, d), the size of the memory matrix is n*n.

In Figure 2, the rows of the matrix represent the row codes of the two-dimensional product code, and the columns represent the column codes. The matrix mainly includes four parts: the information matrix, the row check matrix, the column check matrix and the double check matrix, respectively corresponding to the corresponding Data information.

When the product code is encoded, it can be followed by the first row or the first column. In the invention, the method of synchronous coding of the row and column information bits and then performing the check bit coding can shorten the coding delay of one of the rows and columns, thereby improving the coding efficiency.

In FIG. 3, a two-dimensional product code encoding apparatus based on an extended Hamming code includes: an information input buffer module, an encoding control circuit module, an encoding information storage circuit module, and a subcode encoding logic circuit module, and the subcode encoding logic circuit module mainly includes an internal The line code encoding operation circuit and the reconfigurable column code encoding operation circuit are reconstructed.

Before encoding, the encoded original information is first sent to the information input buffer module, and the encoded original information is converted into the encoded data stream and sent to the encoded information storage circuit. The bit width of the encoded original information may be different from the subcode parameter of the product code, so it is necessary to use a buffer to convert it into a bit width data stream that is consistent with the product code subcode parameter, that is, the length of the subcode information bit. The information input buffer consists of a variable bit width FIFO whose size can be determined by the total amount of encoded original information. After all the encoded original information is stored, the information input buffer is divided by k bit width. The encoded data stream is output to the encoded information storage circuit module, and the encoded enable signal is output to the encoding control circuit module.

The encoder control circuit module has a counter inside, which is started after the code enable signal is valid. The count range is 1~(n+2k), and the count is counted once every (n+2k) clock cycles, counting once per cycle, representing the current code. And the output is done once. After the encoding output is completed, the counter is 0, and the next information input and encoding can be entered.

The subcode encoding logic circuit module mainly includes a reconfigurable row code encoding operation circuit and a reconfigurable column code encoding operation circuit. Since the row code column code adopts the same extended Hamming code, the two circuit structures are the same, and all are the same extended Han. A coding operation circuit of a clear code, which can perform coding of an arbitrary extended Hamming code having a code length smaller than n.

The coded information storage circuit module includes the following parts: (1) four selectors: selector 1, selector 2, selector 3, selector 4; (2) k k-bit information bit registers, ie information bit register set (3) k (nk) bit row check register, that is, row check register group; (4) k (nk) bit column check register, that is, column check register group; (5) (nk) The (nk) bit double check register, that is, the double check register set. The input of each register is connected to the output of the corresponding selector. The encoded data stream is first sent to the selector 1, and the selector 1 stores the encoded data stream in the corresponding information bit register in accordance with the selector 1 control signal and the address control signal of the encoding control circuit. After all the information bit data is stored, that is, after the information bit register group is full, the encoding of the check bit is started. After the encoding is completed, the encoding control circuit takes out the entire codeword from the encoded information storage circuit and outputs the encoded complete information in a row.

The timing scheduling process for the entire device is as follows:

Step 1: Encoding the original information input bit width conversion FIFO. After the FIFO is stored, the parallel output of the encoded data stream is performed according to the k-bit of the codeword parameter, to the coded information storage circuit module, and the code enable signal is output to the code control circuit module. .

Step 2: After the encoding enable signal is valid, the encoding control circuit starts its internal counter, the counting range is 1~(n+2*k), and the encoding phase control is performed, and the encoding information storage circuit module is based on the selector of the encoding controller. The control signal and the address control signal store the corresponding data, and output the information after the encoding, and the specific timing scheduling control operation is as follows:

(1) The count value is 1 to k: the encoded data stream is sequentially stored in the information bit register 1 to the information bit register k.

(2) The count value is k+1~2*k: the start subcode encoding logic circuit module, and the information bit register 1~k data is sequentially sent as a line information data stream to the line code encoding operation circuit for encoding, and the line check data is performed. The stream is sequentially stored in the row check register 1 to the row check register k; at the same time, the highest bit (total k bits) and the next highest bit (total k bits) of the information bit registers 1 to k are up to the lowest bit (total k bits) The bit data is fetched, and the bit of the information bit register 1 is the highest bit, and the same bit of the information bit register k is the lowest bit combination, and is sent as a column information data stream to the column code encoding operation circuit for encoding, and the column check data stream is sequentially output. It is sequentially stored in the column check register 1 to the column check register k.

(3) The count value is 2*k+1 to (n+k): two operations are performed simultaneously during this period.

Operation 1: The line code encoding operation circuit continues to work, and the column code encoding operation circuit stops working. At the same time, the highest bit (total k bits), the next highest bit (total k bits), and the lowest bit (total k bits) of the column check registers 1 to k are sent to the line code encoding operation circuit as a line information data stream every time counting, The row verification information stream is sequentially stored in the double check register 1 to the double check register nk.

Operation 2: In this counting range, the output of the encoding information is synchronously performed, that is, the information bit register 1 and the row check register 1 are used as the upper bits as the upper bits, and the encoded data is merged into an n-bit encoded data to be sent to the encoding control circuit. The coding control circuit inputs the coding information while the code output enable is enabled.

(4) The count value is (n+k+1)~(n+2*k): At this time, the encoded information has been output (nk) group, each group of n bits, and within this counting range, continue to encode information storage. The encoded information is output in the circuit. In the counting range of (2*k+1~3*k), the output information is composed of the data in the information bit register and the contents of the row check register, and the count value is at (3*k+1). When ~n+2*k), the output is parallel n-bit data obtained by combining the data in the column check register and the double check register. The synthesis criterion is as follows: when counting to 3*k+1, the highest bit of the column check registers 1 to k, that is, the kth bit is sequentially taken out, and the kth bit of the column check register 1 is the highest bit. The kth bit of the register k is the lowest bit constituting the k-bit information C1, and C1 is composed of the upper bit and the double check register 1 as n-bit information, and is output to the encoding control circuit, and the encoded information is output therefrom. When counting to 3*k+2, the next highest bit of the column check registers 1 to k, that is, the k-1th bit is sequentially taken out, and the k-1th bit of the column check register 1 is the highest bit, and the column check register k The k-1th bit is the lowest bit constituting the k-bit information C2, and C2 is composed of the bit information of the upper bit and the double check register 2 to constitute n-bit information, and is output to the encoding control circuit, and the encoded information is output therefrom. And so on, until the least significant bit information of the column check register set and the bit information of the double check register set (n-k) constitute n-bit information output.

The above is the workflow of the encoding device. When the encoding operation circuit is between the count value (2*k~n+2*k-1), the encoding output enable is valid, and the rest of the time is invalid.

As can be seen from the above, the encoding apparatus of the present invention requires only (n + 2 * k) clock cycles to complete a full cycle of encoding, and the output of n * n bits of data can be completed within this time.

In this embodiment, the subcode length of the coded information is n=8, and the information bit length is k=4. FIG. 4 is a two-dimensional product code of the (8,4) extended Hamming code of the row code and the column code. Device diagram.

In this device, the encoded data stream is sent to the encoded information storage matrix with a 4-bit width, and the encoding matrix is an 8*8 matrix containing four 4-bit wide information registers and four 4-bit wide rows. Register, 4 4-bit wide column check registers, 4 4-bit wide double check registers, store matrix elements in registers information.

At the beginning of the encoding, the information matrix stores the encoded information, which takes time k=4 cycles; then, after k=4 cycles, the row check matrix and the column check matrix are filled with the check information; When the code is verified, the output of the line code information is synchronously performed, specifically, the information of the first line is first output, that is, the information bit register 1 and the line check register 1 are composed of one line for output, and after nk=4 clock cycles, the output is output. The encoded information of 4 lines is simultaneously encoded, and the double-check information is encoded; in the next k=4 clock cycles, the transmission of the line-coded information is continued.

The specific process of this encoding device throughout the timing scheduling period is as follows:

The first step: the information is transformed into a 4-bit parallel data input value coded information storage circuit by the bit width conversion FIFO for data bit width conversion. At the same time, the code enable signal is input to the code control circuit.

Step 2: The counter inside the encoding control circuit starts counting after receiving the encoding enable signal, and the counting range is 1-16. Each count phase has the following operations:

(1) The count value is 1 to 4, and the information bit register sequentially stores the original coded information.

(2) The count value is 4 to 8: the line code code is synchronized with the column code code, and the coded check information is stored in the line check registers 1 to 4, and the column check registers 1 to 4.

(3) The count value is 9 to 12: the double check code is started, and the 4th bit (the highest bit) of the column check registers 1 to 4 is taken out to form 4-bit data, and encoded, and the coded information after verification is stored. Double check register 1. This is done until all four dual registers are full. At the same time, the information output of the coding matrix of the first to fourth rows is performed. The information bit register is the upper 4 bits, and the row check information register is the lower 4 bits.

(4) The count value is 13 to 16: the output of the column check information and the double check information is performed, and the specific output operation is as shown in FIG. 5, and the information in the information matrix in FIG. 5(a) and FIG. 5(b) Starting with I, the row check information starts with R, the column check information starts with C, and the double check information starts with D. In the coding matrix, each data is stored as shown in the figure, and output is output in rows, and the corresponding output coding information is sequentially information of each row of the matrix.

Thus, after 16 clock cycles, the encoding and encoding outputs are all completed, and a total of 64 bits of information are output.

Claims

A two-dimensional product code encoding device based on an extended Hamming code, characterized in that the device comprises: an information input buffer module, an encoding control circuit module, an encoding information storage circuit module and a subcode encoding logic circuit module, and the information input buffer module For storing the encoded original information by using a FIFO memory and outputting the encoded data stream to the encoded information storage circuit module, and simultaneously outputting a coded enable signal to the encoding control circuit module; the encoding control circuit module is used in the After the code enable signal is valid, the counter inside the circuit is started, and the code information storage circuit module is controlled by the selector control signal and the address control signal in the clock cycle, and finally the coded information and the coded output enable signal are output; The encoding information storage circuit module is configured to store the encoded data stream in the clock cycle, and then use the subcode encoding logic circuit module to perform subcode according to the selector control signal and the address control signal Encoding and information bit data stream and check digit data The stream is supplied to the encoding control circuit module for outputting the encoded information.
The apparatus according to claim 1, wherein the coded information storage circuit module comprises: four selectors, an information bit register containing k k bits of information bit registers. Group, row check register set containing k nk bits of row check register, column check register set of column check register containing k nk bits, double check of double check register containing nk nk bits The register set, the input of each register set is connected to the output of the corresponding selector, where n is the length of the encoded information subcode and k is the length of the information bit data.
The two-dimensional product code encoding apparatus based on the extended Hamming code according to claim 2, wherein the counting range of the internal counter of the encoding control circuit module is 1 to n+2k.
The apparatus according to claim 1, wherein the subcode encoding logic circuit module comprises:

a reconfigurable line code encoding operation circuit, configured to perform extended Hamming code encoding on the line information data stream stored by the coded information storage circuit module, and feed back the encoded line check data stream to the coded information storage circuit module Store

a reconfigurable column code encoding operation circuit, configured to perform extended Hamming code encoding on the column information data stream stored by the encoded information storage circuit module, and feed back the encoded column check data stream to the encoded information storage circuit module Store

The reconfigurable column code encoding operation circuit and the reconfigurable line code encoding operation circuit adopt the same circuit structure.
A two-dimensional product code encoding method based on extended Hamming code, characterized in that the method comprises the following steps Step:

(1) The information input buffer module uses the FIFO memory to store the encoded original information and outputs the encoded data stream to the encoded information storage circuit module, and simultaneously outputs the encoding enable signal to the encoding control circuit module;

(2) the encoding control circuit module starts a counter inside the circuit after the encoding enable signal is valid, and controls the subcode encoding logic circuit module by using a selector control signal and an address control signal in a clock cycle;

(3) the coded information storage circuit module stores the encoded data stream in the clock cycle, and then performs subcode coding using the subcode encoding logic circuit module according to the selector control signal and the address control signal. And storing the obtained check bit information, and transmitting the information bit data stream and the check bit data stream to the encoding control circuit module.

(4) The encoding control circuit module obtains complete encoding information according to the information bit data stream and the parity bit data stream, and outputs the encoded output enable signal.
The two-dimensional product code encoding method based on the extended Hamming code according to claim 5, wherein the internal counter of the encoding control circuit module has a counting range of 1 to n+2k, wherein n is the encoding information subcode. The length, k is the length of the information bit data.
The method according to claim 6, wherein the coded information storage circuit module comprises: a selector, an information bit register group, a row check register group, and a column check register. a group, a double check register set, each register set is respectively connected with a corresponding selector, the subcode encoding logic circuit module comprises a reconfigurable line code encoding operation circuit and a reconfigurable column code encoding operation circuit, step (3) The coded information storage circuit module performs data storage, subcode encoding, and data stream transmission in the clock cycle, and includes the following steps:

The count value is 1 to k: the encoded data stream is sequentially stored in an information bit register group in the encoded information storage circuit module, and the information bit register group includes k k-bit information bit registers;

The count value is k+1~2*k: the data stored in the information bit register group is sequentially sent to the reconfigurable line code encoding operation circuit as a line information data stream to obtain row check bit data, and the data is obtained. The row check data is sequentially stored in the row check register group, and the row check register group includes k row check registers of the nk bits; at the same time, the bit data of the information bit register group is sequentially changed from the highest bit to the lowest bit. The bit is set to the highest bit, and the same bit of the information bit register k is the lowest bit. The same bit is combined and sent to the reconfigurable column code encoding operation circuit as a column information data stream to be encoded. Detecting bit data, and sequentially storing the column check bit data into a column check register group, wherein the column check register set includes k column check registers of nk bits;

The count value is 2*k+1~n+k: the highest bit to the lowest bit of the column check register group is counted as a line every count The data stream is sent to the reconstructed line code encoding operation circuit, and the obtained line information data stream is sequentially stored in a double check register group, and the double check register group includes n-k n-k bits double check registers;

At the same time, in this counting range, the output of the encoded information is synchronously performed, and the data stored in the information bit register and the data stored in the corresponding row check register are used as the upper bits as the upper bits and merged into one n-bit code. Data is sent to the encoding control circuit module, and the encoding control circuit module outputs encoding information, and the encoding output enable is enabled;

The count value is n+k+1~n+2*k: in the counting range n+k+1~2*k, the encoding information in the encoded information storage circuit module is continuously output; in the counting range 2*k +1~3*k, the output coded information is the parallel n-bit data formed by the data in the information bit register and the data in the row check register; in the counting range 3*k+1~n+2*k The output encoded information is a parallel n-bit data formed by combining the data in the column check register and the double check register.