CN111211793B

CN111211793B - Parallel TPC coding method based on Hamming code

Info

Publication number: CN111211793B
Application number: CN202010084985.6A
Authority: CN
Inventors: 周敬权; 范道松; 郝筱鲲
Original assignee: Chengdu Yeruan Technology Co ltd
Current assignee: Chengdu Yeruan Technology Co ltd
Priority date: 2020-02-10
Filing date: 2020-02-10
Publication date: 2023-08-04
Anticipated expiration: 2040-02-10
Also published as: CN111211793A

Abstract

The invention discloses a design method of TPC coding applied to the communication field channel coding, which can detect errors and correct errors in the data transmission of the channel coding, and greatly shortens the coding time through parallel TPC coding, thereby improving the coding processing speed. The generation matrix of different encoders is selected according to different data amounts, and mainly the generation matrix of the encoding has different output data clocks. The serial coding of the two-dimensional TPC is converted into parallel coding by utilizing the serial-parallel conversion idea, so that the data processing time is improved, and the method has the advantages that any data stream is input, the coding times are only twice, and the same time is consumed for different data streams; compared with the traditional serial TPC coding, the time consumption is greatly reduced, the TPC coding processing speed is improved by utilizing the internal resources of the FPGA, the TPC coding with different widths can be converted into parallel coding, and the TPC coding is finished through the parallel coding under the condition that the system clock is unchanged.

Description

Parallel TPC coding method based on Hamming code

Technical Field

The invention relates to a channel coding method applied to the field of communication, in particular to a parallel TPC coding method based on Hamming codes.

Background

With the development of communication technology, communication distance is longer and longer, noise exists in the process of transmitting signals, and fading occurs. The multipath interference and the like can cause serious distortion of signals, so that the error rate can be ensured to be within an allowable range through forward error control to a certain extent, and the transmission efficiency is improved.

Turbo product codes (TPC, turbo Product Code) have parallel structures of decoding performance close to shannon's limit and high-speed decoding, and have been widely used in wireless communication in recent years.

Disclosure of Invention

The invention aims to provide a parallel TPC coding method based on Hamming codes, which solves the problems that the processing speed of TPC coding is improved by utilizing internal resources of an FPGA, TPC codes with different widths can be converted into parallel codes, the TPC codes are finished through parallel codes under the condition of unchanged system clock, and the time is shortened and the speed is improved.

The invention is realized by the following technical scheme:

a hamming code-based parallel TPC coding method, comprising: selecting a coding mechanism and a counting and storing mechanism according to the size of the coded data; an input and output clock is calculated from the pre-encoding data and the post-encoding data.

The working principle of the invention is as follows: acquiring a data stream of a system, wherein the data stream has the size of k ² Calculating a data output clock; calculating the generation matrix and the storage mechanism size of the data encoder according to the data stream size; reading data according to a row, and simultaneously encoding the data by a plurality of encoders to finish parallel encoding, wherein the encoding mode adopts TPC encoding; when the data is encoded by the encoder, encoding single bits according to the single bits and outputting the single bits; and outputting the data according to a proper clock after the encoding is finished.

Further, according to the size of the coded data stream, N parallel encoders are used to implement the parallel coding method, where the encoders are further divided into a row encoder and a column encoder.

Further, a row code or column code generator matrix is selected according to the size of the encoded data stream, and the input/output of the encoder is one bit input/output. The data generated by the encoder is n bits in total, n takes the integer power of 2, the output format is k data original code bits, n-k supervision code elements, and the relation is 2 ^n-k ＝n。

Further, depending on the size of the data stream, the manner in which the data is stored in the storage mechanism may be different. Wherein the deposit mechanism comprises three deposit mechanisms, namely a deposit mechanism A1, a deposit mechanism A2 and a deposit mechanism A3.

Further, the raw data is stored in columns. The purpose of this deposit is to accomplish simultaneous encoding by multiple row encoders. And the coding speed is improved.

Further, the line code data continues to be stored in columns, unlike the storing mechanism A1, where the data is stored in n-k more lines

Further, the encoded data are integrated together and added to the data frame header to adjust the output sequence.

Compared with the prior art, the invention has the following advantages and beneficial effects:

1. the invention relates to a parallel TPC coding method based on Hamming codes, which is characterized in that any data stream is input, the coding times are only twice, and the same time is consumed for different data streams;

2. compared with the traditional serial TPC coding, the Hamming code-based parallel TPC coding method provided by the invention has the advantages that the time consumption is greatly reduced;

3. the invention relates to a Hamming code-based parallel TPC coding method, which utilizes the internal resources of an FPGA to improve the TPC coding processing speed, can convert TPC codes with different widths into parallel codes, and is greatly completed through the parallel codes under the condition of unchanged system clock.

Drawings

The accompanying drawings, which are included to provide a further understanding of embodiments of the invention and are incorporated in and constitute a part of this application, illustrate embodiments of the invention. In the drawings:

FIG. 1 is a flow chart of a TPC parallel coding system embodying the present invention;

fig. 2 is a block diagram of a TPC parallel coding system in accordance with an embodiment of the present invention.

Detailed Description

For the purpose of making apparent the objects, technical solutions and advantages of the present invention, the present invention will be further described in detail with reference to the following examples and the accompanying drawings, wherein the exemplary embodiments of the present invention and the descriptions thereof are for illustrating the present invention only and are not to be construed as limiting the present invention.

Example 1

As shown in fig. 1-2, the invention discloses a parallel TPC coding method based on hamming codes, which comprises the following specific implementation modes: storing original data into an asynchronous FIFO1 with a certain clock, reading the data to a RAM1 through a high clock, and preparing for line coding; the read data of the RAM1 is coded in rows and stored in the RAM2; the data read out by the RAM2 are column-coded and stored in the RAM3; the data stored in the RAM3 has completed TPC encoding and is finally added to the FIFO2 together with a suitable frame header, written in at a high clock, and read out at a matched clock.

Example 2

Based on embodiment 1, as shown in fig. 1-2, the invention discloses a parallel TPC coding method based on hamming codes, which comprises the following specific implementation modes: depending on the external module input, its data input clock will determine the encoded data FIFO2 output clock. The readouts are then read out in a sequence to the RAM1 to be encoded. In a specific order, taking a two-dimensional matrix with subcodes as extended Hamming codes (n+1, k, delta) as an example, the data quantity of the one-time input FIFO1 is k ² Record A _i，j (i, j=1, 2..k). Is stored into RAM1 in the format of

Example 3

Based on the above embodiment, as shown in fig. 1-2, the invention discloses a hamming code-based parallel TPC coding method, which is implemented by the following steps: reading out data from the RAM1 according to the rows to an encoder for encoding, wherein the input and output of the encoder are single bits; single-bit input/output can be realized according to the system code (original data, check code, parity check code), and the end of line coding is stored into RAM2 in the format of

Example 4

Based on the above embodiment, as shown in fig. 1-2, the invention discloses a hamming code-based parallel TPC coding method, which is implemented by the following steps: reading out the output of the RAM2 according to the row, continuing to an encoder for column coding, and storing the column coding into the RAM3; the data amount at this time is (n+1) ² 。

Example 5

Based on the above embodiment, as shown in fig. 1-2, the invention discloses a hamming code-based parallel TPC coding method, which is implemented by the following steps: the RAM3 data is output to the FIFO with the data frame header added before being read out according to an appropriate clock, the output clock of which depends on the data size.

The design concept of the encoder in the row encoding and the column encoding is derived from the Hamming code concept, the hamming module inputs 1 bit, stores the first k bits of data into the register unit, generates a supervision code through generating a matrix after the kth data is input, can perform input and output simultaneously in the whole encoder, and can meet the design requirement when the data differ by a few clock cycles, and the specific design time delay is determined according to the system requirement, so that the smaller the specific design time delay is in principle the better.

The foregoing description of the embodiments has been provided for the purpose of illustrating the general principles of the invention, and is not meant to limit the scope of the invention, but to limit the invention to the particular embodiments, and any modifications, equivalents, improvements, etc. that fall within the spirit and principles of the invention are intended to be included within the scope of the invention.

Claims

1. A hamming code-based parallel TPC coding method, comprising: selecting a coding mechanism and a counting and storing mechanism according to the size of the coded data; calculating an input clock and an output clock according to the data before encoding and the data after encoding;

the input and output of the encoder are one bit input and output according to the size of the encoded data stream, the data generated by the encoder is n bits in total, n takes the integer power of 2, the output format is k data original code bits, n-k supervision code elements, and the relation is 2 ^n-k ＝n；

According to different data flow sizes, data are stored in a storage mechanism in different modes, wherein the storage mechanism comprises at least three storage mechanisms, namely a storage mechanism A1, a storage mechanism A2 and a storage mechanism A3;

storing the original data of the storage mechanism A1 according to the columns;

storing the row coding data of the storing mechanism A2 according to columns, wherein n-k rows are needed for storing the rows of the data, which are different from the storing mechanism A1;

the stock mechanism A3 integrates the coded data and adds the data frame head to adjust the output sequence.

2. The hamming code-based parallel TPC coding method of claim 1, wherein N parallel encoders are used, including a row encoder and a column encoder, depending on the size of the coded data stream.