CN106788466A - Turbo code coding and decoding chip for minimizing communication system - Google Patents
Turbo code coding and decoding chip for minimizing communication system Download PDFInfo
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- CN106788466A CN106788466A CN201611144967.2A CN201611144967A CN106788466A CN 106788466 A CN106788466 A CN 106788466A CN 201611144967 A CN201611144967 A CN 201611144967A CN 106788466 A CN106788466 A CN 106788466A
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- decoding
- turbo code
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
- H03M13/29—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes combining two or more codes or code structures, e.g. product codes, generalised product codes, concatenated codes, inner and outer codes
- H03M13/2957—Turbo codes and decoding
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
- H03M13/65—Purpose and implementation aspects
- H03M13/6502—Reduction of hardware complexity or efficient processing
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L1/00—Arrangements for detecting or preventing errors in the information received
- H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
- H04L1/0056—Systems characterized by the type of code used
- H04L1/0064—Concatenated codes
Abstract
The invention provides a kind of Turbo code coding and decoding chip for minimizing communication system, digital intermediate frequency signal is input into the input buffer storage of Turbo code coding module during coding, data are read by encoding control circuit to be encoded, output data to Hamming code coding module and complete Hamming code coding；During decoding, digital intermediate frequency signal input Hamming code decoding module completes Hamming code decoding, export again to the buffer storage of Turbo code decoding module, different RAM are write according to different delays mode control data by MUX, Turbo code decoding iteration is completed by decoding control circuit control component decoder A, component decoder B, until decoding result meets bit error rate requirement, decoding intermediate data storage is in decoding normalization memory array.The present invention realizes the integrated of Turbo code encoder and decoder, reduces algorithm complex, reduces the input pin and memory number of coder, reduces memory area, it is easy to which chip is realized, reduces and realize power consumption.
Description
Technical field
The invention belongs to communication technical field, it is related to a kind of signal of communication process chip, more particularly to a kind of Turbo code to compile
Coding chip, can simultaneously meet coding and decoding demand of the miniaturization communication system to Turbo code.
Background technology
The Turbo code coding and decoding function of legacy communications system do not have integrated, and coding and decoding is no and other codes are cascaded, and
Decoding iteration number of times is 4, and complexity is high, as shown in figure 1, memory is dispersed in around each functional block, size, shape difference compared with
Greatly, as shown in Fig. 2 due to there is above mentioned problem, its way of realization is typically realized using FPGA.If applied in a communications system
Then have the following disadvantages：
1st, because decoding iteration unit is larger, and decoding iteration number of times is 4, general Turbo code decoding module rule
Mould is big, occupancy FPGA resource is more, and power consumption is larger, limits the performance of other functional module performances of communication system.
2nd, Turbo code codec module has used a large amount of memories, memory to be dispersed in around each functional block, size,
Shape difference is larger, causes the larger of memory, and be unfavorable for that chip is realized.
The content of the invention
In order to overcome the deficiencies in the prior art, the present invention to provide a kind of Turbo code for minimizing communication system and compile
Code chip, using two-stage iterative decoding, while Turbo code and Hamming code are cascaded, will encode the storage with decoding module
Device is normalized design, and to reduce amount of memory and area, rear end layout, meets communication system when being easy to chip to realize
Application demand to minimizing the Turbo code coder of low-power consumption.
The technical solution adopted for the present invention to solve the technical problems is：A kind of Turbo code coding and decoding chip, including
Turbo code decoding module, Turbo code coding module, Hamming code coding module and Hamming code decoding module, wherein Turbo code are translated
Code module includes MUX MUX, input buffer storage RAM_in and Turbo code decoding circuit, Turbo code decoding circuit
Including decoding normalization memory array, component decoder A, component decoder B and decoding control circuit；Turbo code encodes mould
Block includes input buffer storage RAM_in, encoding control circuit and coding normalization memory array；
In coding work pattern, digital intermediate frequency signal is input to the input buffer storage of Turbo code coding module
RAM_in, the data in RAM_in are read by encoding control circuit, are encoded according to the coding rule of Turbo code, in generation
Between data storage in coding normalization memory array, it is complete that Turbo code coding module outputs data to Hamming code coding module
Into Hamming code coding；
In work decoding pattern, Hamming code decoding module will be first input into by the digital intermediate frequency signal for deinterleaving, it is complete
Into Hamming code decoding, export to the buffer storage RAM_in of Turbo code decoding module, by MUX MUX11 according to not
Different RAM are write with mode control data is postponed, is completed by decoding control circuit control component decoder A, component decoder B
Turbo code decoding iteration, until decoding result meets bit error rate requirement, decoding intermediate data storage is in decoding normalization memory
In array.
The beneficial effects of the invention are as follows：
1) present invention greatly reduces algorithm complex due to being cascaded using two-stage iterative decoding and Hamming code；
2) present invention is normalized design due to that will encode with the memory of decoding module, greatly reduces memory number
Mesh and area.
3) present invention substantially reduces the volume and power consumption of Trubo CODECs due to using chip implementation.
Brief description of the drawings
Fig. 1 is traditional Turbo code coder decoding iteration block diagram；
Fig. 2 is traditional Turbo code coder memory distribution block diagram；
Fig. 3 is Turbo code coding and decoding chip structure block diagram of the present invention；
Fig. 4 is Turbo code coding and decoding chip decoding module block diagram of the present invention；
Fig. 5 is Turbo code coding and decoding chip decoding circuit block diagram of the present invention；
Fig. 6 is Turbo code coding and decoding chip coding module block diagram of the present invention；
Fig. 7 is the exemplary application map of Turbo code coding and decoding chip of the present invention.
Specific embodiment
The present invention is further described with reference to the accompanying drawings and examples, and the present invention includes but are not limited to following implementations
Example.
Turbo code coding and decoding integrated chip of the invention has Turbo code decoding module 1, Turbo code coding module 3, Hamming
Code coding module 2, Hamming code decoding module 4, wherein Turbo code decoding module are by MUX MUX11, input buffer-stored
Device RAM_in 12 and Turbo code decoding circuit 13 are constituted, Turbo code coding module by input buffer storage RAM_in 31,
Encoding control circuit 32 and coding normalization memory array 33 are constituted, and Turbo code decoding circuit is by decoding normalization memory
Array 131, component decoder A 132, component decoder B 133 and decoding control circuit 134 are constituted.
The chip encoding function and decoding function are separate, in coding work pattern, digital intermediate frequency signal are input into
To input buffer storage RAM_in 31, the data in RAM_in 31 are read by encoding control circuit 32, according to Turbo code
Coding rule is encoded, encoding control circuit 32 generation intermediate data storage in coding normalization memory array 33,
The data of the output of Turbo code coding module 3 have the feature of Turbo code, export and complete the Chinese to the Hamming code coding module 2 of rear class
Exported after plain code coding；In work decoding pattern, Hamming code decoding will be first input into by the digital intermediate frequency signal for deinterleaving
Module 4, completes Hamming code decoding, exports to buffer storage RAM_in 12, by MUX MUX11 according to different delays
Mode control data writes different RAM, controls component decoder A 132, component decoder B complete by decoding control circuit 134
Into Turbo code decoding iteration, until decoding result meets bit error rate requirement, decoding intermediate data storage is in decoding normalization storage
In device array 131.
Above-mentioned Turbo code coding and decoding chip, Turbo code encoder and decoder are integrated in a chips；By subtracting
Few decoding iteration number of times reduction algorithm complex, while Turbo code and Hamming code cascade are brought with making up iterations reduction
Reliability reduction defect；Polylith input buffer storage is write data into by selector timesharing, largely to reduce chip
Input pin；The memory of encoder and decoder is normalized design respectively, to reduce memory number, reduces storage
Device area.The chip reduces algorithm complex, reduces the input pin and memory number of coder, reduces storage
Device area, it is easy to which chip is realized, reduces and realize power consumption.
As shown in figure 3, chip of the invention includes that Turbo code decoding module 1, Turbo code coding module 3, Hamming code are compiled
Code module 2, Hamming code decoding module 4, wherein Turbo code decoding module is by MUX MUX11, input buffer storage
RAM_in 12 and Turbo code decoding circuit 13 are constituted, and Turbo code coding module is by input buffer storage RAM_in 31, volume
Code control circuit 32 and coding normalization memory array 33 are constituted, and Turbo code decoding circuit is by decoding normalization memory array
Row 131, component decoder A 132, component decoder B 133 and decoding control circuit 134 are constituted.
The chip by reduce decoding iteration number of times reduction algorithm complex, while by Turbo code and Hamming code cascade with
Make up the defect that iterations reduces the reliability reduction for bringing；Polylith input buffering is write data into by selector timesharing to deposit
Reservoir, largely to reduce chip input pin；The memory of encoder and decoder is normalized design respectively, to reduce
Memory number, reduces memory area.
Turbo code decoding iteration number of times is 2 in the present embodiment.
Turbo code and Hamming code are cascaded in the present embodiment.
Memory in the present embodiment to Turbo code coding and decoding portion has carried out normalization design, normalization design
Memory size unification afterwards, negligible amounts, area are smaller.
The operation principle of whole chip is as follows in the present embodiment：Encoding function and decoding function are separate, in coding work
During operation mode, source data first passes through Hamming code coding, then carries out Turbo code coding；In work decoding pattern, the number for receiving
Decoded according to Turbo code is first passed through, then decoded by Hamming code.
An application example of the invention is as shown in Figure 7.It is the practical application in communication system, and the chip can be simultaneously
It is operated in transmitting and receives loop, in loop is received, reception antenna 1 receives radiofrequency signal, respectively enters down coversion 2, frame
Enter Turbo code coding and decoding chip 8 after synchronous 3, bit synchronization 4, demodulation 5, solution albefaction 6 and deinterleaving 7, the data after deinterleaving are first
First input Hamming code decoding module 4, completes Hamming code decoding, exports and gives buffer storage RAM_in12, by MUX
MUX11 writes different RAM according to different delays mode control data, and component decoder A is controlled by decoding control circuit 134
132nd, component decoder B completes Turbo code decoding iteration, until decoding result meets bit error rate requirement, decoding intermediate data is deposited
Storage is in decoding normalization memory array 131.
Relevant information is exported after the decoding for completing Turbo code.
In loop is sent, digital intermediate frequency signal is input to input buffer storage RAM_ by Turbo code coding and decoding chip 8
In 31, the data in RAM_in 31 are read by encoding control circuit 32, are encoded according to the coding rule of Turbo code, are compiled
In coding normalization memory array 33, Turbo code coding module 3 is exported the intermediate data storage of the generation of code control circuit 32
Data there is the feature of Turbo code, export and exported after completing Hamming code coding to the Hamming code coding module 2 of rear class, respectively
Into the 9, albefaction 10 that interweaves, modulation 11, up-conversion 12, finally sent by transmission antenna 13.With mention in background technology
Tradition application is compared, and traditional Turbo code coder is realized using FPGA, is disperseed using four decoding iterations, and memory
Around functional block, cause to realize that power consumption steeply rises, be not suitable for minimizing platform.
Chip of the present invention reduces algorithm complex using decoding iteration twice, while using Turbo code and Hamming code level
Connection, improves reliability, not only small volume, and power consumption is less than traditional FPGA implementations.
Under some special applications, application of the invention can also be further expanded.It is of the invention to realize that index is not less than
FPGA implementations, therefore, the present invention can be also used for the Turbo code coding and decoding of communication system on large scale equipment.
Claims (1)
1. a kind of Turbo code coding and decoding chip for minimizing communication system, including Turbo code decoding module, Turbo code volume
Code module, Hamming code coding module and Hamming code decoding module, it is characterised in that：Wherein Turbo code decoding module includes multichannel
Selector MUX, input buffer storage RAM_in and Turbo code decoding circuit, Turbo code decoding circuit include that decoding is normalized
Memory array, component decoder A, component decoder B and decoding control circuit；Turbo code coding module includes that input is buffered
Memory RAM _ in, encoding control circuit and coding normalization memory array；In coding work pattern, digital intermediate frequency signal
The input buffer storage RAM_in of Turbo code coding module is input to, the data in RAM_in is read by encoding control circuit,
Coding rule according to Turbo code is encoded, generation intermediate data storage in coding normalization memory array, Turbo
Code coding module outputs data to Hamming code coding module and completes Hamming code coding；In work decoding pattern, will be handed over by solution
The digital intermediate frequency signal knitted is input into Hamming code decoding module first, completes Hamming code decoding, exports to Turbo code decoding module
Buffer storage RAM_in, writes different RAM, by translating by MUX MUX11 according to different delays mode control data
Code control circuit control component decoder A, component decoder B complete Turbo code decoding iteration, until decoding result meets error code
Rate requirement, decoding intermediate data storage is in decoding normalization memory array.
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111211793A (en) * | 2020-02-10 | 2020-05-29 | 成都烨软科技有限公司 | Parallel TPC coding method and device based on Hamming code |
| CN111865336A (en) * | 2020-04-24 | 2020-10-30 | 北京芯领航通科技有限公司 | Turbo decoding storage method and device based on RAM bus and decoder |
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| CN1645752A (en) * | 2005-01-21 | 2005-07-27 | 清华大学 | Coding and decoding scheme for Turbo code and multi-dimensional modulating cascade system |
| CN101394189A (en) * | 2001-05-11 | 2009-03-25 | 高通股份有限公司 | Buffer architecture for a turbo decoder |
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| KR100370780B1 (en) * | 2000-03-15 | 2003-02-05 | 학교법인 포항공과대학교 | Coding/decoding method and apparatus of turbo code concatenated by Hamming code |
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN111211793A (en) * | 2020-02-10 | 2020-05-29 | 成都烨软科技有限公司 | Parallel TPC coding method and device based on Hamming code |
| CN111211793B (en) * | 2020-02-10 | 2023-08-04 | 成都烨软科技有限公司 | Parallel TPC coding method based on Hamming code |
| CN111865336A (en) * | 2020-04-24 | 2020-10-30 | 北京芯领航通科技有限公司 | Turbo decoding storage method and device based on RAM bus and decoder |
| CN111865336B (en) * | 2020-04-24 | 2021-11-02 | 北京芯领航通科技有限公司 | Turbo decoding storage method and device based on RAM bus and decoder |
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