CN112332869A - Improved TPC iteration method and apparatus - Google Patents
Improved TPC iteration method and apparatus Download PDFInfo
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- CN112332869A CN112332869A CN202011138586.XA CN202011138586A CN112332869A CN 112332869 A CN112332869 A CN 112332869A CN 202011138586 A CN202011138586 A CN 202011138586A CN 112332869 A CN112332869 A CN 112332869A
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
- H03M13/29—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes combining two or more codes or code structures, e.g. product codes, generalised product codes, concatenated codes, inner and outer codes
- H03M13/2957—Turbo codes and decoding
- H03M13/2975—Judging correct decoding, e.g. iteration stopping criteria
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
- H03M13/27—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes using interleaving techniques
- H03M13/2703—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes using interleaving techniques the interleaver involving at least two directions
- H03M13/271—Row-column interleaver with permutations, e.g. block interleaving with inter-row, inter-column, intra-row or intra-column permutations
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
- H03M13/27—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes using interleaving techniques
- H03M13/2771—Internal interleaver for turbo codes
Abstract
The invention discloses an improved TPC iteration method and a device, which at least comprise the following steps: step S1: acquiring coded data and storing the coded data in a row buffer and a column buffer respectively according to the row and column distribution of the information code elements; step S2: acquiring data from a row buffer or a column buffer line by line or column, and executing a TPC decoding algorithm to obtain decoding result information; step S3: updating the line buffer, the row buffer and the line/row decoding indicator according to the line/row recording coordinates by the decoding result information; step S4: extracting the position information of the error row/column according to the row/column decoding indication array, and performing deep iterative optimization on the error code element matrix; step S5: judging whether the coded data of all rows and columns are decoded successfully, if so, outputting decoding result information; otherwise, steps S3 and S4 are repeated until the coded data of all ranks are decoded successfully or the decoding result information cannot be updated further.
Description
Technical Field
The present invention relates to the field of TPC decoding technology, and in particular, to an improved TPC iteration method and apparatus.
Background
Turbo Product Code (TPC), a highly efficient forward error correction code, has excellent error correction capability and considerable application prospect, and is of great interest in the field of communications. The decoding algorithm is divided into hard decision decoding (HIHO) and soft decision decoding (SISO). The HIHO has low complexity, does not need complex operation, has a simple structure, but cannot meet the control system with high errors. The HIHO has some uncorrectable error patterns, the error rate is higher, sometimes the random error number does not exceed the error correction capability of the hard decision iterative decoding, but the situation that the error cannot be corrected exists, so the error correction capability is limited; SISO decoding iterative algorithm is quite complex, decoding time is long, resource occupancy rate is high, and realization difficulty is large.
At present, the decoding is widely applied to SISO decoders based on a Chase decoding algorithm, the Chase algorithm is used as a basic decoding algorithm of a subcode to generate external information required in an iteration process, and the algorithm complexity is reduced. Many later scholars improve the algorithm, for example, a parallel iterative decoding structure is adopted, so that the time delay is reduced to half, and the performance is lost; for example, the gradient algorithm greatly reduces the decoding complexity, but the decoding performance is not ideal; and a TPC self-adaptive decoding algorithm is used for screening the confidence coefficient of the extra-soft information according to the signal-to-noise ratio of a channel, and adjusting decoding according to the result, but the decoding has great limitation because the signal-to-noise ratio parameter cannot be obtained.
The decoding method of the TPC usually adopts a serial iterative decoding mode, can obtain better error rate performance, and is carried out in a row-column alternating mode in the decoding process. Therefore, the iterative decoding algorithm is also a commonly used method at present to improve the error correction capability by re-correcting the previous error correction result. However, in the prior art, multiple decoding rounds are performed on the basis of all symbol matrices, which results in a complex and long-delay decoding iteration process.
Therefore, in the decoding algorithm, how to reduce the resource occupancy rate in the decoding process, how to reduce the decoding complexity, how to obtain smaller decoding delay, and the like become the future research direction, and the decoding algorithm needs to be further optimized.
Therefore, it is necessary to provide a technical solution to solve the technical problems of the prior art.
Disclosure of Invention
In view of the above, it is necessary to provide an improved TPC iteration method and apparatus, which improve the iteration process without increasing the error correction code weight, and update the decoding result to the row/column buffer in time by recording the coordinate information according to the row/column, and extract the position information of the error row/column from the row/column error buffer, so as to perform deep iterative optimization on the error symbol matrix, thereby saving the decoding time and greatly improving the decoding efficiency.
In order to solve the technical problems in the prior art, the technical scheme of the invention is as follows:
an improved TPC iteration method comprising at least the steps of:
step S1: acquiring coded data and storing the coded data in a row buffer and a column buffer respectively according to the row and column distribution of the information code elements;
step S2: acquiring data from a row buffer or a column buffer line by line or column, and executing a TPC decoding algorithm to obtain decoding result information;
step S3: updating the line buffer, the row buffer and a line/row decoding indicator according to the decoding result information according to the line/row recording coordinates, wherein the line/row decoding indicator is used for indicating whether the decoding of the coded data of the corresponding line/row is successful or not;
step S4: extracting the position information of the error row/column according to the row/column decoding indication array, and performing deep iterative optimization on the error code element matrix, namely, performing a TPC decoding algorithm on the encoded data of the error row/column to update decoding result information;
step S5: judging whether the coded data of all rows and columns are decoded successfully, if so, outputting decoding result information; otherwise, steps S3 and S4 are repeated until the coded data of all ranks are decoded successfully or the decoding result information cannot be updated further.
As a further improvement, the row buffer and the column buffer are transposed.
As a further improvement, the row buffer or the column buffer is selected by a selector.
As a further improvement scheme, when the bit widths of rows and columns of the coded data are inconsistent, the bit widths of the rows or columns with small bit widths are consistent by complementing 0 in the rows and columns.
As a further improvement, in step S4, a decoding iteration is performed based on the row error bit buffer and the column error bit buffer obtained according to the row/column decoding indicator.
The invention also discloses an improved TPC iteration device, which at least comprises an acquisition unit, a decoding execution unit, a judgment unit and an output unit, wherein,
the acquiring unit is used for acquiring coded data;
the decoding execution unit is used for executing decoding operation on the acquired coded data;
the judging unit is used for judging whether the current decoding reaches an end condition;
the output unit is used for outputting decoding result information when decoding is finished;
the coding execution unit at least comprises:
the line buffer is used for storing data to be decoded according to lines;
the column buffer is used for storing data to be decoded according to columns;
a selector for selecting the row buffer or the column buffer;
a row/column decoder for performing a row-by-row or column-by-column TPC decoding algorithm on the selected row buffer or column buffer;
a decoding result buffer for storing decoding result information and updating the line buffer and the row buffer;
and the row/column decoding indicator is used for indicating whether the coded data of the corresponding row/column is decoded successfully or not and generating an error code element matrix as the basis of the next decoding iteration.
As a further improvement, the row buffer and the column buffer are transposed.
As a further improvement scheme, the row/column decoding indicator is two one-dimensional arrays, so that a row error bit buffer and a column error bit buffer are generated.
As a further improvement, the row/column decoder is used for multiplexing row and column decoding, and the same decoding algorithm is adopted to perform the row decoding and the column decoding.
As a further improvement scheme, when the bit widths of rows and columns of the coded data are inconsistent, the bit widths of the rows or columns with small bit widths are consistent by complementing 0 in the rows and columns.
Compared with the prior art, the technical scheme of the invention has the following technical effects:
1. because the indication array for successfully decoding the rows and the columns is set in the decoding process, the decoding result can be timely updated to the row/column buffer according to the row/column recording coordinate information, meanwhile, the position information of the error row/column is extracted from the row/column error bit buffer, and only the deep iterative optimization is carried out on the error code element matrix, thereby greatly saving the decoding time and hardware resources. In the multi-round decoding process, iterative decoding is only carried out aiming at error rows and columns, so that the efficient iterative decoding method for selective error correction is realized, and the effects of high decoding speed, stable performance and small resource occupation can be achieved.
2. The line/row buffers are mutually transposed, and the data of the two srams is updated in one step, so that the process of interleaving and deinterleaving of lines and rows is saved, and the decoding speed is improved.
3. The selector selects the row decoding or the column decoding, so that the row/column decoder can be multiplexed, and the hardware resources are further simplified.
Drawings
Fig. 1 is a block flow diagram of an improved TPC iteration method of the present invention.
Fig. 2 is a flow chart of a preferred embodiment of the improved TPC iteration method of the present invention.
Fig. 3 is a block diagram of the improved TPC iteration apparatus of the present invention.
FIG. 4 is a block diagram of a decoding execution unit according to the present invention.
FIG. 5 is a schematic diagram of the decoding process according to the preferred embodiment of the present invention.
The following specific embodiments will further illustrate the invention in conjunction with the above-described figures.
Detailed Description
The technical solution provided by the present invention will be further explained with reference to the accompanying drawings.
Referring to fig. 1, there is shown a flow chart of an improved TPC iteration method of the present invention, which at least includes the following steps:
step S1: acquiring coded data and storing the coded data in a row buffer and a column buffer respectively according to the row and column distribution of the information code elements;
step S2: acquiring data from a row buffer or a column buffer line by line or column, and executing a TPC decoding algorithm to obtain decoding result information;
step S3: updating the line buffer, the row buffer and a line/row decoding indicator according to the decoding result information according to the line/row recording coordinates, wherein the line/row decoding indicator is used for indicating whether the decoding of the coded data of the corresponding line/row is successful or not;
step S4: extracting the position information of the error row/column according to the row/column decoding indication array, and performing deep iterative optimization on the error code element matrix, namely, performing a TPC decoding algorithm on the encoded data of the error row/column to update decoding result information;
step S5: judging whether the coded data of all rows and columns are decoded successfully, if so, outputting decoding result information; otherwise, steps S3 and S4 are repeated until the coded data of all ranks are decoded successfully or the decoding result information cannot be updated further.
In the technical scheme, as the row/column decoding indicator is arranged in the decoding process, the decoding result can be timely updated to the row/column buffer according to the row/column recording coordinate information, meanwhile, the position information of the error row/column is extracted from the row/column error bit buffer, and only the deep iterative optimization is carried out on the error code element matrix, so that the decoding time and the hardware resource are greatly saved. In the multi-round decoding process, iterative decoding is only carried out aiming at error rows and columns, so that the efficient iterative decoding method for selective error correction is realized, and the effects of high decoding speed, stable performance and small resource occupation can be achieved.
As a further improvement scheme, the invention provides a row and column mark of decoding failure and a corresponding data extraction method. That is, the decoding iteration is performed based on the row-error bit buffer and the column-error bit buffer obtained from the row/column decoding indicator. The row/row error bit buffer is used for storing row/row decoding results, the row/row record of successful decoding is 0, the row/row record of failure decoding results is 1, and a one-dimensional array is formed; the deep iterative decoding only needs to decode according to the row/column of the array 1.
In the above technical solution, the row/column buffer is used for storing encoded information symbols, and since different signal transmission bit widths may have differences and may be inconsistent with a block code bit width of the decoder, the encoded information is transmitted to the row/column buffer first. The column buffer and the row buffer are transposed to each other, and are used for performing row-column decoding, and when data is stored, the data of two srams is updated in one step, so that row-column interleaving and deinterleaving time is saved.
In the above technical solution, the line buffer or the column buffer is selected by the selector. The selector is used for selecting the round to carry out row decoding or column decoding. When the line decoding is selected, outputting data from the line buffer to the decoder; when the column decoding is selected, data is output from the column buffer into the decoder. Due to the arrangement of the selector, the same decoder can be multiplexed by the row decoding and the column decoding, and hardware resources are further saved.
As a further improvement scheme, when the bit widths of rows and columns of the coded data are inconsistent, the bit widths of the rows or columns with small bit widths are consistent by complementing 0 in the rows and columns.
In the above technical solution, the row/column decoder obtains the information symbol from the selector according to the bit width of the block code, and can obtain the information symbol with the specified bit width from the row/column buffer in a pingpong manner, and the row/column decoder outputs the information symbol after the first decoding is performed. It is assumed that the row decoding error correction capability is not greater than X symbols and the column decoding capability is not greater than Y symbols. When the number of the row error symbols is less than or equal to X, the row error information symbol can be corrected; when the row error symbol is greater than X, the row error information symbol is uncorrectable. When the error code elements in the list are less than or equal to Y, the error information code elements in the list can be corrected; when more than Y error symbols are listed, the erroneous information symbols of the column are uncorrectable. For the correctable rows/columns, marking coordinate information to a row/column error bit buffer, correcting corresponding information bits and outputting to a decoding result buffer; for the uncorrectable row, the coordinate information is marked to the row/column error bit buffer, and the original code is output to the decoding result buffer.
Referring to fig. 2, there is shown a block flow diagram of a preferred embodiment of the improved TPC iteration method of the present invention, which specifically performs the following steps:
and 1, inputting the coded data to be decoded, and waiting for decoding.
2, inputting the data to be decoded into the line buffer, and inputting the data into the column buffer after line interleaving.
And 3, the selector selects row/column decoding.
4, if selecting line decoding, taking data from line buffer, inputting line decoding result into decoding result buffer. The record of the decoding success line is 0, and the record of the decoding failure line is 1, forming a one-dimensional array input line error bit buffer.
And 5, if the row decoding is selected, taking data from the row buffer, and inputting the row decoding result into the decoding result buffer. The successfully decoded row is recorded as 0, and the failed decoded row is recorded as 1, forming a one-dimensional array input row error bit buffer.
And 6, updating the decoding result to the row/column buffer in time by the decoding result buffer.
And 7, judging the row/column error bit buffer value, and if 1 exists, only carrying out the next iteration decoding on the row/column of 1.
8, the row/column error bit register values are all 0 to represent that all rows and columns are successfully decoded, and then the decoding result is output.
By adopting the technical scheme of the invention, the marking position is an unknown attribute position, and the line coordinate information of successful decoding is marked through one-time line decoding; then row-column decoding is carried out, column coordinate information which is decoded successfully is marked, and the column coordinate information is updated to a row/column buffer; the next round of row/column decoding only needs to decode the row/column with the row/column error bit array record of 1. The deep iterative decoding process only carries out iterative optimization on the wrong row/column, thereby greatly saving decoding time and hardware resources.
Assuming that the input encoding matrix is a 200x300 matrix, after the first round of decoding, 20 rows and 30 columns of symbols fail to correct errors, and after the second round of decoding, 5 rows and 6 columns of symbols fail to correct errors. In the prior art, all 200x300 matrixes are subjected to second iteration decoding and third iteration decoding, but the invention only needs to use 20x300 matrixes to perform second round row decoding and use 30x200 matrixes to perform second round column decoding; only the 5x300 matrix is needed to perform the third row decoding, and the 6x200 matrix is used to perform the third column decoding, so that the time and resource cost of multiple times are saved, and the complexity of the iterative process is reduced.
Referring to fig. 3, a schematic block diagram of an improved TPC iteration apparatus according to the present invention is shown, which at least includes an obtaining unit, a decoding performing unit, a determining unit and an output unit, wherein,
the acquiring unit is used for acquiring coded data;
the decoding execution unit is used for executing decoding operation on the acquired coded data;
the judging unit is used for judging whether the current decoding reaches an end condition;
the output unit is used for outputting the decoding result information when the decoding is finished.
Referring to fig. 4, a circuit structure diagram of a decoding execution unit of the present invention is shown, wherein the decoding execution unit at least comprises:
the line buffer is used for storing data to be decoded according to lines;
the column buffer is used for storing data to be decoded according to columns;
a selector for selecting the row buffer or the column buffer;
a row/column decoder for performing a row-by-row or column-by-column TPC decoding algorithm on the selected row buffer or column buffer; since the selector is used to select the row buffer or the column buffer, the row/column decoder can be multiplexed as a row and column decoder, and the same decoding algorithm can be used to perform row decoding and column decoding.
A decoding result buffer for storing decoding result information and updating the line buffer and the row buffer;
and the row/column decoding indicator is used for indicating whether the coded data of the corresponding row/column is decoded successfully or not and generating an error code element matrix as the basis of the next decoding iteration.
In the technical scheme, as the row/column decoding indicator is arranged in the decoding process, the decoding result can be timely updated to the row/column buffer according to the row/column recording coordinate information, meanwhile, the position information of the error row/column is extracted from the row/column error bit buffer, and only the deep iterative optimization is carried out on the error code element matrix, so that the decoding time and the hardware resource are greatly saved. In multiple rounds of decoding iteration, iterative decoding is carried out only aiming at error rows and columns, so that the efficient iterative decoding method for selective error correction is realized, and the effects of high decoding speed, stable performance and small resource occupation can be achieved. Meanwhile, due to the arrangement of the selector, the same decoder can be multiplexed by the row decoding and the column decoding, and hardware resources are further saved.
As a further improvement, the line buffer and the column buffer are transposed. The method is used for performing row-column decoding, and when the data is stored, the data of the two srams is updated in one step, so that row-column interleaving and deinterleaving time is saved.
As a further improvement scheme, the row/column decoding indicator is two one-dimensional arrays, so that a row error bit buffer and a column error bit buffer are generated. In the next round of decoding iteration, an error code element matrix is obtained on the basis of the row error bit buffer and the column error bit buffer, deep iteration optimization is carried out on the error code element matrix, correct code elements do not participate in the next round of iteration process, the number of the error code elements is reduced, decoding time is saved, and decoding efficiency is greatly improved.
The technical solution of the present invention is described in detail below by a specific embodiment, and referring to fig. 5, a schematic diagram of an iterative decoding process implemented by using the technical solution of the present invention is shown, and the specific implementation process is as follows:
1. assuming that data to be decoded is a matrix with 12 rows and 10 columns, after the first round of row decoding, marking row coordinate information, marking a row which is successfully decoded as 0, marking a row which is failed in decoding as 1, successfully decoding to correct bits, and inputting the row which is failed in decoding into a row buffer according to an original code.
2. After the line decoding, the 0 th, 2 nd, 5 th, 7 th and 9 th lines are decoded successfully, the decoding of the other lines is failed, and the coordinate information recorded by the decoding result is updated to the line-row buffer.
3. And (3) acquiring data from the row-column interleaver, performing first round of column decoding, marking column coordinate information, marking a column mark 0 for successful decoding, marking a column mark 1 for failed decoding, modifying correct bits for successful decoding, and updating a row-column buffer according to the original code and the row-column coordinate information when the decoding fails.
4. After the column decoding, the 0 th, 2 nd, 7 th and 8 th columns are successfully decoded.
5. Iterative line decoding is performed according to marked decoding failure lines 1, 3, 4, 6, 8, a, b.
6. And only the decoding failure line is decoded line by line.
7. After the current line decoding, the 3 rd, 6 th, 8 th and b th lines are successfully decoded, and the result is updated to the line-row buffer according to the coordinate information.
8. Iterative column decoding is performed according to the marked failed decoding rows 1, 4, 5, 6, 9.
9. Only the decoding failure column is decoded column by column.
10. After the current round of row decoding, all the rows are successfully decoded, the result is updated to the row-column buffer, and the decoding is finished. If there are still error code elements after the current round of decoding, repeating the steps e to i until all code elements are successfully decoded.
In the decoding iteration process, the marked position is an unknown attribute position, and the line coordinate information of successful decoding is marked through one-time line decoding; then row-column decoding is carried out, column coordinate information which is decoded successfully is marked, and the column coordinate information is updated to a row/column buffer; the next round of row/column decoding only needs to decode the row/column with the row/column error bit array record of 1. The deep iterative decoding process only carries out iterative optimization on the wrong row/column, thereby greatly saving decoding time and hardware resources.
The above description of the embodiments is only intended to facilitate the understanding of the method of the invention and its core idea. It should be noted that, for those skilled in the art, it is possible to make various improvements and modifications to the present invention without departing from the principle of the present invention, and those improvements and modifications also fall within the scope of the claims of the present invention.
The previous description of the disclosed embodiments is provided to enable any person skilled in the art to make or use the present invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other embodiments without departing from the spirit or scope of the invention. Thus, the present invention is not intended to be limited to the embodiments shown herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.
Claims (10)
1. An improved iterative TPC method, comprising at least the steps of:
step S1: acquiring coded data and storing the coded data in a row buffer and a column buffer respectively according to the row and column distribution of the information code elements;
step S2: acquiring data from a row buffer or a column buffer line by line or column, and executing a TPC decoding algorithm to obtain decoding result information;
step S3: updating the line buffer, the row buffer and a line/row decoding indicator according to the decoding result information according to the line/row recording coordinates, wherein the line/row decoding indicator is used for indicating whether the decoding of the coded data of the corresponding line/row is successful or not;
step S4: extracting the position information of the error row/column according to the row/column decoding indication array, and performing deep iterative optimization on the error code element matrix, namely, performing a TPC decoding algorithm on the encoded data of the error row/column to update decoding result information;
step S5: judging whether the coded data of all rows and columns are decoded successfully, if so, outputting decoding result information; otherwise, steps S3 and S4 are repeated until the coded data of all ranks are decoded successfully or the decoding result information cannot be updated further.
2. The iterative method of modified TPC of claim 1, wherein the row and column buffers are transposes of each other.
3. An improved TPC iteration method according to claim 1 or 2, wherein the row buffer or the column buffer is selected by a selector.
4. An improved iterative TPC method according to claim 1 or claim 2, wherein when the row and column bit widths of the encoded data are not identical, the row or column with less bit width is made identical by complementing the row and column by 0.
5. The iterative method for improving TPC as claimed in claim 1 or 2 wherein in step S4, the decoding iteration is performed based on the row error bit buffer and the column error bit buffer obtained from the row/column decoding indicator.
6. An improved TPC iteration device is characterized by at least comprising an acquisition unit, a decoding execution unit, a judgment unit and an output unit, wherein,
the acquiring unit is used for acquiring coded data;
the decoding execution unit is used for executing decoding operation on the acquired coded data;
the judging unit is used for judging whether the current decoding reaches an end condition;
the output unit is used for outputting decoding result information when decoding is finished;
the coding execution unit at least comprises:
the line buffer is used for storing data to be decoded according to lines;
the column buffer is used for storing data to be decoded according to columns;
a selector for selecting the row buffer or the column buffer;
a row/column decoder for performing a row-by-row or column-by-column TPC decoding algorithm on the selected row buffer or column buffer;
a decoding result buffer for storing decoding result information and updating the line buffer and the row buffer;
and the row/column decoding indicator is used for indicating whether the coded data of the corresponding row/column is decoded successfully or not and generating an error code element matrix as the basis of the next decoding iteration.
7. The improved TPC iteration device of claim 6, wherein the row and column buffers are transposes of each other.
8. The improved TPC iteration device of claim 6, wherein the column/row decoding indicator is two one-dimensional arrays, thereby generating a column error bit buffer and a row error bit buffer.
9. The improved TPC iteration device of claim 6, wherein the row/column decoder is configured for row and column decoding multiplexing, and the same decoding algorithm is used for both row decoding and column decoding.
10. The improved TPC iteration means of claim 9, wherein when the row and column bit widths of the encoded data are not identical, the row or column with less bit width is made identical by complementing 0 in front of the row and column.
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN115225203A (en) * | 2022-06-08 | 2022-10-21 | 芯翼信息科技(上海)有限公司 | Data de-interleaving method and device, electronic equipment and storage medium |
| US11750221B1 (en) | 2022-03-28 | 2023-09-05 | Samsung Electronics Co., Ltd. | Encoding and decoding of data using generalized LDPC codes |
Citations (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5719884A (en) * | 1995-07-27 | 1998-02-17 | Hewlett-Packard Company | Error correction method and apparatus based on two-dimensional code array with reduced redundancy |
| US20020049947A1 (en) * | 2000-06-02 | 2002-04-25 | Satish Sridharan | Product code based forward error correction system |
| US7100101B1 (en) * | 2002-11-08 | 2006-08-29 | Xilinx, Inc. | Method and apparatus for concatenated and interleaved turbo product code encoding and decoding |
| US9231623B1 (en) * | 2013-09-11 | 2016-01-05 | SK Hynix Inc. | Chase decoding for turbo-product codes (TPC) using error intersections |
| CN105634508A (en) * | 2015-12-21 | 2016-06-01 | 西安空间无线电技术研究所 | Realization method of low complexity performance limit approximate Turbo decoder |
| US20170155407A1 (en) * | 2015-12-01 | 2017-06-01 | SK Hynix Inc. | Techniques for low complexity turbo product code decoding |
| US20170279467A1 (en) * | 2016-03-23 | 2017-09-28 | SK Hynix Inc. | Performance optimization in soft decoding of error correcting codes |
| US20190340068A1 (en) * | 2018-05-03 | 2019-11-07 | SK Hynix Memory Solutions America Inc. | Encoder and decoder for memory system and method thereof |
| US20200089598A1 (en) * | 2018-09-19 | 2020-03-19 | SK Hynix Inc. | Reconfigurable simulation system and method for testing firmware of storage |
| US20200097416A1 (en) * | 2018-09-21 | 2020-03-26 | SK Hynix Inc. | Data path protection parity determination for data patterns in storage devices |
| CN111277355A (en) * | 2018-12-04 | 2020-06-12 | 深圳市中兴微电子技术有限公司 | Method and device for correcting deadlock in TPC (transmit power control) decoding |
-
2020
- 2020-10-22 CN CN202011138586.XA patent/CN112332869A/en active Pending
Patent Citations (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5719884A (en) * | 1995-07-27 | 1998-02-17 | Hewlett-Packard Company | Error correction method and apparatus based on two-dimensional code array with reduced redundancy |
| US20020049947A1 (en) * | 2000-06-02 | 2002-04-25 | Satish Sridharan | Product code based forward error correction system |
| US7100101B1 (en) * | 2002-11-08 | 2006-08-29 | Xilinx, Inc. | Method and apparatus for concatenated and interleaved turbo product code encoding and decoding |
| US9231623B1 (en) * | 2013-09-11 | 2016-01-05 | SK Hynix Inc. | Chase decoding for turbo-product codes (TPC) using error intersections |
| US20170155407A1 (en) * | 2015-12-01 | 2017-06-01 | SK Hynix Inc. | Techniques for low complexity turbo product code decoding |
| CN105634508A (en) * | 2015-12-21 | 2016-06-01 | 西安空间无线电技术研究所 | Realization method of low complexity performance limit approximate Turbo decoder |
| US20170279467A1 (en) * | 2016-03-23 | 2017-09-28 | SK Hynix Inc. | Performance optimization in soft decoding of error correcting codes |
| US20190340068A1 (en) * | 2018-05-03 | 2019-11-07 | SK Hynix Memory Solutions America Inc. | Encoder and decoder for memory system and method thereof |
| US20200089598A1 (en) * | 2018-09-19 | 2020-03-19 | SK Hynix Inc. | Reconfigurable simulation system and method for testing firmware of storage |
| US20200097416A1 (en) * | 2018-09-21 | 2020-03-26 | SK Hynix Inc. | Data path protection parity determination for data patterns in storage devices |
| CN111277355A (en) * | 2018-12-04 | 2020-06-12 | 深圳市中兴微电子技术有限公司 | Method and device for correcting deadlock in TPC (transmit power control) decoding |
Non-Patent Citations (3)
| Title |
|---|
| BO FU AND PAUL AMPADU: "n Energy-Efficient Multiwire Error Control Scheme for Reliable On-Chip Interconnects Using Hamming Product Codes", HTTPS://DOI.ORG/10.1155/2008/109490 * |
| X. ZHOU AND R. LI: "A Parallel Turbo Product Codes Decoder Based on Graphics Processing Units", 019 IEEE 21ST INTERNATIONAL CONFERENCE ON HIGH PERFORMANCE COMPUTING AND COMMUNICATIONS; IEEE 17TH INTERNATIONAL CONFERENCE ON SMART CITY; IEEE 5TH INTERNATIONAL CONFERENCE ON DATA SCIENCE AND SYSTEMS (HPCC/SMARTCITY/DSS) * |
| 熊玉平: "一种交错并行高速TPC译码器的设计", 电讯技术, pages 830 - 833 * |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US11750221B1 (en) | 2022-03-28 | 2023-09-05 | Samsung Electronics Co., Ltd. | Encoding and decoding of data using generalized LDPC codes |
| EP4254192A1 (en) * | 2022-03-28 | 2023-10-04 | Samsung Electronics Co., Ltd. | Encoding and decoding of data using generalized ldpc codes |
| CN115225203A (en) * | 2022-06-08 | 2022-10-21 | 芯翼信息科技(上海)有限公司 | Data de-interleaving method and device, electronic equipment and storage medium |
| CN115225203B (en) * | 2022-06-08 | 2024-04-12 | 芯翼信息科技(上海)有限公司 | Data de-interleaving method and device, electronic equipment and storage medium |
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