CN110557220B - Physical layer channel coding and decoding method - Google Patents
Physical layer channel coding and decoding method Download PDFInfo
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L1/00—Arrangements for detecting or preventing errors in the information received
- H04L1/0001—Systems modifying transmission characteristics according to link quality, e.g. power backoff
- H04L1/0006—Systems modifying transmission characteristics according to link quality, e.g. power backoff by adapting the transmission format
- H04L1/0007—Systems modifying transmission characteristics according to link quality, e.g. power backoff by adapting the transmission format by modifying the frame length
- H04L1/0008—Systems modifying transmission characteristics according to link quality, e.g. power backoff by adapting the transmission format by modifying the frame length by supplementing frame payload, e.g. with padding bits
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- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L1/00—Arrangements for detecting or preventing errors in the information received
- H04L1/0001—Systems modifying transmission characteristics according to link quality, e.g. power backoff
- H04L1/0009—Systems modifying transmission characteristics according to link quality, e.g. power backoff by adapting the channel coding
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- H—ELECTRICITY
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- H04L1/0061—Error detection codes
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- H—ELECTRICITY
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- H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
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Abstract
The invention provides a physical layer channel coding and decoding method; the encoding method includes encoding a frame control FC segment and a Payload segment. Directly coding information bits to be transmitted with a certain fixed code rate; filling information bits to be transmitted, then coding a certain fixed code rate, and removing the previous filling bits from the information bits output by coding to realize a code rate lower than the fixed code rate; and thirdly, carrying out coding of a certain fixed code rate on information bits to be transmitted, and then punching the output check bits to realize a code rate higher than the fixed code rate.
Description
Technical Field
The invention belongs to the field of communication, and particularly relates to a channel coding and decoding method.
Background
Channel coding, interleaving, as a key technology of a physical layer, is widely used in various communication systems; in terms of channel coding, turbo codes and LDPC codes are widely used; in an actual physical layer system, according to different service requirements, some service requirements require a low receiving threshold, and some service requirements require a high data rate, so in a physical layer coding scheme, multiple code rates need to be designed for a selected code to support different applications, which also brings about an increase in complexity to a certain extent.
In some systems using Turbo codes as coding schemes, such as OFDM systems of Homeplug AV standards, turbo codes are used to implement 1/2 coding as a mother code, and then a mode of puncturing after coding is used to implement a higher code rate.
However, this system is limited in that a code rate below 1/2 cannot be achieved and will not be applicable in some systems requiring very low reception thresholds.
Disclosure of Invention
The present invention addresses the above-mentioned problems by providing a flexible physical layer channel coding method comprising one or more combinations of the following three methods:
directly coding information bits to be transmitted with a certain fixed code rate;
filling information bits to be transmitted, then coding a certain fixed code rate, and removing the previous filling bits from the information bits output by coding to realize a code rate lower than the fixed code rate;
thirdly, coding information bits to be transmitted with a certain fixed code rate, and punching output check bits to realize a code rate higher than the fixed code rate;
the channel coding method further adopts Turbo codes for coding.
The channel coding method further comprises channel coding of the frame control FC section and/or the Payload section. And adopting a first method and/or a second method for channel coding of the frame control FC section, and adopting a first method, a second method and a third method for channel coding of the Payload section.
The channel coding method adopts a mode of alternately inserting when filling information bits to be transmitted when adopting a method II; the pseudo random sequence PRBS is used when padding the information bits to be transmitted.
The channel coding method fills the information bits to be transmitted in the channel coding method of the frame control FC section, then carries out Turbo coding of 1/2 code rate, and removes the filling bits before the information bits output by coding to realize 1/3 code rate.
According to the channel coding method, the data Payload section realizes different code rate coding according to service requirements, 1/3 code rate is realized according to the first method, 1/2 code rate is realized according to the second method, and code rate higher than 1/2 is realized according to the third method.
In the channel coding method, the code rate of a mother code coder of a frame control FC section is 1/2, the code length of the mother code is 512 bits, the bit length of frame control information is 128 bits, the length of check bits is 256 bits, and the code length of the frame control coded is 384 bits.
According to the channel coding method, the data Payload section realizes different code rate coding according to service requirements: 1/3, 1/2, 2/3, 3/4 and 6/7.
The channel coding method is characterized in that bit interleaving is further carried out after coding, the data after Turbo coding keep the sequence before coding, information bits are in front, check bits are in behind, K represents the number of the information bits, N represents the actual code length after coding, N-K represents the number of the check bits, K information bits are divided into 4 sub-blocks, the size of each sub-block is K/4 bits, N-K check bits are divided into 4 sub-blocks, and the size of each sub-block is (N-K)/4 bits. Bit interleaving comprises four steps:
step one, interleaving information codes: writing the information code output by Turbo coding into a matrix storage space, and sequentially outputting a first block (K/4 bit) of information bits into a block 1, a second block (K/4 bit) into a block 2, a third block (K/4 bit) into a block 3, and a fourth block (K/4 bit) into a block 4 by an encoder, wherein the 1 st column represents a block 1, the 2 nd column represents a block 2, the 3 rd column represents a block 3, and the 4 th column represents a block 4. The 4 bits of each row are read out simultaneously when interleaving is performed. When data is read from the matrix, firstly, starting from row 0, then adding a reading step size StepSize to each reading head row address, so that the first round of row address reading sequence is (0, stepSize,2 x StepSize, …), when [ K/4]/StepSize rows are read, the tail of the matrix is read, then adding 1 to the next round of reading head row address, then adding a step size StepSize to each reading row address, reading [ K/4]/StepSize rows, then reaching the tail again, the second round of reading row address sequence is (1, 1+stepsize,1+2 x, …), then adding 1 to the third round of row address again, and then analogizing to complete the whole rows after the StepSize wheels.
Step two, check code interleaving: firstly, classifying the interleaving types according to code length and code rate, and dividing the interleaving types into an interleaving type 1 and an interleaving type 2. Performing a first block (N-K)/4 bits of parity bits output from Turbo coding into block 1, a second block (N-K)/4 bits into block 2, a third block (N-K)/4 bits into block 3, and a fourth block (N-K)/4 bits into block 4 can be regarded as a matrix storing parity bits into one (N-K)/4 rows and 4 columns, column 1 representing block 1, column 2 representing block 2, column 3 representing block 3, and column 4 representing block 4. Subsequently for different interleaving types, for interleaving type 1, the read of the parity bits is similar to the read of the information bits, except that the first read of the parity bits starts from the row defined by the parity offset parameter offset, the step size parameter is again StepSize, we define t= (N-K)/4, the order of the rows read in the first round is (offset+stepsize) mod T, (offset+2 x StepSize) mod T, …), then the first round is added with 1, the StepSize-1 round is repeated, finally the T/StepSize row data is read in each round through the StepSize round, and the T row data is read in total. For interleave type 2, the row pointer is not initialized after each round of reading, but instead the reading (offset+stepsize) mod T, (offset+2 x StepSize) mod T, …) continues from the beginning until the T rows are read.
In this step, the specific interleaving parameters of the frame control FC section are as follows:
the specific interleaving parameters for the Payload section are as follows:
step three, interleaving between the information code and the check code: then for a 1/3 code rate, the first 4 bits are output as an information code, followed by 2 4-bit check codes, and so on. For a 1/2 code rate, the first 4 bits of the output are information codes, then the 4 bits are check codes, and so on. For a 2/3 code rate, the first 2 4 bits are output as an information code, followed by a 4-bit check code, and so on. For a 3/4 code rate, the first 3 4-bit information codes are output, followed by a 4-bit check code, and so on. For a 6/7 code rate, the first 6 4 bits are output as information bits, then the 4 bits are check bits, and so on.
Step four, nibble shift: the nibble shift is shifted in units of 4 bits, and the order is adjusted every two nibbles, regardless of information bits or check bits, as shown in the following table. Where b0 represents block 1 with bits from information or parity bits, and so on, b1 represents t from block 2, b2 represents from block 3, and b3 represents from block 4. When the bits are serially output, the leftmost bit of the 4 bits is output first, from left to right.
| Outputting the nibble sequence | Shift pattern | ||
| 1 or 2 | |
||
| 3 or 4 | |
||
| 5 or 6 | |
||
| 7 or 8 | |
||
| 9 or 10 | b0b1b2b3 |
According to another aspect of the present invention, the present invention also provides a physical layer channel decoding method, including:
the method is suitable for the signal to be received generated by the first encoding method, adopts the first decoding method, and directly sends the log-likelihood ratio sequence of the bit stream to a decoder for decoding after the log-likelihood ratio sequence of the bit stream to be decoded is obtained by signal processing steps such as synchronization, equalization, constellation mapping and the like at a receiving end; and deleting the check bit after decoding to recover the valid information bit.
After a receiving end obtains a log likelihood ratio sequence of a bit stream to be decoded through signal processing steps such as synchronization, equalization, constellation mapping and the like, filling the log likelihood ratio of a known filling sequence in a corresponding position according to the code generation on the log likelihood ratio sequence of the information bit stream, and then sending the filled log likelihood ratio sequence to a decoder for decoding; and deleting the check bit and the filling information bit after decoding, and recovering the valid information bit.
After a receiving end obtains a log likelihood ratio sequence of a bit stream to be decoded through signal processing steps such as synchronization, equalization, constellation mapping and the like, filling log likelihood ratio information of corresponding bits in a punching position of the bit stream of a check bit according to code generation, and then sending the filled log likelihood ratio sequence to a decoder for decoding; and deleting the check bit after decoding to recover the valid information bit.
Further, based on the signal generated at the time of generation according to the following encoding method two: filling information bits to be transmitted, performing Turbo coding of 1/2 code rate, and removing the previous filling bits from the coded output information bits to realize 1/3 code rate. The decoding method comprises the following steps: after the log-likelihood ratio sequence of the bit stream to be decoded is obtained at the receiving end through signal processing steps such as synchronization, equalization, constellation mapping and the like, filling the log-likelihood ratio of a known filling sequence at a corresponding position according to the code generation on the log-likelihood ratio sequence of the bit stream of the information, and then sending the filled log-likelihood ratio sequence to a mother code decoder for Turbo decoding with 1/2 code rate; and deleting the check bit and the filling information bit after decoding, and recovering the valid information bit.
Compared with the prior art, the technical scheme provided by the invention has the following beneficial effects:
when the code requirement lower than the code rate of the mother code is met, filling the information bits to be transmitted, then coding the code rate of the mother code, and removing the filling bits before the information bits output by coding to realize the code rate lower than the code rate of the mother code; when the coding requirement higher than the code rate of the mother code is met, the information bits to be transmitted are coded at the code rate of the mother code, and then the check bits output by coding are punched to realize the code rate higher than the code rate of the mother code; furthermore, when filling is carried out, the coding performance can be effectively improved by adopting a pseudo random sequence PRBS and an alternate insertion mode. The coding method realizes the coding requirements of various code rates of the communication system with very low complexity, and can realize very excellent performance at each code rate.
Drawings
The accompanying drawings, which are included to provide a further understanding of the invention and are incorporated in and constitute a part of this application, illustrate and together with the description serve to explain the invention. In the drawings:
FIG. 1 is a schematic diagram of the encoding method of the present invention;
FIG. 2 is a schematic diagram of the encoding of a frame control FC segment of the present invention;
FIG. 3 is a schematic diagram of a binary Turbo mother code encoder of the present invention;
FIG. 4 is a schematic diagram of a filling mode of a second encoding method of the present invention;
FIG. 5 is a schematic representation of the encoding of the Payload section of the present invention;
FIG. 6 is a decoding schematic of the present invention;
Detailed Description
The present invention will be described in further detail with reference to the accompanying drawings, in order to make the objects, technical solutions and advantages of the present invention more apparent. The exemplary embodiments of the present invention and the descriptions thereof are used herein to explain the present invention, but are not intended to limit the invention. The terms "unit" or "module" used below may be hardware, software or a combination of both for realizing a predetermined function, and when an embodiment is described in one of the implementations, the other two ways may also realize the intention of the inventive concept, and thus also belong to the contributing scope of the invention.
Fig. 1 is a schematic diagram of the encoding method of the present invention. As shown in fig. 1, in order to realize different code rates to support the requirements of different receiving thresholds and data rates, a physical layer communication system adopts one, two or three of three coding methods to realize different code rates; the core encoder adopts a fixed code rate, and the required different code rates are realized through filling information bits to be input into the encoder or punching check bits of the encoder.
Directly coding information bits to be transmitted with a certain fixed code rate; filling information bits to be transmitted, then coding a certain fixed code rate, and removing the previous filling bits from the information bits output by coding to realize a code rate lower than the fixed code rate; thirdly, coding information bits to be transmitted with a certain fixed code rate, and punching output check bits to realize a code rate higher than the fixed code rate;
in this embodiment, the channel coding uses Turbo codes. And a first method and/or a second method are adopted for channel coding of the frame control FC section. Methods one, two and three are employed for channel coding of the Payload segment.
First, the present embodiment describes channel coding of the frame control FC section. Coding at rate 1/3 is achieved using the method mentioned above, as shown in fig. 2. The mother code encoder adopts a binary Turbo code encoding structure with a fixed code rate of 1/2, as shown in fig. 3, a pair of information bits [ u1, u2] is input, and systematic bits [ u1, u2] and check bits [ p, q ] are output. (p: component encoder 1 check output, q: component encoder 2 check output). The mother code encoder includes an inner interleaver, which is an S-random interleaver or random interleaver known in the Turbo coding art, and which is not described in detail herein, and bit interleaving, which will be described later herein, is two completely different interleaving methods.
The PRBS stream pad_b with equal length as the information bit is filled in the information bit stream u, then the PRBS stream pad_b is sent to a double-bit encoder for encoding, and then the information bit check bit (p: the check output of the component encoder 1 and q: the check output of the component encoder 2) is combined after the filling part is removed for outputting. For a two-bit Turbo encoder: each input pair of information bits [ u1, u2], the output systematic bits [ u1, u2] and the parity bits [ p, q ]. The FC encoding flow is shown in fig. 3. A typical set of frame control FC encoder parameters is given in table 1. The mother code length refers to the code length of a dual bit encoder. The actual code length refers to the output code length after all the encoding steps.
Table 1: FC encoder parameters
Of the set of parameters, the input information bits are 128 bits, the first filled information bits become 256 bits,
filling mode this embodiment adopts an alternate insertion mode, where the information bits u and the filling bits pad_b are alternately inserted. For 1/3 coding, the insertion scheme is: [ u (1), pad_b (1), u (2), pad_b (2) & u (128), pad_b (128) ], as shown in fig. 4, wherein pad_b (1), pad_b (2) represents padding bits, generated by the known pseudo random sequence PRBS. Fig. 4 also shows the padding approach to achieve lower code rates such as 1/4 and 1/5 coding. After filling 256 bits, turbo coding with 1/2 code rate is carried out, the output information bit is 256 bits, the output check bit is 256 bits, then all the filling bits in the 256 bits of the information bit are deleted, the original 128 bits of information bit are restored, and 256 bits of check bit are added, so that 384 bits of coding output is obtained, and the coding with 1/3 code rate is realized.
The following describes the encoding generation method of the Payload section. The Payload section and the FC section use the same 1/2 rate mother code encoder that supports the coding rate: 1/3, 1/2, 2/3, 3/4, 6/7, the above methods one and two and three are adopted according to code rate selection, as shown in fig. 5. The implementation method of the 1/3 code rate is consistent with the FC; the realization method of the 1/2 code rate is that the mother code encoder directly outputs the code rate; the realization method of the 2/3, 3/4 and 6/7 code rates is that after the output of the mother code encoder, check bits (p, q) are punched, and the punching patterns for different code rates are different, as shown in fig. 5. The parent encoder parameters for the Payload section are shown in table 5. The puncturing matrices for different code rates are shown in tables 2-4 (0: puncturing position 1: reserved position).
Table 2:2/3 rate puncturing matrix
| p | 101010101010 |
| q | 101010101010 |
Table 3:3/4 rate puncturing matrix
| p | 100100100100 |
| q | 100100100100 |
Table 4:6/7 rate puncturing matrix
| p | 100000100000 |
| q | 100000100000 |
TABLE 5 payload mother code encoder parameters
After encoding is completed, interleaving is typically performed to break up errors that occur during transmission. The data after Turbo coding keeps the sequence before coding, the information bits are in front, the check bits are in back (p is in front, q is in back), wherein K represents the number of information bits, N represents the actual code length after coding, N-K represents the number of check bits, K information bits are divided into 4 sub-blocks, the size of each sub-block is K/4 bits, N-K check bits are divided into 4 sub-blocks, and the size of each sub-block is (N-K)/4 bits.
The following bit interleaving method is adopted in this embodiment, and includes four steps:
step one, interleaving information codes: writing the information code output by Turbo coding into a matrix storage space, and sequentially outputting a first block (K/4 bit) of information bits into a block 1, a second block (K/4 bit) into a block 2, a third block (K/4 bit) into a block 3, and a fourth block (K/4 bit) into a block 4 by an encoder, wherein the 1 st column represents a block 1, the 2 nd column represents a block 2, the 3 rd column represents a block 3, and the 4 th column represents a block 4. The 4 bits of each row are read out simultaneously when interleaving is performed. When data is read from the matrix, firstly, starting from row 0, then adding a reading step size StepSize to each reading head row address, so that the first round of row address reading sequence is (0, stepSize,2 x StepSize, …), when [ K/4]/StepSize rows are read, the tail of the matrix is read, then adding 1 to the next round of reading head row address, then adding a step size StepSize to each reading row address, reading [ K/4]/StepSize rows, then reaching the tail again, the second round of reading row address sequence is (1, 1+stepsize,1+2 x, …), then adding 1 to the third round of row address again, and then analogizing to complete the whole rows after the StepSize wheels.
Step two, check code interleaving: firstly, classifying the interleaving types according to code length and code rate, and dividing the interleaving types into an interleaving type 1 and an interleaving type 2. Performing a first block (N-K)/4 bits of parity bits output from Turbo coding into block 1, a second block (N-K)/4 bits into block 2, a third block (N-K)/4 bits into block 3, and a fourth block (N-K)/4 bits into block 4 can be regarded as a matrix storing parity bits into one (N-K)/4 rows and 4 columns, column 1 representing block 1, column 2 representing block 2, column 3 representing block 3, and column 4 representing block 4. Subsequently for different interleaving types, for interleaving type 1, the read of the parity bits is similar to the read of the information bits, except that the first read of the parity bits starts from the row defined by the parity offset parameter offset, the step size parameter is again StepSize, we define t= (N-K)/4, the order of the rows read in the first round is (offset+stepsize) mod T, (offset+2 x StepSize) mod T, …), then the first round is added with 1, the StepSize-1 round is repeated, finally the T/StepSize row data is read in each round through the StepSize round, and the T row data is read in total. For interleave type 2, the row pointer is not initialized after each round of reading, but instead the reading (offset+stepsize) mod T, (offset+2 x StepSize) mod T, …) continues from the beginning until the T rows are read. Specific interleaving parameters may be referred to in Table 6/7.
TABLE 6 control of specific interleaving parameters for FC segments
Table 7: specific interleaving parameters for data Payload segments
Step three, interleaving between the information code and the check code: then for a 1/3 code rate, the first 4 bits are output as an information code, followed by 2 4-bit check codes, and so on. For a 1/2 code rate, the first 4 bits of the output are information codes, then the 4 bits are check codes, and so on. For a 2/3 code rate, the first 2 4 bits are output as an information code, followed by a 4-bit check code, and so on. For a 3/4 code rate, the first 3 4-bit information codes are output, followed by a 4-bit check code, and so on. For a 6/7 code rate, the first 6 4 bits are output as information bits, then the 4 bits are check bits, and so on.
Step four, nibble shift: the nibble shift is shifted in units of 4 bits, and the order is adjusted every two nibbles, regardless of information bits or check bits, as shown in table 8. Where b0 represents block 1 with bits from information or parity bits, and so on, b1 represents t from block 2, b2 represents from block 3, and b3 represents from block 4. When the bits are serially output, the leftmost bit of the 4 bits is output first, from left to right.
TABLE 8 nibble shifting
| Outputting the nibble sequence | Shift pattern | ||
| 1 or 2 | |
||
| 3 or 4 | |
||
| 5 or 6 | |
||
| 7 or 8 | |
||
| 9 or 10 | b0b1b2b3 |
The invention also proposes a decoding method, as shown in fig. 6.
For a signal generated by encoding the encoding method I, after the log-likelihood ratio sequence of the bit stream to be decoded is obtained at a receiving end through signal processing steps such as synchronization, equalization, constellation mapping and the like, the log-likelihood ratio sequence of the bit stream is directly sent to a fixed code rate decoder for decoding; and deleting the check bit after decoding to recover the valid information bit.
For signals generated by encoding the second encoding method, after the log-likelihood ratio sequence of the bit stream to be decoded is obtained by signal processing steps such as synchronization, equalization, constellation mapping and the like at a receiving end, filling the log-likelihood ratio of a known filling sequence on the log-likelihood ratio sequence of the bit stream according to corresponding filling positions during encoding generation, and then sending the filled log-likelihood ratio sequence to a decoder for decoding; and deleting the check bit and the filling information bit after decoding, and recovering the valid information bit.
For signals generated by encoding method three, after the log-likelihood ratio sequence of the bit stream to be decoded is obtained by signal processing steps such as synchronization, equalization, constellation mapping and the like at a receiving end, filling log-likelihood ratio information of corresponding bits in corresponding punching positions in encoding generation on the log-likelihood ratio sequence of the bit stream of the check bit, and then sending the filled log-likelihood ratio sequence to a decoder for decoding; and deleting the check bit after decoding to recover the valid information bit.
For example, for the received signal after encoding method two by 1/3 code rate encoding, the soft values of information bits are filled llr (pad_b) and the soft values of check bits are sent to the decoder; the received signal after 1/2 code rate coding is carried out corresponding to the second coding method, and the information bit and the check bit soft value are directly sent into a decoder; and (3) for the received signals after the code rate coding of 2/3, 3/4, 6/7 and the like of the coding method III, filling zeros of check bit soft values at punching positions and sending the check bit soft values and the information bit soft values into a decoder. Wherein llr (pad_b) is generated from the originating pad_b: llr =c (pad_b-0.5), C is a fixed constant.
It will be evident to those skilled in the art that the invention is not limited to the details of the foregoing illustrative embodiments, and that the present invention may be embodied in other specific forms without departing from the spirit or essential characteristics thereof. The present embodiments are, therefore, to be considered in all respects as illustrative and not restrictive, the scope of the invention being indicated by the appended claims rather than by the foregoing description, and all changes which come within the meaning and range of equivalency of the claims are therefore intended to be embraced therein. Any reference sign in a claim should not be construed as limiting the claim concerned.
It should be noted and appreciated that various modifications and improvements of the invention described in detail above can be made without departing from the spirit and scope of the invention as claimed in the foregoing claims. Accordingly, the scope of the claimed subject matter is not limited by any particular exemplary teachings presented.
Claims (13)
1. A physical layer channel coding method, wherein a method two or a combination of a method two and other methods is adopted: directly coding information bits to be transmitted with a certain fixed code rate; filling information bits to be transmitted, then coding a certain fixed code rate, and removing the previous filling bits from the information bits output by coding to realize a code rate lower than the fixed code rate; thirdly, coding information bits to be transmitted with a certain fixed code rate, and punching output check bits to realize a code rate higher than the fixed code rate;
the method II is characterized in that a pseudo random sequence PRBS and an alternate insertion mode are adopted to effectively improve the coding performance.
2. The channel coding method of claim 1, wherein the coding is performed using a Turbo code.
3. The channel coding method of claim 1, comprising channel coding a frame control FC segment and/or a Payload segment.
4. A channel coding method according to claim 3, characterized in that the channel coding of the frame control FC section is performed using a combination of method one and method two.
5. A channel coding method according to claim 3, characterized in that the channel coding of the Payload section uses a combination of three of methods one, two and three.
6. The channel coding method of claim 4, wherein the channel coding method of the frame control FC section fills information bits to be transmitted, then performs Turbo coding of 1/2 code rate, and then removes the previous filling bits from the coded output information bits to realize 1/3 code rate.
7. The channel coding method of claim 5, wherein the data Payload section implements different rate coding according to service requirements, implements 1/3 rate according to method one, implements 1/2 rate according to method two, and implements higher than 1/2 rate according to method three.
8. The channel coding method of claim 6, wherein a mother code encoder code rate of the frame control FC section is 1/2, a mother code length is 512 bits, a frame control information bit length is 128 bits, a check bit length is 256 bits, and a frame control coded code length is 384 bits.
9. The channel coding method of claim 7, wherein the data Payload section implements different rate coding according to traffic requirements: 1/3, 1/2, 2/3, 3/4 and 6/7.
10. The channel coding method of claim 3, wherein bit interleaving is further performed after coding, the data after Turbo coding is kept in a pre-coding order, information bits are preceded, and check bits are followed, wherein K represents the number of information bits, N represents an actual code length after coding, N-K represents the number of check bits, K information bits are divided into 4 sub-blocks, each sub-block has a size of K/4 bits, N-K check bits are divided into 4 sub-blocks, and each sub-block has a size of (N-K)/4 bits; bit interleaving takes four steps:
step one, interleaving information codes: writing information codes output by Turbo codes into a matrix storage space, sequentially outputting a first block (K/4 bits) of information bits into a block 1, a second block (K/4 bits) into a block 2, a third block (K/4 bits) into a block 3, and a fourth block (K/4 bits) into a block 4 by an encoder, wherein the 1 st column represents a block 1, the 2 nd column represents a block 2, the 3 rd column represents a block 3, and the 4 th column represents a block 4, which is equivalent to storing the information bits into a matrix of K/4 rows and 4 columns; 4 bits of each row are read out simultaneously when interleaving is performed; when reading data from the matrix, first starting from row 0, then increasing the first row address by one read step StepSize each time, so that the first round of row address read-out is in the order (0, stepSize,
StepSize, …), after reading [ K/4]/StepSize row, reading the tail of the matrix, adding 1 to the head address of the next row, adding a step size StepSize to the row address, reading [ K/4]/StepSize row, reaching the tail again, reading row address sequence of the second row (1, 1+stepsize,1+2 x StepSize, …), adding 1 to the address of the third row, and so on, and finishing the reading of all rows after passing through the StepSize wheel;
step two, check code interleaving: firstly, classifying the interleaving types according to code length and code rate, and dividing the interleaving types into an interleaving type 1 and an interleaving type 2; performing a first block (N-K)/4 bits of parity bits output from the Turbo code into block 1, a second block (N-K)/4 bits into block 2, a third block (N-K)/4 bits into block 3, a fourth block (N-K)/4 bits into block 4, a matrix equivalent to storing parity bits into one (N-K)/4 row 4 columns, column 1 representing block 1, column 2 representing block 2, column 3 representing block 3, and column 4 representing block 4; subsequently for different interleaving types, for interleaving type 1, the read-out of the parity bits is similar to the read-out of the information bits, except that the first read-out of the parity bits starts from the row defined by the parity offset parameter offset, the step size parameter StepSize, we define t= (N-K)/4, the order of the rows read out in the first round is (offset,
(offset+stepsize) mod T, (offset+2 x StepSize) mod T, …), then the second round adds 1 first, repeats StepSize-1 round, finally reads out T/StepSize row data through each round of StepSize round, and reads out T row data in total; for interlace type 2, the row pointer is not initialized every round of reading, but instead the reading (offset+stepsize) mod T, (offset+2 x StepSize) mod T, …) continues from the beginning until the T rows are read;
in this step, specific interleaving parameters of the frame control FC section are as follows:
step three, interleaving between the information code and the check code: then, for 1/3 code rate, the first 4 bits are output as information codes, and then 2 4-bit check codes are output;
step four, nibble shift: the nibble shift is carried out by taking 4 bits as a unit, the sequence is adjusted once every two nibbles no matter the information bits or the check bits, and the rule is as shown in the following table; where b0 represents block 1 with bits from information or parity bits, and so on, b1 represents t from block 2, b2 represents from block 3, b3 represents from block 4; when the bits are serially output, the leftmost bit of the 4 bits is output first, from left to right.
11. The channel coding method of claim 3, wherein bit interleaving is further performed after coding, the data after Turbo coding is kept in a pre-coding order, information bits are preceded, and check bits are followed, wherein K represents the number of information bits, N represents an actual code length after coding, N-K represents the number of check bits, K information bits are divided into 4 sub-blocks, each sub-block has a size of K/4 bits, N-K check bits are divided into 4 sub-blocks, and each sub-block has a size of (N-K)/4 bits; bit interleaving takes four steps:
step one, interleaving information codes: writing information codes output by Turbo codes into a matrix storage space, sequentially outputting a first block (K/4 bits) of information bits into a block 1, a second block (K/4 bits) into a block 2, a third block (K/4 bits) into a block 3, and a fourth block (K/4 bits) into a block 4 by an encoder, wherein the 1 st column represents a block 1, the 2 nd column represents a block 2, the 3 rd column represents a block 3, and the 4 th column represents a block 4, which is equivalent to storing the information bits into a matrix of K/4 rows and 4 columns; 4 bits of each row are read out simultaneously when interleaving is performed; when reading data from the matrix, first starting from row 0, then increasing the first row address by one read step StepSize each time, so that the first round of row address read-out is in the order (0, stepSize,
StepSize, …), after reading [ K/4]/StepSize row, reading the tail of the matrix, adding 1 to the head address of the next row, adding a step size StepSize to the row address, reading [ K/4]/StepSize row, reaching the tail again, reading row address sequence of the second row (1, 1+stepsize,1+2 x StepSize, …), adding 1 to the address of the third row, and so on, and finishing the reading of all rows after passing through the StepSize wheel;
step two, check code interleaving: firstly, classifying the interleaving types according to code length and code rate, and dividing the interleaving types into an interleaving type 1 and an interleaving type 2; performing a first block (N-K)/4 bits of parity bits output from the Turbo code into block 1, a second block (N-K)/4 bits into block 2, a third block (N-K)/4 bits into block 3, a fourth block (N-K)/4 bits into block 4, a matrix equivalent to storing parity bits into one (N-K)/4 row 4 columns, column 1 representing block 1, column 2 representing block 2, column 3 representing block 3, and column 4 representing block 4; subsequently for different interleaving types, for interleaving type 1, the read-out of the parity bits is similar to the read-out of the information bits, except that the first read-out of the parity bits starts from the row defined by the parity offset parameter offset, the step size parameter StepSize, we define t= (N-K)/4, the order of the rows read out in the first round is (offset,
(offset+stepsize) mod T, (offset+2 x StepSize) mod T, …), then the second round adds 1 first, repeats StepSize-1 round, finally reads out T/StepSize row data through each round of StepSize round, and reads out T row data in total; for interlace type 2, the row pointer is not initialized every round of reading, but instead the reading (offset+stepsize) mod T, (offset+2 x StepSize) mod T, …) continues from the beginning until the T rows are read;
in this step, the specific interleaving parameters of the Payload section are as follows:
step three, interleaving between the information code and the check code: then for 1/3 code rate, the first 4 bits are output as information codes, then 2 4-bit check codes are output, and so on; for the 1/2 code rate, the first 4 bits are output as information codes, then the 4 bits are check codes, and the like are pushed; for the 2/3 code rate, outputting the first 2 4 bits as information codes, then 4 bit check codes, and so on; for 3/4 code rate, outputting the first 3 4-bit information codes, then 4-bit check codes, and so on; for the 6/7 code rate, outputting the first 6 4 bits as information bits, then 4 bits as check bits, and the like;
step four, nibble shift: the nibble shift is carried out by taking 4 bits as a unit, the sequence is adjusted once every two nibbles no matter the information bits or the check bits, and the rule is as shown in the following table; where b0 represents block 1 with bits from information or parity bits, and so on, b1 represents t from block 2, b2 represents from block 3, b3 represents from block 4; when the bits are serially output, the leftmost bit of the 4 bits is output first, from left to right.
12. A physical layer channel decoding method, comprising the following decoding method two or a combination of decoding method two and other decoding methods:
the decoding method I comprises the steps of obtaining a log-likelihood ratio sequence of a bit stream to be decoded through signal processing steps such as synchronization, equalization, constellation mapping and the like at a receiving end, and directly sending the log-likelihood ratio sequence of the bit stream to a fixed code rate decoder for decoding; deleting the check bit after decoding to recover the effective information bit;
the signal to be received by the receiving end has the following characteristics when being generated, and the information bits to be transmitted are directly encoded with a certain fixed code rate;
after the log-likelihood ratio sequence of the bit stream to be decoded is obtained by signal processing steps such as synchronization, equalization, constellation mapping and the like at a receiving end, filling the log-likelihood ratio of a known filling sequence in a corresponding filling position according to coding generation on the log-likelihood ratio sequence of the bit stream of information, and then sending the filled log-likelihood ratio sequence to a decoder for decoding; deleting check bits and padding information bits after decoding, and recovering effective information bits;
the signal to be received by the receiving end has the following characteristics when being generated, firstly, the information bits to be transmitted are filled, then, the coding with a certain fixed code rate is carried out, and the filling bits before the coded output information bits are removed, so that the code rate lower than the fixed coding code rate is realized;
the method is characterized in that a pseudo random sequence PRBS and an alternate insertion mode are adopted to effectively improve coding performance;
the decoding method III, after the receiving end obtains the log likelihood ratio sequence of the bit stream to be decoded through signal processing steps such as synchronization, equalization, constellation mapping and the like, the log likelihood ratio information of corresponding bits is filled in the log likelihood ratio sequence of the check bit stream according to corresponding punching positions when the check bit stream is generated by encoding, and then the filled log likelihood ratio sequence is sent to a decoder for decoding; deleting the check bit after decoding to recover the effective information bit;
the signal to be received by the receiving end has the following characteristics when being generated, the information bits to be transmitted are encoded with a certain fixed code rate, and the output check bits are punched, so that the code rate higher than the fixed code rate is realized.
13. The channel decoding method of claim 12, wherein,
after the log-likelihood ratio sequence of the bit stream to be decoded is obtained at the receiving end through signal processing steps such as synchronization, equalization, constellation mapping and the like, filling the log-likelihood ratio of a known filling sequence at a corresponding position according to the code generation on the log-likelihood ratio sequence of the bit stream of the information, and then sending the filled log-likelihood ratio sequence to a mother code decoder for Turbo decoding with 1/2 code rate; deleting check bits and padding information bits after decoding, and recovering effective information bits;
the signal to be received by the receiving end has the following characteristics when being generated, firstly, the information bits to be transmitted are filled, then the Turbo coding of 1/2 code rate is carried out, and the filling bits before the information bits output by the coding are removed, so that the 1/3 code rate is realized.
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