CN101777924A - Method and device for decoding Turbo codes - Google Patents
Method and device for decoding Turbo codes Download PDFInfo
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- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
- H03M13/27—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes using interleaving techniques
- H03M13/2739—Permutation polynomial interleaver, e.g. quadratic permutation polynomial [QPP] interleaver and quadratic congruence interleaver
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- H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
- H03M13/27—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes using interleaving techniques
- H03M13/2771—Internal interleaver for turbo codes
- H03M13/2775—Contention or collision free turbo code internal interleaver
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- H03M13/29—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes combining two or more codes or code structures, e.g. product codes, generalised product codes, concatenated codes, inner and outer codes
- H03M13/2957—Turbo codes and decoding
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- H03M13/37—Decoding methods or techniques, not specific to the particular type of coding provided for in groups H03M13/03 - H03M13/35
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Abstract
The invention discloses a method and a device for decoding Turbo codes. The method comprises the following steps: as for each code block in a input sequence, dividing each code block into M numbered code segments, inputting the M numbered code segments into M numbered decoding units respectively, decoding the code segments respectively input by the M numbered decoding units in a parallel manner according to the Log-MAP algorithm, and outputting the decoded code segments, wherein M is a natural number larger than 1; in the decoding process, the forward path metric parameters and backward path metric parameters of the boundary of respective corresponding code segment are transferred between decoding units corresponding to adjacent code segments. The technical scheme of the invention can improve the Turbo decoding speed.
Description
Technical field
The present invention relates to the communication system technology, particularly relate to a kind of Turbo code interpretation method and device.
Background technology
Because the outstanding error correcting capability of nearly Shannon circle of Turbo code, Long Term Evolution (LTE, Long Term Evolution) system selects the channel coding schemes of Turbo code as high-speed data service for use.
Fig. 1 is the schematic diagram of the Turbo encoder in the prior LTE system.As shown in Figure 1, LTE adopts traditional by two parallel component coders and the Turbo encoder that interleaver is formed.Two component coders are respectively component coder 1 and component coder 2.Wherein, each component coder adopts identical structure with the WCDMA system, comprises three registers, and state number is 8.And interleaver has adopted twice replaced polynomial (QPP, Quadratic Permutation Polynomial) interleaver.Suppose the bit stream c of input interleaver
kLength be K, promptly this bit stream is c
0, c
1..., c
K-1, be c ' through the bit stream of the back output that interweaves
0, c '
1..., c '
K-1, they satisfy corresponding relation c ' so
i=c
∏ (i), the corresponding relation of the element sequence number before and after interweaving satisfies quadratic polynomial: ∏ (i)=(f
1I+f
2i
2) mod K, i=0,1 ..., K-1.Form with tabulation in the existing standard has provided under the various weaving lengths quadratic polynomial parameter f
1And f
2Pairing numerical value.The code check of encoder shown in Figure 1 is 1/3, exports 3 component (x
k, z
k, z '
k), wherein, xk is the data of input channel, z
kAnd z '
kBe verification sequence, owing to be subjected to the Turbo code influence of 12 tail bits altogether, the length of each component code is D=K+4.
Maximum a posteriori probability (the MAP of soft inputting and soft output (SISO) is adopted in Turbo code decoding, Maximum A Posteriori) algorithm, this algorithm is a posterior probability of calculating each state transitions, message bit and the coded identification of markoff process under the situation of given channel observation sequence, as long as calculate all possible posterior probability of this tittle, promptly can get the value with maximum a posteriori probability by hard decision is estimated value.The MAP algorithm is an optimal algorithm of realizing the Turbo iterative decoding.
Log-domain maximum a posteriori probability (Log-MAP) algorithm is that the log-domain of MAP algorithm is realized.The calculation procedure of Log-MAP algorithm is as follows:
(a) from k=0, according to following formula (1) Branch Computed metric D
k I, m:
Wherein, claim that γ is the branch metric parameter, k is a time index, and m is the state subscript, and σ is a constant, x
kBe channel observation sequence, y
kBe verification sequence, p is D
k I, mPrior information, the value of p can get 0 when initial, gets the external information in the last iterative process afterwards.
(b) when k=0, the initialization forward path is measured A, and utilizes D according to following formula (2)
k I, mFrom k=0 to k=N-1, calculate and storage forward path tolerance A
k m:
Here, claim that α is the forward path metric parameter.
(c) when k=N-1, to path metric B, and utilize D after the initialization according to following formula (3)
k I, mCalculating and storage back are to path metric B from k=N-2 to k=0
k m:
Here, claim that β is the forward path metric parameter.
(d) according to following formula (4) from k=0 to k=N-1 computing information bit log-likelihood ratio LLR:
Calculate external information L according to LLR
e:
Le (dk)=L (dk|Y1N)-[La (dk)+lcxk) formula (5)
(e) D that external information is calculated during as next iteration
k I, mPrior information, loop iteration computing said process until the iterations It that reaches maximum, and is made corresponding judgement according to the LLR in the last iterative process and is exported.
Wherein, max
*(x, y)=ln (e
x+ e
y)=max (x, y)+ln (1+e
-| x-y|), comprise maximizing computing and correction function f (x)=ln (1+e
-x) computing, function f (x) can adopt look-up tables'implementation.
The basic structure of the Turbo decoder of realizing based on above-mentioned Log-MAP algorithm as shown in Figure 2.
Fig. 2 is the basic block diagram of existing Turbo decoder.As shown in Figure 2, soft inputting and soft output (SISO) decoder of realization Turbo decoder is made up of the cascade of two component decoders, be respectively component decoder 1 and component decoder 2, employed interleaver is identical in the Turbo encoder among interleaver and Fig. 1, is the QPP interleaver.Being input as of component decoder 1: the log-likelihood ratio y of channel observation sequence
k s, the log-likelihood ratio y of the verification sequence of component coder 1 output among Fig. 1
k 1p, and the prior information L that extracts by the output of component decoder 2
A1(d
k).The output of component decoder 1 is log-likelihood ratio L
E1(x).L
E1(x) deduct the log-likelihood ratio y of channel observation sequence
k sAnd the prior information L of input component decoder 1
A1(d
k), obtain the external information L that component decoder 1 is exported
1e(d
k).To L
1e(d
k) interweaving obtains L
A2(d
k).Being input as of component decoder 2: the log-likelihood ratio y of channel observation sequence
k sSequence after interweaving, the log-likelihood ratio y of the checking sequence of component coder 2 outputs among Fig. 1
k 2p, and the prior information L that extracts by the output of component decoder 1
A2(d
k).The output of component decoder 2 is log-likelihood ratio L
E2(x).L
E2(x) the prior information L that deducts the channel observation sequence log-likelihood ratio after interweaving and import component decoder 2
A2(d
k), obtain the external information L that component decoder 2 is exported
2e(d
k).L
2e(d
k) knit the prior information that obtains next iteration input component decoder 1 through reciprocal cross.Like this, through iteration repeatedly, the external information that component decoder 1 and component decoder 2 are produced tends towards stability, and posterior probability ratio approaches the maximum-likelihood decoding to whole sign indicating number gradually.
Existing communication system in universal mobile telecommunications system (UMTS, UniversalMobile Telecommunication system), is selected the channel coding schemes of Turbo code as high-speed data service for use, and the data rate of its requirement is about 2Mbit/s.The decoding speed that is existing Turbo decoder is about 2Mbit/s.
But the specific design index request peak rate of LTE system reaches up 50Mbit/s, descending 100Mbit/s.The decoding speed that this means the Turbo decoder in the LTE system must satisfy the decoding output speed greater than 100Mbit/s.
Therefore, the decoding speed of existing Turbo decoder has much room for improvement.
Summary of the invention
The invention provides a kind of Turbo code interpretation method, this method can improve the Turbo code decoding speed.
The present invention also provides a kind of Turbo code code translator, and this device has improved the Turbo code decoding speed.
For achieving the above object, technical scheme of the present invention is achieved in that
The invention discloses a kind of Turbo code interpretation method, this method comprises:
For each code block in the list entries, this code block is divided into M sign indicating number section, M is the natural number greater than 1, M sign indicating number section inputed to M decoding unit respectively, decipher input code section separately is parallel according to log-domain maximum a posteriori probability Log-MAP algorithm by M decoding unit, and the sign indicating number section after the output decoding;
Wherein, pairing two decoding units of two sign indicating number sections that any front and back are adjacent are called first decoding unit and second decoding unit, then in decode procedure, first decoding unit transmits the forward path metric parameter of the ending boundary point of self sign indicating number section to second decoding unit, so that second decoding unit calculates the forward path metric parameter of the initial boundary point of self sign indicating number section; And second decoding unit transmits initial boundary point back to the path metric parameter of self sign indicating number section to first decoding unit, so that first decoding unit calculates ending boundary point back to the path metric parameter of self sign indicating number section.
The invention also discloses a kind of Turbo code code translator, this device comprises: M decoding unit, M are the natural number greater than 1;
Each code block in the list entries inputs to a described M decoding unit respectively after being divided into M sign indicating number section;
Each decoding unit is used to receive the sign indicating number section of input, according to log-domain maximum a posteriori probability Log-MAP algorithm the input code section is deciphered, with the sign indicating number section output after the decoding;
Wherein, pairing two decoding units of two sign indicating number sections that any front and back are adjacent are called first decoding unit and second decoding unit, then in decode procedure, first decoding unit transmits the forward path metric parameter of the ending boundary point of self sign indicating number section to second decoding unit, so that second decoding unit calculates the forward path metric parameter of the initial boundary point of self sign indicating number section; And second decoding unit transmits initial boundary point back to the path metric parameter of self sign indicating number section to first decoding unit, so that first decoding unit calculates ending boundary point back to the path metric parameter of self sign indicating number section.
As seen from the above technical solution, the present invention is this to input to a plurality of decoding units respectively after each code block in the list entries is divided into a plurality of yards sections, decipher the sign indicating number section of input separately is parallel according to the Log-MAP algorithm by a plurality of decoding units, wherein, in decode procedure, transmit the forward path metric parameter and the technical scheme of back of correspondence code section boundary between the pairing decoding unit of adjacent code section to the path metric parameter, a plurality of decoding units are parallel to be deciphered owing to have, therefore improved decoding speed greatly, and the quantity of decoding unit is many more, and decoding speed is fast more.
Description of drawings
Fig. 1 is the schematic diagram of the Turbo encoder in the prior LTE system;
Fig. 2 is the basic block diagram of existing Turbo decoder;
Fig. 3 is the composition structured flowchart of the Turbo code code translator in the embodiment of the invention;
Fig. 4 is the transmission schematic diagram of boundary condition value between the adjacent decoding unit in the Turbo decoder in the embodiment of the invention;
Fig. 5 is the composition structural representation of the code translator that comprises the multi-stage pipeline sub-decoder in the embodiment of the invention;
Fig. 6 is the partial interior structural representation of the SISO decoder in the embodiment of the invention;
Fig. 7 is the overall sequential operation figure of the Turbo code translator in the embodiment of the invention.
Embodiment
Because existing Turbo code code translator includes only a decoding unit that comprises basic structure shown in Figure 2, by this unique decoding unit each code block of list entries (being sequence to be decoded) is deciphered, decoding speed is subject to the decoding efficiency of this unique decoding unit, therefore decoding speed is low, can not satisfy the high-speed data service demand of systems such as LTE.
Based on this, core concept of the present invention is: by a plurality of decoding units employing Log-MAP algorithms the parallel Turbo code that carries out of different sign indicating number sections of each code block in the list entries is deciphered, and needs according to the Log-MAP algorithm, in decode procedure, need to transmit the forward path metric parameter of correspondence code section boundary separately and back between the adjacent decoding unit to the path metric parameter.
The parallel scheme of deciphering of this a plurality of decoding unit can improve the speed of Turbo code decoding exponentially, and the parallel decoding unit quantity of deciphering is many more, and decoding speed is fast more.Therefore, can be in the middle of actual according to the number of the decoding speed requirements set decoding unit of reality.
Fig. 3 is the composition structured flowchart of the Turbo code code translator in the embodiment of the invention.As shown in Figure 3, the Turbo code code translator in the present embodiment comprises: the decoding unit that input-buffer, output buffers, interleaving/deinterleaving memory and M are parallel, and M is any natural number greater than 1, for example 4,8,16 etc.
In Fig. 3, input-buffer and output buffers be used for string and with and string conversion, input-buffer realizes that also ping-pong operation is to improve throughput.The ping-pong operation here is meant that input-buffer will import data and optionally export to different decoding units, for example, first yard section of a certain code block is sent to decoding unit 1, second sign indicating number section of this code block is sent to decoding unit 2, by that analogy.The interleaving/deinterleaving memory is used for storing that process that each decoding unit carries out Turbo code decoding computing interweaves or the data of deinterleaving computing.M decoding unit is used for according to the Log-MAP algorithm input code section (the input code section comprises channel observation sequence and verification sequence) being deciphered, and the sign indicating number section after will deciphering outputs to output buffers.Each decoding unit is here all finished the decoding algorithm function that basic structure shown in Figure 2 is finished, and promptly each decoding unit all comprises two component decoders and the corresponding interleaver and the deinterleaver of cascade.
According to the formula (2) in the log-MAP algorithm of introducing in the background technology and formula (3) as can be known, depend on the forward path metric parameter of its previous point corresponding to the calculating of the forward path metric parameter α of certain point, and depend on the back of a point thereafter to the calculating of path metric parameter beta thereafter to the path metric parameter.Therefore, because the calculating of Log-MAP algorithm needs, code translator shown in Figure 3 is in decode procedure, transmit the forward path metric parameter of correspondence code section boundary separately and back between the pairing decoding unit of each adjacent code section to the path metric parameter, be specially: adjacent pairing two decoding units of two sign indicating number sections in front and back are called first decoding unit and second decoding unit arbitrarily, then in decode procedure, first decoding unit transmits the forward path metric parameter of the ending boundary point of self sign indicating number section to second decoding unit, so that second decoding unit calculates the forward path metric parameter of the initial boundary point of self sign indicating number section; And second decoding unit transmits initial boundary point back to the path metric parameter of self sign indicating number section to first decoding unit, so that first decoding unit calculates ending boundary point back to the path metric parameter of self sign indicating number section.
For example, when one 80000 list entries need carry out Turbo code decoding, (mode that list entries is divided into a plurality of code blocks is same as the prior art at first to be divided into a plurality of code blocks with these 80000, do not do qualification among the present invention, for example can divide etc.) according to the size of input-buffer, here hypothesis is divided into 10 code blocks, i.e. each code block 8000 point; For each code block, this code block is divided into M sign indicating number section, here establish M and equal 8, preferably be divided into M=8 of equal in length sign indicating number section, i.e. each yard section 1000 points input to these 8 sign indicating number sections respectively that 8 decoding units are parallel to be deciphered, be that in 1 pair of this code block of decoding unit 1～1000 deciphers, 2 pairs 1001～2000 of decoding units are deciphered ..., 8 pairs 7001～8000 of decoding units are deciphered.The front is mentioned, according to the formula (2) in the log-MAP algorithm of introducing in the background technology and formula (3) as can be known, depend on the forward path metric parameter of its previous point corresponding to the calculating of the forward path metric parameter α of certain point, and depend on the back of a point thereafter to the calculating of path metric parameter beta thereafter to the path metric parameter.Therefore decoding unit 1 need pass to decoding unit 2 with the forward path metric parameter of the 1000th point, so that decoding unit 2 calculates the forward path metric parameter of the 1001st point; Correspondingly, decoding unit 2 need pass to decoding unit 1 to the path metric parameter with the back of the 1001st point, so that decoding unit 1 calculates the back to the path metric parameter of the 1000th point.Between same other the adjacent decoding unit,, all in decode procedure, transmit the forward path metric parameter of correspondence code section boundary and back to the path metric parameter as between decoding unit 2 and the decoding unit 3, between decoding unit 3 and the decoding unit 4 etc.
Fig. 4 is the transmission schematic diagram of boundary condition value between the adjacent decoding unit in the Turbo decoder in the embodiment of the invention.The boundary condition value here refers to the forward path metric parameter α value of the pairing sign indicating number of each decoding unit section boundary point or afterwards to path metric parameter beta value.Referring to Fig. 4, transmit the α value or the β value of correspondence code segment boundary point between the component decoder of the correspondence in each adjacent decoding unit mutually, for example for adjacent decoding unit 1 and decoding unit 2, transmit the α value or the β value of correspondence code segment boundary point between its component decoder 1 separately, transmit the α value or the β value of correspondence code segment boundary point between its component decoder 2 separately.
In the present invention, the number M of the decoding unit that comprises in the Turbo code code translator can be decided according to actual conditions, for example in the LTE system, determines the number of decoding unit according to the LTE decoding rate demand of reality.Therefore this code block is divided into a plurality of yards sections,, has improved the throughput of Turbo code code translator greatly and reduced decoding and postpone by the parallel scheme of deciphering of a plurality of decoding units.According to the Turbo code Design of Interleaver criterion in the LTE system, can guarantee code translator interweave and deinterleaving during, the memory access conflict problem can not take place between each decoding unit, thereby guaranteed the reliability of above-mentioned parallel organization design.
In order further to improve the decoding speed of Turbo code code translator, in one embodiment of the present of invention, each decoding unit in the Turbo code code translator all is designed to the structure of multi-stage pipeline sub-decoder, be a plurality of sub-decoders that each decoding unit comprises concatenated in order, these a plurality of sub-decoders are finished It interative computation (It is for deciphering required total iterations of finishing according to the Log-MAP algorithm to the input code section) jointly, and each sub-decoder is finished It/R interative computation wherein, and It and It/R are natural number.For example, total iterations 12, if each decoding unit comprises the two-stage sub-decoder, then first order sub-decoder is finished preceding 6 interative computations of a sign indicating number section, second level sub-decoder is finished back 6 interative computations of this yard section; Like this after first order sub-decoder is finished preceding 6 interative computations of the corresponding sign indicating number section in a certain code block, proceed the 7th iteration of this yard section by second level sub-decoder, and this moment, first sub-decoder can carry out interative computation the 1st time to the corresponding sign indicating number section in the next code block, so decoding rate is equivalent to be doubled.Again for example, total iterations still is 12 o'clock, if each decoding unit comprises three grades of sub-decoders, then first order sub-decoder is finished preceding 4 interative computations of sign indicating number section, second level sub-decoder is finished 4 interative computations of the centre of this yard section, and third level sub-decoder is finished back 4 interative computations of this yard section; In this case, decoding rate is equivalent to improve twice.By that analogy, the number of the cascade sub-decoder that is provided with in the decoding unit is many more, and promptly pipeline series is many more, and decoding rate is fast more.
Fig. 5 is the composition structural representation of the code translator that comprises the multi-stage pipeline sub-decoder in the embodiment of the invention.As shown in Figure 5, in the present embodiment with M decoding unit, R level production line sub-decoder is that example describes, here R is any natural number greater than 1, all one-level sub-decoders in M decoding unit constitute first order streamlines, all secondary sub-decoders in M decoding unit constitute second level streamlines ..., all the R level sub-decoders in M decoding unit constitute the R level production line.
Illustrated the internal structure of first order streamline and second level streamline in Fig. 5, the structure of each level production line afterwards (to the R level, R was more than or equal to 3 o'clock from the third level) is identical with the structure of second level streamline, the Therefore, omited.
In Fig. 5, represent data selector with MUX, represent the SISO decoder that soft inputting and soft is exported with SISO, show the external information memory with ram table, represent external information with Le.Then corresponding M UX, SISO in MUX11, SISO11, RAM11, MUX21, SISO21, RAM21 and the subsequent pipeline and RAM device constitute decoding unit 1, wherein, MUX11, SISO11, RAM11 constitute the one-level sub-decoder in the decoding unit 1, MUX21, SISO21 and RAM21 constitute the secondary sub-decoder in the decoding unit 1, by that analogy.Equally, corresponding M UX in MUX12, SISO12, RAM12, MUX22, SISO22, RAM22 and the subsequent pipeline, SISO and RAM device constitute decoding unit 2, wherein, MUX21, SISO21, RAM21 constitute the one-level sub-decoder in the decoding unit 2, MUX22, SISO22 and RAM22 constitute the secondary sub-decoder in the decoding unit 2, by that analogy.The formation of follow-up decoding unit also by that analogy.In each sub-decoder, the SISO decoder is read and write corresponding RAM by the data switch bus.
In Fig. 5, each data selector MUX is used for when interative computation first initial external information exported to corresponding SISO decoder, after interative computation the time external information that will obtain from the RAM of correspondence export to the SISO decoder of correspondence; Wherein, the MUX in the one-level sub-decoder is 0 as initial external information, the MUX in other each sub-decoders except that the one-level sub-decoder, and the external information that the last interative computation of its upper level sub-decoder is obtained is as initial external information.Each SISO decoder utilizes the data and the input code section of MUX output to carry out interative computation It/R time, and the external information that each interative computation obtains is sent to corresponding RAM; Each RAM is used to store the external information that the each interative computation of SISO decoder is produced, and provides this external information to the MUX of correspondence, carries out next time interative computation so that MUX sends to the SISO unit with this external information.
In Fig. 5, pairing two decoding units of two sign indicating number sections that any front and back are adjacent are called first decoding unit and second decoding unit, then in decode procedure: the corresponding sub-decoder of each sub-decoder in first decoding unit in second decoding unit transmits the forward path metric parameter of the ending boundary point of self sign indicating number section, so that the corresponding sub-decoder in second decoding unit calculates the forward path metric parameter of the initial boundary point of self sign indicating number section; The corresponding sub-decoder of each sub-decoder in second decoding unit in first decoding unit transmits initial boundary point back to the path metric parameter of self sign indicating number section, so that the corresponding sub-decoder in first decoding unit calculates ending boundary point back to the path metric parameter of self sign indicating number section.For example, between the SISO13 in the sub-decoder 1 between the SISO11 and the SISO12 in the sub-decoder 1 in the decoding unit 2 in the sub-decoder 1 in decoding unit 1, in the sub-decoder 1 in the decoding unit 2 in SISO12 and the decoding unit 3, between the SISO21 in the sub-decoder 2 in the decoding unit 1 and the SISO22 in the sub-decoder 2 in the decoding unit 2 etc., all need to transmit the forward path metric parameter of corresponding separately input code section boundary and back to the path metric parameter.
In Fig. 5, input-buffer is used to store list entries, this list entries comprises channel information and verification sequence, according to demand different code blocks is input in the various flows waterline by the RAM chip selection logic, and the code block that will import a streamline is divided in a plurality of decoding units that are input to respectively after a plurality of yards sections in this streamline.Sign indicating number section after each decoding unit will be deciphered outputs to the hard decision unit; The hard decision unit is used to receive the sign indicating number section after the decoding of M decoding unit output, carries out outputing in the output buffers behind the hard decision to deciphering back sign indicating number section.The hard decision mode here is same as the prior art, is meant each information is all carried out following judgement: be output as 1 if this information, is then adjudicated corresponding positions more than or equal to 0; If this information, is then adjudicated corresponding positions less than 0 and is output as 0.
In structure shown in Figure 5, key issue is, how the external information that the upper level streamline is produced passes to its next stage streamline as the prior information of its next stage streamline.Below with R=2, promptly the code translator of two level production lines is that example is illustrated this problem: with total iterations be 12 times be example, first order streamline is when component decoder 2 computings that the 6th iteration handling the n-1 code block is far away in calculating, still according to the read-write of the address after interweaving RAM; After this second level streamline begins the 7th interative computation of n-1 code block, and first order streamline begins next code block, i.e. the 1st of the n code block the interative computation.When second level streamline begins to carry out the 7th interative computation of n-1 code block, carry out 1 computing of component decoder earlier, read external information Le among the RAM of the address that need increase progressively in order from first order streamline; At this moment, first order streamline is being handled component decoder 1 calculating process in the 1st interative computation of n code block, need read and write Le in proper order from above-mentioned address ram.Read but write always to be slower than, therefore, the sub-decoder in the streamline of the second level has time enough to obtain Le information (in fact reading Le with first order pipeline synchronization) from the RAM of first order streamline.Because the front and back stages sub-decoder all is the address read Le information that increases progressively in order, and the Le information that the one-level sub-decoder writes back always is slower than the process of reading, and therefore, can guarantee that the Le information in the first order streamline can correctly pass to second level streamline.Le before the data selector MUX in the second level streamline among Fig. 5 represents from the next external information of first order streamline transmission.
Each SISO decoder among Fig. 5 all comprises basic structure shown in Figure 2, and promptly each SISO decoder all comprises two component decoders and corresponding interleaver and deinterleaver.These two component decoders represent that with component decoder 1 and component decoder 2 component decoder 1 and component decoder 2 are finished interative computation jointly one time, and its algorithm function of carrying out separately is identical with two component decoders among Fig. 2.Also comprise corresponding address calculation module in each SISO decoder in addition.Between component decoder 1 operational stage, the address that address calculation module increases progressively in order is by the corresponding RAM of data access bus switches read-write; Between component decoder 2 operational stages, address calculation module is according to the RAM of the address after interweaving by data access bus switches read-write correspondence.
Fig. 6 is the partial interior structural representation of the SISO decoder in the embodiment of the invention.As shown in Figure 6, the one-component decoder in the SISO decoder and the structural representation of address calculation module have been illustrated.Here, because the internal structure of two component decoders in the SISO decoder is identical, therefore only illustrated the internal structure of one of them component decoder.
As shown in Figure 6, the one-component decoder in the SISO decoder comprises: branch metric calculation module, state update module, memory module, control module and external information computing module;
Wherein, the branch metric calculation module is used for according to input information Branch Computed metric parameter, and sends to state update module and external information computing module; The input information here comprises channel information and prior information, and channel information comprises channel observation sequence and verification sequence;
The state update module is used for going out the forward path metric parameter according to the branch metric calculation of parameter that receives, and sends to memory module and preserve, and goes out the back to the path metric parameter according to the branch metric calculation of parameter that receives, and sends to the external information computing module;
Memory module is used to preserve the forward path metric parameter from the state update module;
The external information computing module is used for calculating external information and output according to input information, from the branch metric parameter of branch metric calculation module, back to the path metric parameter and from the forward path metric parameter of memory module from the state update module;
Control module is used for branch metric calculation module, state update module, memory module and external information computing module are carried out sequencing control.
As shown in Figure 6, address calculation module comprises a data selector MUX and an interleaving address computing unit; Wherein, first of MUX is input as the original address information that increases progressively of order, and second is input as interweave address information after calculating of original address information via interleaving address computing unit; When the component decoder in the SISO decoder 1 carried out computing, as OPADD, when component decoder 2 carried out computing, address calculation module was selected second input as OPADD with first input in the address calculation module selection.
Each component decoder each quantity of state of Log-MAP algorithm computation γ, α, β and information bit log-likelihood ratio LLR and external information Le in the SISO unit.For the process of calculating γ, α, β, LLR and Le, need be divided into two step priorities and finish, be i.e. forward recursion process and backward recursion process.The forward recursion process need consumes L/M (L is the length of code block, and M is the number of decoding unit) individual computation of Period γ and α, and storage α value.Then carry out the backward recursion computing, consume L/M computation of Period γ, β, LLR and Le.The above-mentioned forward recursion and the process of backward recursion are successively to carry out, because the recursion of α and β all needs to use the γ value, and the γ value can only select forward direction or back to computing in once calculating.In order to further specify technical scheme of the present invention, provide the overall sequential operation figure of the Turbo code translator in the embodiment of the invention below.
Fig. 7 is the overall sequential operation figure of the Turbo code translator in the embodiment of the invention.As shown in Figure 7, with R level production line sub-decoder structure is example, R is any natural number, be each decoding unit by one-level sub-decoder, secondary sub-decoder ..., when R level sub-decoder constitutes, all one-level sub-decoders of formation first order streamline are finished preceding It/R the iteration of each code block and are far calculated, all secondary sub-decoders of formation second level streamline are finished second It/R iteration of each code block and are far calculated, ..., all R level sub-decoders that constitute the R level production line are finished the It/R time last interative computation of each code block.Here, It is total iterations.The far away calculation of each iteration comprises that 1 computing of component decoder and 2 computings of component decoder, each component decoder computing comprise forward recursion γ and α computing and back first recursion γ, β, LLR and Le computing again.
In sum, the present invention is this to be divided into a plurality of code blocks with list entries, input to a plurality of decoding units respectively after each code block being divided into a plurality of yards sections of equal in length, decipher the sign indicating number section of input separately is parallel according to the Log-MAP algorithm by a plurality of decoding units, wherein, in decode procedure, transmit the forward path metric parameter and the technical scheme of back of respectively answering the sign indicating number section boundary between the adjacent decoding unit to the path metric parameter, a plurality of decoding units are parallel to be deciphered owing to have, therefore improved decoding speed greatly, and the quantity of decoding unit is many more, and decoding speed is fast more.In addition, also further decoding unit is designed to the structure of multi-stage pipeline among the present invention, has further improved decoding speed, and the progression of streamline is many more, decoding speed is fast more.
The above only is preferred embodiment of the present invention, and is in order to restriction the present invention, within the spirit and principles in the present invention not all, any modification of being made, is equal to replacement, improvement etc., all should be included within the scope of protection of the invention.
Claims (10)
1. a Turbo code interpretation method is characterized in that, this method comprises:
For each code block in the list entries, this code block is divided into M sign indicating number section, M sign indicating number section inputed to M decoding unit respectively, decipher input code section separately is parallel according to log-domain maximum a posteriori probability Log-MAP algorithm by M decoding unit, and the sign indicating number section after the output decoding;
Wherein, pairing two decoding units of two sign indicating number sections that any front and back are adjacent are called first decoding unit and second decoding unit, then in decode procedure, first decoding unit transmits the forward path metric parameter of the ending boundary point of self sign indicating number section to second decoding unit, so that second decoding unit calculates the forward path metric parameter of the initial boundary point of self sign indicating number section; And second decoding unit transmits initial boundary point back to the path metric parameter of self sign indicating number section to first decoding unit, so that first decoding unit calculates ending boundary point back to the path metric parameter of self sign indicating number section.
2. method according to claim 1 is characterized in that, each decoding unit comprises R sub-decoder, and R is a natural number;
A described M decoding unit comprises according to parallel decoding of sign indicating number section of Log-MAP algorithm to input separately: for each decoding unit, finish jointly according to the Log-MAP algorithm by the sub-decoder of the R in this decoding unit the input code section is deciphered required It the interative computation of finishing, and each sub-decoder is finished It/R interative computation wherein; Wherein, It and It/R are natural number;
Described first decoding unit is to the forward path metric parameter of the ending boundary point of second decoding unit transmission self sign indicating number section, so that second decoding unit calculates the forward path metric parameter of the initial boundary point of self sign indicating number section: the corresponding sub-decoder of each sub-decoder in first decoding unit in second decoding unit transmits the forward path metric parameter of the ending boundary point of self sign indicating number section, so that the corresponding sub-decoder in second decoding unit calculates the forward path metric parameter of the initial boundary point of self sign indicating number section;
Described second decoding unit transmits initial boundary point back to the path metric parameter of self sign indicating number section to first decoding unit, so that first decoding unit calculates the back of ending boundary point of self sign indicating number section: the corresponding sub-decoder of each sub-decoder in second decoding unit in first decoding unit transmits initial boundary point back to the path metric parameter of self sign indicating number section, so that the corresponding sub-decoder in first decoding unit calculates ending boundary point back to the path metric parameter of self sign indicating number section.
3. method according to claim 1 and 2 is characterized in that, the equal in length of described M the sign indicating number section that marks off;
And/or,
This method further comprises: the sign indicating number section after the decoding is carried out hard decision.
4. a Turbo code code translator is characterized in that, this device comprises: M decoding unit, M are the natural number greater than 1;
Each code block in the list entries inputs to a described M decoding unit respectively after being divided into M sign indicating number section;
Each decoding unit is used to receive the sign indicating number section of input, according to the Log-MAP algorithm input code section is deciphered, with the sign indicating number section output after the decoding;
Wherein, pairing two decoding units of two sign indicating number sections that any front and back are adjacent are called first decoding unit and second decoding unit, then in decode procedure: first decoding unit transmits the forward path metric parameter of the ending boundary point of self sign indicating number section to second decoding unit, so that second decoding unit calculates the forward path metric parameter of the initial boundary point of self sign indicating number section; And second decoding unit transmits initial boundary point back to the path metric parameter of self sign indicating number section to first decoding unit, so that first decoding unit calculates ending boundary point back to the path metric parameter of self sign indicating number section.
5. device according to claim 4 is characterized in that, each decoding unit comprises R sub-decoder of concatenated in order, is followed successively by: one-level sub-decoder, secondary sub-decoder ..., R level sub-decoder; Wherein, R is a natural number;
Finish jointly according to the Log-MAP algorithm by this R sub-decoder the input code section is deciphered required It the interative computation of finishing, and each sub-decoder is finished It/R interative computation wherein; It and It/R are natural number.
Wherein, in decode procedure: the corresponding sub-decoder of each sub-decoder in first decoding unit in second decoding unit transmits the forward path metric parameter of the ending boundary point of self sign indicating number section, so that the corresponding sub-decoder in second decoding unit calculates the forward path metric parameter of the initial boundary point of self sign indicating number section; The corresponding sub-decoder of each sub-decoder in second decoding unit in first decoding unit transmits initial boundary point back to the path metric parameter of self sign indicating number section, so that the corresponding sub-decoder in first decoding unit calculates ending boundary point back to the path metric parameter of self sign indicating number section.
6. according to claim 4 or 5 described devices, it is characterized in that this device further comprises: the hard decision unit;
Described each decoding unit is used for the sign indicating number section after the decoding is outputed to the hard decision unit;
Described hard decision unit is used to receive the sign indicating number section after the decoding of M decoding unit output, carries out exporting behind the hard decision to deciphering back sign indicating number section.
7. device according to claim 5 is characterized in that, each sub-decoder comprises: data selector, soft inputting and soft output SIS O decoder and external information memory;
Data selector is used for when interative computation first initial external information being exported to the SISO decoder, after interative computation the time will export to the SISO decoder from the external information that the external information memory obtains; Wherein, the data selector in the one-level sub-decoder is 0 as initial external information, and the external information that the data selector in other sub-decoders obtains the last interative computation of upper level sub-decoder is as initial external information;
The SISO decoder utilizes the data and the input code section of data selector output to carry out interative computation It/R time, and the external information that each interative computation obtains is sent to the external information memory;
The external information memory is used to store the external information that the each interative computation of SISO decoder is produced, and provides this external information to data selector, carries out next time interative computation so that data selector sends to the SISO unit with this external information;
Wherein, in decode procedure: SISO decoder in the corresponding sub-decoder of the SISO decoder in each sub-decoder in first decoding unit in second decoding unit transmits the forward path metric parameter of the ending boundary point of self sign indicating number section, so that the SISO decoder in the corresponding sub-decoder in second decoding unit calculates the forward path metric parameter of the initial boundary point of self sign indicating number section; SISO decoder in the corresponding sub-decoder of SISO decoder in each sub-decoder in second decoding unit in first decoding unit transmits initial boundary point back to the path metric parameter of self sign indicating number section, so that the SISO decoder calculates ending boundary point back to the path metric parameter of self sign indicating number section in the corresponding sub-decoder in first decoding unit.
8. device according to claim 7 is characterized in that, further comprises the data access bus switches at each sub-decoder;
In each sub-decoder, the SISO decoder is read and write by the external information-storing device of data switch bus.
9. device according to claim 7 is characterized in that, each SISO decoder comprises: the component decoder of address calculation module and two cascades; The component decoder of described two cascades is the first component decoder and second component decoder;
The first component decoder and second component decoder are finished interative computation jointly one time;
Between the first component decoder operational stage, the corresponding external information memory of address read-write that address calculation module increases progressively in order;
Between second component decoder operational stage, address calculation module is according to the corresponding external information memory of the read-write of the address after interweaving.
10. device according to claim 9 is characterized in that, each component decoder comprises: branch metric calculation module, state update module, memory module, control module and external information computing module;
The branch metric calculation module is used for according to input information Branch Computed metric parameter, and sends to state update module and external information computing module;
The state update module is used for going out the forward path metric parameter according to the branch metric calculation of parameter that receives, and sends to memory module and preserve, and goes out the back to the path metric parameter according to the branch metric calculation of parameter that receives, and sends to the external information computing module;
Memory module is used to preserve the forward path metric parameter from the state update module;
The external information computing module is used for calculating external information and output according to input information, from the branch metric parameter of branch metric calculation module, back to the path metric parameter and from the forward path metric parameter of memory module from the state update module;
Control module is used for branch metric calculation module, state update module, memory module and external information computing module are carried out sequencing control.
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