CN105915235A - Intel CPU-based parallel Turbo decoding method - Google Patents

Abstract

The invention discloses an Intel CPU-based parallel Turbo decoding method comprising the following steps: (1) Turbo decoding operation is accelerated via a single instruction multiple data stream instruction; in the single instruction multiple data stream instruction, 128 bits are distributed to each code block, the number of parallel code blocks is determined according to an instruction bit width supported by a CPU, pertinent codes are written, and internal operation of each code block is enabled to be as same as single code block coding operation; (2) in the single instruction multiple data stream instruction, a forward direction state measurement value alpha and a reverse direction state measurement value beta are calculated at the same time in a log-likelihood ratio mode, and two intermediate vectors respectively having a positive state and a negative state are generated in calculating processes; when a time sequence is k, a sequence number of alpha is set as k, and a sequence number of beta is code length N-1-K. When k reaches or exceeds a half of N, alpha and beta of a time sequence N-1-K are loaded into vectors and positions are switched, the vectors and the two intermediate vectors in the time sequence k are subjected to calculating operation, and log-likelihood ratio information can be obtained and output.

Description

A kind of parallel Turbo decoding method based on Intel CPU

Technical field

The invention belongs to field of data transmission, relate to Turbo interpretation method in a kind of transmitter physical layer.

Background technology

In a communications system, in order to make channel capacity approach shannon limit, a lot of in the case of can use Turbo coding and decoding skill Art.Turbo coding step is relatively simple, decodes the most relative complex.In order to meet the two-forty of communication system requirements, need to the greatest extent The handling capacity of Turbo decoding may be improved.

The Turbo decoding of mobile communication in the past is carried out often in specific DSP platform.Refer to along with Intel CPU is mono- Making the development of multiple data stream, its computing capability is increasingly stronger, and Turbo based on Intel CPU decoding also begins to be occurred and continuous Improve.Turbo based on Intel CPU decoding in the past unrealized parallel decoding under single-instruction multiple-data stream (SIMD) instructs.

Summary of the invention

Technical problem: the present invention provides a kind of and uses single-instruction multiple-data stream (SIMD) instruction to realize many code blocks parallel Turbo decoding Method.

Technical scheme: the Turbo interpretation method based on Intel CPU of the present invention, specifically includes following steps:

(1) in single-instruction multiple-data stream (SIMD) instructs, each code block distributes 128, sets parallel code block number and supports as CPU Instruction bit wide divided by 128；Iteration indicator index=0 is set；

(2) each code block carrying out solution respectively to cut out, each code block obtains two string system informations L_sys0, L_sys1With two string schools Test information L_p0, L_p1, described system information L_sys1By system information L_sys0Intertexture obtains, described L_sys0、L_p0By the component in system Decoder 0 processes, described L_sys1、L_p1Processed by the component decoder 1 in system；

(3) with branched measurement value that each sequential in each code block of log-likelihood ratio form calculus component decoder 0 is corresponding γ₁₁、γ₁₀, i.e. γ₁₁=0.5 (L_sys+L_p+L_a), γ₁₀=0.5 (L_sys-L_p+L_a), wherein L_aFor prior information, L_sysFor L_sys0With L_sys1General symbol(s), L_pFor L_p0And L_p1General symbol(s)；

(4) in component decoder 0, in sequential k, θ is built^k+1, particularly as follows: according to the convolutional code generator matrix of each code block List bifurcation state metric γ₁₁ ^k、γ₁₀ ^kCorresponding sequence, by γ₁₁ ^k、γ₁₀ ^kBy described corresponding sequence construct vector γ^k；

Single-instruction multiple-data stream (SIMD) instruction is used to carry out vector calculus, i.e. θ^k+=θ^k+γ^k, θ^k-=θ^k-γ^k, then according to volume Long-pending code generator matrix corresponding states position changes θ^k+, θ^k-Internal data rearranges；Seek θ^k+And θ^k-The maximum of corresponding data It is worth the vector theta as next sequential^k+1, then it is normalized；

Wherein, θ^kProduced by a upper sequential, θ^kIn comprise eight forward state metric values α of parallel code block_j ^kAnti-with eight To state measurement value β_j ^m, j is number of state indexes, and N is system code length, as k=0, and θ⁰Internal data is: α₀ ⁰=-127, β₀ ^N-1=- 127, α_j≠0 ⁰=0, β_j≠0 ^N-1=0；θ^k+、θ^k-It is respectively positive and negative middle vector, m=N-k-1 for state；

(5), in component decoder 0, when sequential k is less than the half of N, makes k=k+1, and return step (4), be otherwise loaded into Vector theta^m, the α internal by it_j ^mAnd β_j ^kReversing of position, calculates L according to following formula^k+And L^k-:

L^k+=θ^m+θ^k+, L^k-=θ^m+θ^k-,

Wherein L^k+And L^K-The state of being respectively is vector in the middle of positive and negative output log-likelihood ratio；Described L^k+And L^k-Each arrow The output log-likelihood ratio intermediate value of internal eight the k sequential having parallel code block respectively of amount and the output logarithm of eight m sequential are seemingly So than intermediate value；

Obtain L respectively^k+The maximum l of the output log-likelihood ratio intermediate value of middle k sequential and m sequential^k+And l^m+, L^k-During middle k The maximum l of the output log-likelihood ratio intermediate value of sequence and m sequential^k-And l^m-, then calculate l^k+-l^k-It is i.e. the output in k moment Log-likelihood ratio information, l^m+-l^m-It is i.e. the output log-likelihood ratio information in m moment；If k=N-1, then enter step (6), no Then make k=k+1, and return step (4)；

(6) according to the processing method of component decoder 0 in described step (3) to (5) and flow process, in component decoder 1 Carry out component decoding, obtain exporting log-likelihood ratio information, then by formula L_e=L_o-L_sys-L_aObtain external information L_e, currently When decoder is decoder 0, by L_e0Interweave and obtain prior information L of decoder 1_a1, when current decoder is decoder 1, by L_e1 Deinterleave prior information L obtaining decoder 0_a0, wherein L_e0、L_a0For external information and the prior information of decoder 0, L_e1、L_a1 For external information and the prior information of decoder 1, L_eIt is L_e0、L_e1General symbol(s), L_aIt is L_a0、L_a1General symbol(s)；

(7) iteration indicator index accumulates once, and such as index < 6, then returns step (3), as index=6, and decoding Terminate.

Further, in the inventive method, in described step (1), cpu instruction collection bit wide is 256；Parallel code block is set Number is 2, and the computing in described step (3) to (6) uses AVX2 instruction set to process.

Further, in the inventive method, in described step (1), cpu instruction collection bit wide is 512, arranges parallel code block Number is 4, and the computing in described step (3) to (6) uses AVX512 instruction set to process.

Further, in the inventive method, described step (4) neutralizes and uses single-instruction multiple-data stream (SIMD) instruction to realize in (5) Forward state metric value and the parallel computation of reverse state metric value.

Further, in the inventive method, the normalized in described step (4) is: θ^k+1Internal 8 states α^k+1、β^m-1All deduct 0 state value α of this metric₀ ^k+1、β₀ ^m-1。

The present invention is compared with existing solid size block decoding method, and the method processes multiple code block number within the same instructions cycle According to, the multiple that improved efficiency is identical with parallel code block number.Compared with the method that existing forward respectively calculates α backwards calculation β, The method completes the former forward and reverse calculating, improved efficiency one times within the same instructions cycle.

Beneficial effect: the present invention compared with prior art, has the advantage that

, better performances the most perfect with the srsLTE project on github in current Turbo decoder implementation, this Scheme uses AVX instruction set, 128 senior vector registers, 16 fixed points, solid size block decoding, and order calculates the side of α, β Method.The present invention, compared with this scheme, has a characteristic that

(1) when the instruction set that single-instruction multiple-data stream (SIMD) instruction set is AVX2, AVX512 or renewal that CPU supports, this Bright corresponding increase parallel code block number also uses corresponding instruction to make full use of the bit wide that instruction set is supported during decoding； Not for AVX2 or the method for the instruction set of renewal in srsLTE, it is impossible to give full play to processor performance；Due to AVX, The instruction cycle of AVX2 and AVX512 is identical, but the data volume processed is the most double, then use AVX2 and AVX512 real Existing parallel decoding is identical with using AVX solid size block decoding required time, when instruction set is AVX2, and the vector that this method is corresponding Computing handling capacity is the twice of vector calculus handling capacity in srsLTE, when instruction set is AVX512, and the vector that this method is corresponding Computing handling capacity is four times of vector calculus handling capacity in srsLTE；

(2) method of parallel computation α, β that the present invention uses is to represent fixed-point number with 8, arranges 8 shapes in 128 The α of state and the β of 8 states, and srsLTE represents fixed-point number with 16,128 can only arrange 8 16 fixed-point numbers, because of In this same instructions cycle, this method can be with parallel computation α, β, and the method in srsLTE can only serial computing α, β；Additionally exist When calculating output log-likelihood ratio, due to the parallel arranged of α, β, two output log-likelihood ratio information can be calculated every time, And the method in srsLTE can only calculate one；Use 8 fixed points compare with 16 fixed points the bit error rate of increase 0.3dB with In.

Accompanying drawing explanation

Fig. 1 is parallel Turbo decoding structure chart.

Fig. 2 is generator matrix [1 011；110 1] corresponding states position variation diagram.

Fig. 3 is α, β Vector operation flow chart.

Fig. 4 is output log-likelihood ratio Vector operation flow chart.

Detailed description of the invention

Below in conjunction with embodiment and Figure of description, the present invention is further illustrated.

Embodiment 1: a kind of parallel Turbo decoding method based on Intel CPU, in this embodiment, hardware platform uses Intel CPU Core i7-4790, supports AVX2 instruction set, is furnished with 16 256 senior vector registers, dominant frequency 3.6GHz； Turbo code generator matrix is [1 011；110 1], data acquisition is with 8 fixed-point representations.Code block 1 during dicode block parallel decoding Low 128, code block 2 is high 128, the most mutual, as shown in Figure 1 between code block.The Turbo code information of carrying is system letter Breath L_sys0, check information L_p0And L_p1, L_sys1By L_sys0Obtain through intertexture.It is described below the decoding process of a code block:

(1) code-aiming block carries out solution and cuts out, and obtains two string system informations L_sys0, L_sys1With two string check information L_p0, L_p1, described System information L_sys1By system information L_sys0Intertexture obtains, described L_sys0、L_p0Processed by the component decoder 0 in system, described L_sys1、L_p1Processed by the component decoder 1 in system；

(3) with branched measurement value that each sequential in each code block of log-likelihood ratio form calculus component decoder 0 is corresponding γ₁₁、γ₁₀；

According to bifurcation state metric calculation formula:

$\mathrm{\&gamma;}(s_i^k,s_j^{(k+1)})=0.5(L_{sys}^k+L_a^k)u_k+0.5\left(L_p^k{p}_k\right)$

L_sys, L_p, L_a, L_eIt is respectively system information, check information, prior information and external information；u_k, p_kRepresent system respectively System code and check code；s_i ^kRepresent that k walks i-th mode bit；

Obtain γ₁₁=0.5 (L_sys+L_p+L_a), γ₁₀=0.5 (L_sys-L_p+L_a), wherein L_aFor prior information, L_sysFor L_sys0 And L_sys1General symbol(s), L_pFor L_p0And L_p1General symbol(s)；

(4) in component decoder 0, in sequential k, θ is built^k+1, particularly as follows: list according to the convolutional code generator matrix of code block Branched measurement value γ₁₁ ^k、γ₁₀ ^kCorresponding sequence, as in figure 2 it is shown, by γ₁₁ ^k、γ₁₀ ^kBy described corresponding sequence construct vector γ^k； Vector theta^kInternal fixed-point number arrangement is β₇ ^m, β₆ ^m, β₅ ^m, β₄ ^m, β₃ ^m, β₂ ^m, β₁ ^m, β₀ ^m, α₇ ^k, α₆ ^k, α₅ ^k, α₄ ^k, α₃ ^k, α₂ ^k, α₁ ^k, α₀ ^k, Therefore corresponding from a high position to low level in this example γ is arranged as γ₁₁ ^m, γ₁₀ ^m, γ₁₀ ^m, γ₁₁ ^m, γ₁₁ ^m, γ₁₀ ^m, γ₁₀ ^m, γ₁₁ ^m, γ₁₁ ^k, γ₁₁ ^k, γ₁₀ ^k, γ₁₀ ^k, γ₁₀ ^k, γ₁₀ ^k, γ₁₁ ^k, γ₁₁ ^k, m is the reverse sequential of k, and m=N-k-1, N are system code length Degree；

According to forward state metric calculation formula calculating α:

${\mathrm{\&alpha;}}_j^{(k+1)}={\max }_{i\&Element;F}^{*}\{{\mathrm{\&alpha;}}_i^k+\mathrm{\&gamma;}(s_i^k,s_j^{(k+1)})\}$

Set F contain k step in s_j ^(k+1)2 relevant mode bits, α⁰=0 ,-∞ ,-∞ ,-∞ ,-∞ ,-∞ ,- ∞,-∞}；

According to backward state metric calculation formula calculating β:

${\mathrm{\&beta;}}_j^{(k-1)}={\max }_{i\&Element;B}^{*}\{{\mathrm{\&beta;}}_i^k+\mathrm{\&gamma;}(s_j^{(k-1)},s_i^k)\}$

Set B comprises and state s_j ^(k-1)The mode bit of relevant k step, β^N-1=0 ,-∞ ,-∞ ,-∞ ,-∞ ,-∞ ,- ∞,-∞}；

Single-instruction multiple-data stream (SIMD) instruction is used to carry out vector calculus, as it is shown on figure 3, i.e. θ^k+=θ^k+γ^k, θ^k-=θ^k-γ^k, Then change θ according to convolutional code generator matrix corresponding states position^k+, θ^k-Internal data rearranges；Seek θ^k+And θ^k-Corresponding The maximum of data is as the vector theta of next sequential^k+1；When using single-instruction multiple-data stream (SIMD) instruction to calculate, owing to 8 fixed The restriction of point, obtains θ^k+1After to be normalized, the α of i.e. internal 8 states^k+1、β^m-1All deduct 0 shape of this metric State value α₀ ^k+1、β₀ ^m-1, i.e. after normalization, internal arrangement is β₇ ^m-1-β₀ ^m-1, β₆ ^m-1-β₀ ^m-1, β₅ ^m-1-β₀ ^m-1, β₄ ^m-1-β₀ ^m-1, β₃ ^m-1- β₀ ^m-1, β₂ ^m-1-β₀ ^m-1, β₁ ^m-1-β₀ ^m-1, 0, α₇ ^k+1-α₀ ^k+1, α₆ ^k+1-α₀ ^k+1, α₅ ^k+1-α₀ ^k+1, α₄ ^k+1-α₀ ^k+1, α₃ ^k+1-α₀ ^k+1, α₂ ^k+1- α₀ ^k+1, α₁ ^k+1-α₀ ^k+1, 0；

Wherein, as k=0, θ⁰Portion's data are: α₀ ⁰=-127, β₀ ^N-1=-127, α_j≠0 ⁰=0, β_j≠0 ^N-1=0；θ^k+、θ^k- It is respectively positive and negative middle vector, θ for state^kProduced by a upper sequential, θ^kIn comprise eight forward-facing state degree of parallel code block Value α_j ^kWith eight reverse state metric values β_j ^m, j is number of state indexes；

In Vector operation involved by this step, each code block takies 128 within vector, involved Vector operation In, low 64 calculate forward state metric value α, and high 64 calculate reverse state metric value β, will not between high 64 and low 64 Data are had to exchange；

(5), in component decoder 0, when sequential k is less than the half of N, makes k=k+1, and return step (4), otherwise basis Below equation calculates output log-likelihood ratio L_o:

$L_o^k={\max }_{\{s^k,s^{(k+1)}\}\&Element;U^1}^{*}\{{\mathrm{\&alpha;}}_i^k+{\mathrm{\&beta;}}_j^{(k+1)}+\mathrm{\&gamma;}(s_i^k,s_j^{(k+1)})\}-{\max }_{\{s^k,s^{(k+1)}\}\&Element;U^{-1}}^{*}\{{\mathrm{\&alpha;}}_i^k+{\mathrm{\&beta;}}_j^{(k+1)}+\mathrm{\&gamma;}(s_i^k,s_j^{(k+1)})\}$

Set U¹And U^-1Contain and work as u_kMode bit when respectively 1 and-1；

As shown in Figure 4, it is loaded into vector theta^m, the α internal by it_j ^mAnd β_j ^kReversing of position, calculates L according to following formula^k+And L^k-:

L^k+=θ^m+θ^k+, L^k-=θ^m+θ^k-, wherein L^k+And L^k-The state of being respectively is to vow in the middle of positive and negative output log-likelihood ratio Amount；Described L^k+And L^K-Have respectively inside each vector parallel code block eight k sequential output log-likelihood ratio intermediate value and The output log-likelihood ratio intermediate value of eight m sequential；

Obtain L respectively^k+The maximum l of the output log-likelihood ratio intermediate value of middle k sequential and m sequential^k+And l^m+, L^k-During middle k The maximum l of the output log-likelihood ratio intermediate value of sequence and m sequential^k-And l^m-, then calculate l^k+-l^k-It is i.e. the output in k moment Log-likelihood ratio information, l^m+-l^m-It is i.e. the output log-likelihood ratio information in m moment, succinct for view, l in figure^k+、l^k-Use l table Show, and l^m+、l^m-Representing with x, state is labeled on the right side of block diagram；If k=N-1, perform next step operation, otherwise make k=k+1, and Return step (4)；

In Vector operation involved by this step, each code block takies 128 within vector, when low 64 calculating are current The output log-likelihood ratio of sequence k, high 64 output log-likelihood ratios calculating sequential N-k-1, except by vector theta^N-k-1Internal α_j ^N-k-1And β_j ^kOutside during reversing of position, high 64 bit data and low 64 bit data are exchanged, high 64 and low 64 in remaining Vector operation Between do not have data exchange；

(6) according to the processing method of component decoder 0 in described step (3) to (5) and flow process, in component decoder 1 Carry out component decoding, obtain exporting log-likelihood ratio information, then by formula L_e=L_o-L_sys-L_aObtain external information L_e, currently When decoder is decoder 0, by L_e0Interweave and obtain prior information L of decoder 1_a1, when current decoder is decoder 1, by L_e1 Deinterleave prior information L obtaining decoder 0_a0, wherein L_e0、L_a0For external information and the prior information of decoder 0, L_e1、L_a1 For external information and the prior information of decoder 1, L_eIt is L_e0、L_e1General symbol(s), L_aIt is L_a0、L_a1General symbol(s)；

(7) iteration indicator index accumulates once, and such as index < 6, then returns step (3), as index=6, and decoding Terminate.

This parallel Turbo decoding method major advantage based on Intel CPU is that handling capacity is high, and bit error rate performance Lose limited.As shown in Table 1, matched group is the Turbo solid size block that the order in srsLTE calculates α, β to the result of embodiment 1 Decoding scheme.The comparison other of bit-error rate penalty is to use double-precision floating points to carry out the bit error rate of Turbo decoding under MATLAB.

Form 1 solid size block and dicode block parallel Turbo decoding Performance comparision

Above-described embodiment is only the preferred embodiment of the present invention, it should be pointed out that: for the ordinary skill of the art For personnel, under the premise without departing from the principles of the invention, it is also possible to making some improvement and equivalent, these are to this Bright claim improve with equivalent after technical scheme, each fall within protection scope of the present invention.

Claims (5)

1. a parallel Turbo decoding method based on Intel CPU, it is characterised in that the method comprises the steps:

(1) in single-instruction multiple-data stream (SIMD) instructs, each code block distributes 128, sets the finger that parallel code block number is supported as CPU Make bit wide divided by 128；Iteration indicator index=0 is set；

(2) each code block carrying out solution respectively to cut out, each code block obtains two string system informations L_sys0, L_sys1With two string verification letters Breath L_p0, L_p1, described system information L_sys1By system information L_sys0Intertexture obtains, described L_sys0、L_p0Decoded by the component in system Device 0 processes, described L_sys1、L_p1Processed by the component decoder 1 in system；

(3) with branched measurement value γ that each sequential in each code block of log-likelihood ratio form calculus component decoder 0 is corresponding₁₁、 γ₁₀, i.e. γ₁₁=0.5 (L_sys+L_p+L_a), γ₁₀=0.5 (L_sys-L_p+L_a), wherein L_aFor prior information, L_sysFor L_sys0And L_sys1 General symbol(s), L_pFor L_p0And L_p1General symbol(s)；

(4) in component decoder 0, in sequential k, θ is built^k+1, particularly as follows: list according to the convolutional code generator matrix of each code block Bifurcation state metric γ₁₁ ^k、γ₁₀ ^kCorresponding sequence, by γ₁₁ ^k、γ₁₀ ^kBy described corresponding sequence construct vector γ^k；

Single-instruction multiple-data stream (SIMD) instruction is used to carry out vector calculus, i.e. θ^k+=θ^k+γ^k, θ^k-=θ^k-γ^k, then according to convolutional code Generator matrix corresponding states position changes θ^k+, θ^k-Internal data rearranges；Seek θ^k+And θ^k-The maximum of corresponding data is made Vector theta for next sequential^k+1, then it is normalized；

Wherein, θ^kProduced by a upper sequential, θ^kIn comprise eight forward state metric values α of parallel code block_j ^kWith eight reverse state Metric β_j ^m, j is number of state indexes, and N is system code length, as k=0, and θ⁰Internal data is: α₀ ⁰=-127, β₀ ^N-1=-127, α_j≠0 ⁰=0, β_j≠0 ^N-1=0；θ^k+、θ^k-It is respectively positive and negative middle vector, m=N-k-1 for state；

(5), in component decoder 0, when sequential k is less than the half of N, makes k=k+1, and return step (4), be otherwise loaded into vector θ^m, the α internal by it_j ^mAnd β_j ^kReversing of position, calculates L according to following formula^k+And L^k-:

L^k+=θ^m+θ^k+, L^k-=θ^m+θ^k-,

Wherein L^k+And L^K-The state of being respectively is vector in the middle of positive and negative output log-likelihood ratio；Described L^k+And L^k-In each vector Portion has output log-likelihood ratio intermediate value and the output log-likelihood ratio of eight m sequential of eight k sequential of parallel code block respectively Intermediate value；

Obtain L respectively^k+The maximum l of the output log-likelihood ratio intermediate value of middle k sequential and m sequential^k+And l^m+, L^k-Middle k sequential and The maximum l of the output log-likelihood ratio intermediate value of m sequential^k-And l^m-, then calculate l^k+-l^k-It it is i.e. the output logarithm in k moment Likelihood ratio information, l^m+-l^m-It is i.e. the output log-likelihood ratio information in m moment；If k=N-1, then enter step (6), otherwise make k =k+1, and return step (4)；

(6) according to the processing method of component decoder 0 in described step (3) to (5) and flow process, carry out in component decoder 1 Component decodes, and obtains exporting log-likelihood ratio information, then by formula L_e=L_o-L_sys-L_aObtain external information L_e, currently decode When device is decoder 0, by L_e0Interweave and obtain prior information L of decoder 1_a1, when current decoder is decoder 1, by L_e1Solve and hand over Knit prior information L obtaining decoder 0_a0, wherein L_e0、L_a0For external information and the prior information of decoder 0, L_e1、L_a1For translating The external information of code device 1 and prior information, L_eIt is L_e0、L_e1General symbol(s), L_aIt is L_a0、L_a1General symbol(s)；

(7) iteration indicator index accumulates once, and such as index < 6, then returns step (3), and as index=6, decoding terminates.

Parallel Turbo decoding method based on Intel CPU the most according to claim 1, it is characterised in that described step (1) in, cpu instruction collection bit wide is 256；Arranging parallel code block number is 2, and the computing in described step (3) to (6) uses AVX2 instruction set processes.

Parallel Turbo decoding method based on Intel CPU the most according to claim 1, it is characterised in that described step (1) in, cpu instruction collection bit wide is 512, and arranging parallel code block number is 4, and the computing in described step (3) to (6) uses AVX512 instruction set processes.

4. according to the parallel Turbo decoding method based on Intel CPU described in claim 1,2 or 3, it is characterised in that institute State step (4) to neutralize and (5) use single-instruction multiple-data stream (SIMD) instruction realize forward state metric value and reverse state metric value Parallel computation.

5. according to the parallel Turbo decoding method based on Intel CPU described in claim 1,2 or 3, it is characterised in that institute The normalized stated in step (4) is: θ^k+1The α of internal 8 states^k+1、β^m-1All deduct 0 state value α of this metric₀ ^k+1、 β₀ ^m-1。