CN109936376A - The method of byte-oriented operation cyclic code CRC16-CCITT verification - Google Patents
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Abstract
A kind of method that the present invention proposes byte-oriented operation cyclic code CRC16-CCITT verification, it is intended to which a binary number can only once be handled by solving conventional recycle check code CRC coding and decoding, be unsatisfactory for the needs of problems of high-speed digital communication system.The technical scheme is that: in FPGA, cyclic redundancy check generating function is write according to the multinomial of cyclic check code CRC16-CCITT and first phase；After receiving the transmission data of high-speed communication system, cyclic redundancy check generating function module writes cyclic redundancy check generating function according to the multinomial and first phase of cyclic check code CRC16 and CCITT, functional operation is calculated using simple exclusive or, the function is handled according to 8 channel parallel datas each time, corresponding data and its length are inputted at port according to the needs of different high-speed digital communication systems, corresponding cyclic redundancy check is generated, so as to real-time statistics CRC check result.
Description
Technical field
The present invention relates to debugging check code technical fields in data communication, are related to a kind of data transmission error-detecting function, press
The method of byte operation cyclic code CRC16-CCITT verification.
Background technique
In high-speed digital communication Transmission system, the transmission of signal inevitably will receive the interference of extraneous various factors, channel
Noise, intersymbol interference can all cause transmission signal be distorted, thus distorted signals generate mistake.In order to improve digital communication
Reliability and reduce the bit error rate, channel coding technology is usually used to carry out Error Control.It is transmitted in the data of communication system
In the process, due to the influence of complicated factors various in channel, so that the signal of transmission is interfered, cause the appearance of error code.
A variety of detection methods can be used in order to check whether received data has error code in recipient.Error control coding is current number
According to a kind of method of the raising data communication reliability generallyd use in transmission process, CRC is that one kind is applied in practical communication
Very extensive Error Control check code has very strong error detecing capability.During actual data transfer, sender is by the school CRC
It tests code and is attached to the tail portion of passed data flow and transmit together；Recipient removes the data received with same generator polynomial
Stream, if remainder is zero, can determine whether that received data are correct.Otherwise, it can determine whether that data generate in transmission process
Error code.Cyclic check code CRC is most common a kind of error check code in data communication field, it is characterized in that information field and
The length of check field can be arbitrarily selected.Due to having coding and interpretation method simple, the strong feature of error detecing capability is extensive
Applied in data communication system.CRC code be it is dimeric, preceding part is information code, the information for exactly needing to verify,
It is partially check code afterwards, if CRC code is total to long n bit, k bit of information code length is known as (n, k) code.Its coding rule
Be: 1, first by prime information code (kbit) move to left r (k+r=n) 2, with a generator polynomial g (x) (can also regard as two into
Number processed) with mould 2 formula above is removed, obtained remainder is exactly check code.
Generally there are two types of methods for the calculating of cyclic check code CRC: hardware and software is realized.Hardware based cyclic check code
CRC parallel algorithm has the certain methods being derived using look-up table and look-up table, but these methods are with the increasing of parallel number
Add and need the longer CRC remainder storage table of length, feasibility is small.Especially in high-speed digital communication system, not only transmit
Rate requirement is high, and certain communication systems also require to carry out CRC check to the data of random length.Although most of use hardware
Circuit completes CRC check in the chips, but the realization of traditional cyclic check code CRC coding and decoding is moved using linear feedback
Bit register can only once handle a binary number, be unsatisfactory for high-speed digital communication system although implementation method is simple
Demand.The method that the calculating of software realization generallys use look-up table generates cyclic redundancy check according to look-up table, but software is calculated
Method realize be sequence execute mode, for high rate data transmission require digital communication system in can not application software method
Realize CRC check.It is such as relatively difficult to achieve using the above method.
The realization of traditional cyclic check code CRC coding and decoding be using linear feedback shift register, though implementation method
It is so simple, but a binary number can only be once handled, it is unsatisfactory for the demand of high-speed digital communication system.Therefore, in order to full
The transmission demand of sufficient high-speed digital communication system needs a kind of byte-oriented operation (8 tunnels are parallel) CRC16 and CCITT to verify
FPGA implementation method simply directly calculates the school CRC according to the random length and CRC multinomial and its first phase of transmission data
Test code.
Summary of the invention
The present invention is not able to satisfy the high requirement of high-speed digital communication rate for existing cyclic check code CRC computing technique,
And the data of random length are carried out with the demand of CRC check, a kind of correctness that can guarantee data transmission and complete is provided
Property, and it is able to satisfy high-speed data communication requirement, the method for byte-oriented operation cyclic code CRC16-CCITT verification.To solve tradition
Cyclic check code CRC coding and decoding can only once handle a binary number, the demand for being unsatisfactory for high-speed digital communication system is asked
Topic.
Above-mentioned purpose of the invention can be reached by the following measures.A kind of byte-oriented operation cyclic code CRC16-
The method of CCITT verification, characterized by comprising the steps of: in FPGA, according to the more of cyclic check code CRC16-CCITT
Item formula and first phase write cyclic redundancy check generating function, construct cyclic redundancy check generating function module, are receiving high-speed communication system
After the transmission data of system, transmission data are divided into two-way, all the way according to update port input data and register value module
The value of input data and register is updated, cyclic redundancy check is generated, last CRC check result data and CRC16-CCITT is more
Xiang Shiyu first phase is sent into CRC16-CCITT check code generating function, judges whether that verification is completed according to data length control, no
Then, it executes a CRC16-CCITT verification and just feeds back a CRC check result to update port input data and register value
Module, after the completion of frame data verification, output CRC check result is real-time to CRC16-CCITT check results statistical module
CRC check is counted as a result, output data and check results；Another way transmission data give CRC generating function and generate CRC check knot
While fruit, transmission data are given to data Postponement module, the transmission data received are postponed, made by data Postponement module
It is perfectly aligned that the CRC check result data that module generates is completed in transmission data after delay and CRC check, is sent into CRC16-
The statistical module real-time statistics CRC check of CCITT check results is as a result, output data and check results.
The present invention compared with prior art, has the following beneficial effects:
The present invention writes CRC according to the random length of transmission data, the multinomial of cyclic check code CRC16 and CCITT and first phase
Check code generating function, the operation in function are calculated using simple exclusive or, and cyclic redundancy check is write in FPGA design and generates letter
Number, the function are handled according to 8 channel parallel datas each time, using 8 road parallel algorithms, simply directly calculate the school CRC
Code is tested, i.e., once can handle a byte data, handle the value for only needing to update input data and register each time, so that it may
To generate cyclic redundancy check；Then, inputted at port according to the needs of different high-speed digital communication systems corresponding data and
Its length, so that it may corresponding cyclic redundancy check is generated, so as to real-time statistics CRC check result.Compared to traditional primary
A binary number can be handled, the present invention can satisfy the high requirement of high-speed digital communication rate.
The present invention writes cyclic redundancy check generating function according to the multinomial and first phase of cyclic check code CRC16 and CCITT,
Operation in function is calculated using simple exclusive or, which is handled according to 8 channel parallel datas each time, i.e., once can be with
A byte data is handled, handles the value for only needing to update input data and register each time, so that it may generate CRC check
Code；Then, corresponding data and its length, Ke Yisheng are inputted at port according to the needs of different high-speed digital communication systems
At corresponding cyclic redundancy check, so as to real-time statistics CRC check result.The transmission data that can be adapted for random length are wanted
It asks, transmission data can be set, and according to different data conveying lengths, more new data and register value at port are calculated corresponding
Cyclic redundancy check, real-time statistics CRC check as a result, to guarantee data transmission correctness and integrality.
Present invention is suitably applied to transmit the CRC check of data in high-speed digital communication system, can be widely applied for each
The CRC check of kind data transmission set.
Detailed description of the invention
The present invention is further illustrated with implementation with reference to the accompanying drawing, but does not therefore limit the present invention to the example
Among range.
Fig. 1 is the flow chart of byte-oriented operation cyclic code CRC16-CCITT verification of the present invention.
Specific embodiment
Refering to fig. 1.According to the present invention, it in FPGA, is compiled according to the multinomial of cyclic check code CRC16-CCITT and first phase
Cyclic redundancy check generating function is write, cyclic redundancy check generating function module is constructed, in the transmission data for receiving high-speed communication system
Later, transmission data are divided into two-way, input data is updated according to update port input data and register value module all the way
With the value of register, cyclic redundancy check is generated, last CRC check result data and CRC16-CCITT multinomial are sent with first phase
Enter CRC16-CCITT check code generating function, judges whether that verification is completed according to data length control；Otherwise, it executes primary
CRC16-CCITT verification just feeds back a CRC check result to update port input data and register value module, Zhi Daoyi
After the completion of frame data verification, output CRC check result to CRC16-CCITT check results statistical module real-time statistics CRC check
As a result, output data and check results；It, will while another way transmission data give CRC generating function generation CRC check result
Transmission data give data Postponement module, and data Postponement module postpones the transmission data received, the biography after making delay
Transmission of data and the CRC check result data that module generation is completed in CRC check are perfectly aligned, are sent into CRC16-CCITT check results
The CRC check of statistical module real-time statistics is as a result, output data and check results.
Cyclic redundancy check generating function module updates port input data according to transmission data, according to last CRC check knot
Fruit data update register value, execute a CRC16-CCITT verification and just feed back a CRC check as a result, until a frame number
It is completed according to verification, exports CRC check result.The each frame data length of the transmission data of high-speed digital communication system be it is fixed,
Therefore, delay length is fixed, and is to maintain changeless.
CRC16-CCITT check results module is raw by comparing check bit in transmission data and CRC16-CCITT check code
At the CRC check in function as a result, verification is correct, then the frame data preferably bag data, and the success of CRC check state is reported,
Otherwise it is rascal, CRC check state is reported to fail；Finally, CRC check statistical result and transmission data are sent out, work as next frame
It when data are transferred to next, repeats the above process, starts to execute CRC check.
After receiving the transmission data of high-speed communication system, cyclic redundancy check generating function module is according to data content
Input port data and register value are updated, CRC check result is generated by CRC16-CCITT check code generating function；Together
When communications system transmission data are postponed, according to a frame data length control verification terminate, the transmission data after delay with
The CRC check result data that module generation is completed in CRC check is perfectly aligned, passes through CRC16-CCITT check results statistical module
The two is subjected to check results statistics and reports verification state, output data and its result to export statistical result.
In FPGA, cyclic redundancy check generating function module is verified using 8 tunnel Parallel CRC 16 and CCITT, is marked according to CRC16
8 road parallel algorithms of quasi-polynomial x16+x15+x2+1 construction, it is raw to construct 8 tunnel Parallel CRC 16-CCITT check codes according to demand
At function, 8 road parallel algorithms of the CRC16 check code generating function according to CRC16 standard polynomial x16+x15+x2+1 construction, wound
Build CRC16 check code generating function.Cyclic redundancy check generating function module calls function when carrying out CRC16 verification
NextCRC16_DATA8 (Data, CRC_reg), wherein Data is the input data of 8 bit wides, and CRC_reg is register value.
When input port updates a byte data, cyclic redundancy check generating function module calls CRC generating function CRC16=
Perhaps CCITT=nextCCITT_DATA8 generates CRC16 CCITT check results to nextCRC16_DATA8, according to input
Data length controls whether the frame check is completed, and gives CRC check result to CRC16 or CCITT verification knot if completing
Fruit statistical module；Otherwise, CRC check is fed back as a result, continuing to call CRC generating function.
Cyclic redundancy check generating function module inputs the data Data and register value CRC_reg of 8 bit wides, according to CRC
The first phase and CRC check multinomial x16+x15+x2+1 or x16+x12+x5+1, i.e., corresponding generating function of verification calculate
Corresponding check results update the defeated of first phase and generating function if a transmission frame number according to being not over, proceeds as described above
Enter data, until test ending.
High-speed digital communication Transmission system is after a frame data are transmitted, the frame data test ending, and Transmission system will
Transmission data after delay are counted with inspection result, if check results are correct, transmission frame number evidence is preferably wrapped；It is no
Then, transmission frame number evidence is rascal, and check results are reported to high-speed digital communication Transmission system monitoring software.
Wherein, the specific algorithm of CRC16 check code generating function module and CCITT check code generating function module designs such as
Under: D:=Data；
C:=CRC_reg；
NewCRC (0) :=D (0) xor D (1) xor D (2) xor D (3) xor D (4) xor D (5) xor D (6) xor D (7)
xor C(8)xor C(9)xor C(10)xor C(11)xor C(12)xor C(13)xor C(14)xor C(15)；
NewCRC (1) :=D (1) xor D (2) xor D (3) xor D (4) xor D (5) xor D (6) xor D (7) xor C (9)
xor C(10)xor C(11)xor C(12)xor C(13)xor C(14)xor C(15)；
NewCRC (2) :=D (2) xor D (3) xor D (4) xor D (5) xor D (6) xor D (7) xorD (0) xor D (1)
xor D(2)xor D(3)xor D(4)xor D(5)xor D(6)xor D(7)xor C(10)xor C(11)xor C(12)
xor C(13)xor C(14)xor C(15)xor C(8)xor C(9)xor C(10)xor C(11)xor C(12)xor C
(13)xor C(14)xor C(15)；
NewCRC (3) :=D (3) xor D (4) xor D (5) xor D (6) xor D (7) xorD (1) xor D (2) xor D (3)
xor D(4)xor D(5)xor D(6)xor D(7)xor C(11)xor C(12)xor C(13)xor C(14)xor C(15)
xor C(9)xor C(10)xor C(11)xor C(12)xor C(13)xor C(14)xor C(15)；
NewCRC (4) :=D (4) xor D (5) xor D (6) xor D (7) xorD (2) xor D (3) xor D (4) xor D (5)
xor D(6)xor D(7)xor C(12)xor C(13)xor C(14)xor C(15)xor C(10)xor C(11)xor C
(12)xor C(13)xor C(14)xor C(15)；
NewCRC (5) :=D (3) xor D (4) xor D (5) xor D (6) xor D (7) xorD (5) xor D (6) xor D (7)
xor C(11)xor C(12)xor C(13)xor C(14)xor C(15)xor C(13)xor C(14)xor C(15)；
NewCRC (6) :=D (4) xor D (5) xor D (6) xor D (7) xorD (6) xor D (7) xor C (14) xor C (15)
xor C(12)xor C(13)xor C(14)xor C(15)；
NewCRC (7) :=D (5) xor D (6) xor D (7) xor D (7) xorC (13) xor C (14) xor C (15) xor C
(15)；
NewCRC (8) :=D (6) xor D (7) xor C (0) xor C (14) xor C (15)；
NewCRC (9) :=D (7) xor C (1) xor C (15)；
NewCRC (10) :=C (2)；
NewCRC (11) :=C (3)；
NewCRC (12) :=C (4)；
NewCRC (13) :=C (5)；
NewCRC (14) :=C (6)；
NewCRC (15) :=D (0) xor D (1) xor D (2) xor D (3) D (4) xor D (5) xorD (6) xor D (7) xor C
(7)xor C(8)xor C(9)xor C(10)xor C(11)xor C(12)xor C(13)xor C(14)xor C(15)；
The VHDL of function nextCCITT_DATA8 realizes that code is as follows:
D:=Data；
C:=CRC_reg；
NewCRC (0) :=D (4) xor D (0) xor C (8) xor C (12)；
NewCRC (1) :=D (5) xor D (1) xor C (9) xor C (13)；
NewCRC (2) :=D (6) xor D (2) xor C (10) xor C (14)；
NewCRC (3) :=D (7) xor D (3) xor C (11) xor C (15)；
NewCRC (4) :=D (4) xor C (12)；
NewCRC (5) :=D (5) xor D (4) xor D (0) xor C (8) xor C (12) xor C (13)；
NewCRC (6) :=D (6) xor D (5) xor D (1) xor C (9) xor C (13) xor C (14)；
NewCRC (7) :=D (7) xor D (6) xor D (2) xor C (10) xor C (14) xor C (15)；
NewCRC (8) :=D (7) xor D (3) xor D (0) xor C (11) xor C (15)；
NewCRC (9) :=D (4) xor C (1) xor C (12)；
NewCRC (10) :=D (5) xor C (2) xor C (13)；
NewCRC (11) :=D (6) xor C (3) xor C (14)；
NewCRC (12) :=D (7) xor D (4) xor D (0) xor C (4) xor C (8) xor C (12) xor C (15)；
NewCRC (13) :=D (5) xor D (1) xor C (5) xor C (9) xor C (13)；
NewCRC (14) :=D (6) xor D (2) xor C (6) xor C (10) xor C (14)；
NewCRC (15) :=D (7) xor D (3) xor C (7) xor C (11) xor C (15)；
Above in conjunction with attached drawing to the present invention have been described in detail, it is to be noted that being described in examples detailed above
Preferred embodiment only of the invention, is not intended to restrict the invention, and for those skilled in the art, the present invention can
There are a various modifications and variations, for example process flow and processing sequence can be changed in conjunction with concrete implementation, can select and set identification
Different parameters in the process realize technical method of the invention.All within the spirits and principles of the present invention, made any
Modification, equivalent replacement, improvement etc., should be included within scope of the presently claimed invention.
Claims (10)
1. a kind of method of byte-oriented operation cyclic code CRC16-CCITT verification, characterized by comprising the steps of: in FPGA
In, cyclic redundancy check generating function is write according to the multinomial of cyclic check code CRC16-CCITT and first phase, constructs cyclic redundancy check
Transmission data are divided into two-way, all the way according to more after receiving the transmission data of high-speed communication system by generating function module
New port input data and register value module update the value of input data and register, generate cyclic redundancy check, will be last
CRC check result data and CRC16-CCITT multinomial and first phase are sent into CRC16-CCITT check code generating function, according to number
Judge whether that verification is completed according to length control, otherwise, executes a CRC16-CCITT verification and just feed back a CRC check result
To port input data and register value module is updated, after the completion of frame data verification, output CRC check result is arrived
The statistical module real-time statistics CRC check of CRC16-CCITT check results is as a result, output data and check results；Another way transmission
Data give CRC generating function and generate CRC check as a result, giving transmission data to data Postponement module simultaneously, and data postpone mould
Block postpones the transmission data received, and the transmission data and CRC check after making delay complete the CRC check that module generates
Result data is perfectly aligned, is sent into the statistical module real-time statistics CRC check of CRC16-CCITT check results as a result, output data
And check results.
2. the method for byte-oriented operation cyclic code CRC16-CCITT verification as described in claim 1, it is characterised in that: the school CRC
It tests yard generating function module and updates port input data according to transmission data, posted according to the update of last CRC check result data
Storage numerical value executes CRC16-CCITT verification and just feeds back a CRC check as a result, completing until a frame data verify, defeated
CRC check result out.
3. the method for byte-oriented operation cyclic code CRC16-CCITT verification as described in claim 1, it is characterised in that: high speed
The each frame data length of the transmission data of digital communication system be it is fixed, delay length is fixed, and is to maintain solid
It is fixed constant.
4. the method for byte-oriented operation cyclic code CRC16-CCITT verification as described in claim 1, it is characterised in that:
CRC16-CCITT check results module is by comparing in check bit and CRC16-CCITT check code generating function in transmission data
CRC check as a result, verification is correct, then otherwise the frame data preferably bag data, and report the success of CRC check state is bad
Packet reports CRC check state to fail；Finally, CRC check statistical result and transmission data are sent out, when next frame data transmit
It when arrival, repeats the above process, starts to execute CRC check.
5. the method for byte-oriented operation cyclic code CRC16-CCITT verification as described in claim 1, it is characterised in that: connecing
After the transmission data for receiving high-speed communication system, cyclic redundancy check generating function module updates input port according to data content
Data and register value generate CRC check result by CRC16-CCITT check code generating function；Simultaneously by communication system
Transmission data are postponed, and are terminated according to frame data length control verification, mould is completed in the transmission data after delay and CRC check
The CRC check result data that block generates is perfectly aligned, is verified the two by CRC16-CCITT check results statistical module
As a result it counts, to export statistical result, reports verification state, output data and its result.
6. the method for byte-oriented operation cyclic code CRC16-CCITT verification as described in claim 1, it is characterised in that:
In FPGA, cyclic redundancy check generating function module is verified using 8 tunnel Parallel CRC 16 and CCITT, according to CRC16 standard polynomial
8 road parallel algorithms of x16+x15+x2+1 construction, construct 8 tunnel Parallel CRC 16-CCITT check code generating functions according to demand.
7. the method for byte-oriented operation cyclic code CRC16-CCITT verification as claimed in claim 6, it is characterised in that: CRC16
8 road parallel algorithms of the check code generating function according to CRC16 standard polynomial x16+x15+x2+1 construction, creation CRC16 verification
Code generating function.
8. the method for byte-oriented operation cyclic code CRC16-CCITT verification as claimed in claim 7, it is characterised in that: the school CRC
Yard generating function module is tested when carrying out CRC16 verification, is called function nextCRC16_DATA8 (Data, CRC_reg), wherein
Data is the input data of 8 bit wides, and CRC_reg is register value.
9. the method for byte-oriented operation cyclic code CRC16-CCITT verification as described in claim 1, it is characterised in that: high speed
When digital communication system input port updates a byte data, cyclic redundancy check generating function module calls CRC generating function
Perhaps CCITT=nextCCITT_DATA8 generates CRC16 CCITT check results to CRC16=nextCRC16_DATA8,
Control whether the frame check is completed according to input data length, if complete if by CRC check result give CRC16 or
CCITT check results statistical module；Otherwise, CRC check is fed back as a result, continuing to call CRC generating function.
10. the method for byte-oriented operation cyclic code CRC16-CCITT verification as described in claim 1, it is characterised in that: CRC
Check code generating function module inputs the data Data and register value CRC_reg of 8 bit wides, according to the first phase of CRC check
With CRC check multinomial x16+x15+x2+1 or x16+x12+x5+1, i.e., corresponding generating function calculates corresponding verification
As a result, updating the input data of first phase and generating function, directly if a transmission frame number is proceeded as described above according to being not over
To test ending.
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Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111752747A (en) * | 2020-06-09 | 2020-10-09 | 山东华翼微电子技术股份有限公司 | Memory security verification method for enhancing error detection capability |
| CN112036117A (en) * | 2020-08-28 | 2020-12-04 | 西安微电子技术研究所 | CRC check control system suitable for multiple bit width parallel input data |
| CN114389755A (en) * | 2022-01-12 | 2022-04-22 | 上海黑眸智能科技有限责任公司 | Data verification method, device, storage medium and terminal |
| CN114726383A (en) * | 2022-04-12 | 2022-07-08 | 北京理工大学 | High-throughput parallel cyclic redundancy check method based on CRC-16 |
| CN116107800A (en) * | 2023-04-12 | 2023-05-12 | 浙江恒业电子股份有限公司 | Verification code generation method, data recovery method, medium and electronic equipment |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20070016842A1 (en) * | 2005-07-13 | 2007-01-18 | Microchip Technology Incorporated | Method and apparatus for configuring a cyclic redundancy check (CRC) generation circuit to perform CRC on a data stream |
| US20070089028A1 (en) * | 2005-09-21 | 2007-04-19 | Semiconductor Energy Laboratory Co., Ltd. | Cyclic redundancy check circuit and semiconductor device having the cyclic redundancy check circuit |
| CN105653390A (en) * | 2014-11-10 | 2016-06-08 | 无锡华润矽科微电子有限公司 | SoC system verification method |
| CN107154836A (en) * | 2017-06-28 | 2017-09-12 | 西安空间无线电技术研究所 | A kind of cardiopulmonary bypass in beating heart redundancy CRC check method based on FPGA |
| CN107229533A (en) * | 2017-05-27 | 2017-10-03 | 郑州云海信息技术有限公司 | A kind of method of SmartRack system hardwares CRC |
-
2019
- 2019-01-31 CN CN201910094540.3A patent/CN109936376B/en active Active
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20070016842A1 (en) * | 2005-07-13 | 2007-01-18 | Microchip Technology Incorporated | Method and apparatus for configuring a cyclic redundancy check (CRC) generation circuit to perform CRC on a data stream |
| US20070089028A1 (en) * | 2005-09-21 | 2007-04-19 | Semiconductor Energy Laboratory Co., Ltd. | Cyclic redundancy check circuit and semiconductor device having the cyclic redundancy check circuit |
| CN105653390A (en) * | 2014-11-10 | 2016-06-08 | 无锡华润矽科微电子有限公司 | SoC system verification method |
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