CN105653390A - SoC system verification method - Google Patents
SoC system verification method Download PDFInfo
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- CN105653390A CN105653390A CN201410625088.6A CN201410625088A CN105653390A CN 105653390 A CN105653390 A CN 105653390A CN 201410625088 A CN201410625088 A CN 201410625088A CN 105653390 A CN105653390 A CN 105653390A
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Abstract
The invention provides a SoC system verification method characterized by comprising the following steps: 1, a one-chip microcomputer mcu inputs to-be verified data into a 32bit data input dwell vessel through a data bus; 2, a CRC parallel calculating module extracts the data from the input dwell vessel; 3, the CRC parallel calculating module carries out CRC16 verification calculation according to CRC_CCITT standards; 4, the parallel calculating module inputs the verification result into a verification result dwell vessel; 5, the verification result dwell vessel returns the previous calculating result to a computing module for next calculation; 6, the verification result dwell vessel returns the result to the mcu data bus. The SoC system verification method is faster in speed, higher in stability, large in calculating speed improvable space, and less in used resources.
Description
Technical field
Inventive design digital communication technology field, especially designs a kind of verification method of SoC system.
Background technology
In data transmission system, due to the instability of communication link, the interference of external environment, the failure and other reasons of instrument, the data that receiving end receives usually have certainMistake, theseMistakeIf signal normally adopted, unexpected consequence can be produced, some time even can cause huge loss. Therefore, introduce checking system to be necessary very much. Verification mode conventional in SoC system has a lot, simply such as parity checking, but for a large amount of data, under the conditions of demand that high precision inspection is wrong, conventional verification mode is compared in CRC verification. CRC verify full name cyclic redundancy check (CRC) algorithm (CyclicRedundancyCheck), referred to as CRC, be a kind of check results can be iterated until net result export verification mode. CRC checking algorithm with have high-performance, simple, be easy to the advantages such as realization and be widely used in communication system.
Under normal circumstances, what CRC adopted is serial computing mode, namely checking data inputs by turn in units of bit and verifies, every bit once calculates, pending data has all calculated and has namely obtained check results, but in today that SoC resource is flourish, mcu processing power is constantly in rising, data bit width ceaselessly develops from 8 to 16 32, storing device also constantly expands simultaneously, the calculated amount carried out required for data verification is also in continuous rising, and the timing requirements that SoC system is strict, the speed calculated is proposed very high requirement again simultaneously. Therefore, the CRC parallel computing being applied to SoC system is very necessary. In SoC system, also having a kind of mode to be the function increasing CRC verification in mcu software, data verify in mcu, but this kind of method still has certain shortcoming, and such as mcu processes the consumption of resource, the difficulty etc. of computing power lifting. In existing SoC verification mode, parity checking is too simple, can only be applied to the verification of small amount of data, and the error rate verified is relatively high, the accuracy rate that serial CRC verifies has had guarantee, but counting yield is lower, if it is intended to improve the clock requency that can only improve verification module.
For above shortcoming, the CRC16 verification method based on CRC_CCITT that inventive design inputs for 32 bit parallels, CRC16 verification has sufficiently high verification accuracy rate, and when not having repetition rate, CRC16 100% can detect out odd numberMistakeBit causesMistake, and length be less than 16 suddenMistake, and length be greater than 16 suddenMistakeIn, only new numerical value differs with former numerical value just to be divided exactly by the 16 of CRC_CCITT formula and just can not be detected, and this probability is very low. Computationally, the present invention adopts parallel computation mode, it is possible within one-period, and 32 bit parallel input data are carried out verify calculation, timing requirements harsh in SoC system is provided and supports significantly by undoubtedly, is verification mode very useful in 32 mcu systems. Whole functions of the present invention are realized by hardware circuit, compare software CRC mode, and the mode of the present invention has speed faster, higher stability, and the space that computing velocity can promote is also very big, and meanwhile, the resource taken is also less.
Summary of the invention
It is an object of the invention to overcome the shortcoming of above-mentioned prior art, it provides have speed faster, higher stability, the space that computing velocity can promote is also very big, and the verification method of the also less a kind of SoC system of the resource taken.
In order to realize above-mentioned purpose, the present invention realizes by the following technical solutions: a kind of verification method of SoC system, it is characterised in that, comprise the following steps:
1) micro-chip mcu is input to 32 bit data input registers by the data that data bus will verify;
2) CRC parallel computation module takes out data from input register;
3) CRC parallel computation module carries out the CRC16 verify calculation based on CRC_CCITT standard;
4) check results is input to check results register by parallel computation module;
5) calculation result that check results register feedback is last calculates to calculating module next time;
6) result is returned to mcu data bus by check results register. .
Further, described CRC16 verify calculation formula is: CRC_CCITT=X16+X12+X5+1.
Adopt the verification method of a kind of SoC system of the present invention, there is following useful effect:
(1), the inventive design CRC16 verification method based on CRC_CCITT that 32 bit parallels are inputted, CRC16 verification has sufficiently high verification accuracy rate, and when not having repetition rate, CRC16 100% can detect out odd numberMistakeBit causesMistake, and length be less than 16 suddenMistake, and length be greater than 16 suddenMistakeIn, only new numerical value differs with former numerical value just to be divided exactly by the 16 of CRC_CCITT formula and just can not be detected, and this probability is very low.
(2), computationally, the present invention adopts parallel computation mode, it is possible within one-period, and 32 bit parallel input data are carried out verify calculation, timing requirements harsh in SoC system is provided and supports significantly by undoubtedly, is verification mode very useful in 32 mcu systems.
(3), whole functions of the present invention realize by hardware circuit, compare software CRC mode, the mode of the present invention has speed faster, higher stability, and the space that computing velocity can promote is also very big, and meanwhile, the resource taken is also less.
Accompanying drawing explanation
Fig. 1For the frame of the calculation formula serial computing that communicatesFigure��
Fig. 2For CRC checking system frameFigure��
Embodiment
In order to more clearly describe thisInventionTechnology contents, conduct further description below in conjunction with specific embodiment.
Refer toFig. 1ExtremelyFig. 2Shown in, that the CRC design of the present invention adopts is CRC_CCITT, and it is the communication verification formula usually adopted in the world. Its verification formula is as follows:
CRC_CCITT=X16+X12+X5+1
The frame of its serial computingFigure is such as Fig. 1Shown in.
The iterative formula of its corresponding bit is as follows:
Wherein i represents that j represents that jth secondary data inputs corresponding to i-th that CRC exports, and represents the data of jth time verification input, represents the multinomial coefficient of in CRC_CCITT i-th. Data data_in inputs from a high position successively to low position, it can be seen that the time required for serial computing is directly proportional to the length of data.
According to parallel computation, according to serial iteration formula, we can calculate the calculation formula of parallel check:
If the maintenance result that 32 bit data of input are 16 registers of d, CRC verification is r, then the calculation formula calculating check results in one-period is as follows:
r[0]=r[3]^r[4]^r[6]^r[10]^r[11]^r[12]^d[0]^d[4]^d[8]^d[11]^d[12]^d[19]^d[20]^d[22]^d[26]^d[27]^d[28]
r[1]=r[4]^r[5]^r[7]^r[11]^r[12]^r[13]^d[1]^d[5]^d[9]^d[12]^d[13]^d[20]^d[21]^d[23]^d[27]^d[28]^d[29]
r[2]=r[5]^r[6]^r[8]^r[12]^r[13]^r[14]^d[2]^d[6]^d[10]^d[13]^d[14]^d[21]^d[22]^d[24]^d[28]^d[29]^d[30]
r[3]=r[6]^r[7]^r[9]^r[13]^r[14]^r[15]^d[3]^d[7]^d[11]^d[14]^d[15]^d[22]^d[23]^d[25]^d[29]^d[30]^d[31]
r[4]=r[0]^r[7]^r[8]^r[10]^r[14]^r[15]^d[4]^d[8]^d[12]^d[15]^d[16]^d[23]^d[24]^d[26]^d[30]^d[31]
r[5]=r[0]^r[1]^r[3]^r[4]^r[6]^r[8]^r[9]^r[10]^r[12]^r[15]^d[0]^d[4]^d[5]^d[8]^d[9]^d[11]^d[12]^d[13]^d[16]^d[17]
^d[19]^d[20]^d[22]^d[24]^d[25]^d[26]^d[28]^d[31]
r[6]=r[1]^r[2]^r[4]^r[5]^r[7]^r[9]^r[10]^r[11]^r[13]^d[1]^d[5]^d[6]^d[9]^d[10]^d[12]^d[13]^d[14]^d[17]^d[18]
^d[20]^d[21]^d[23]^d[25]^d[26]^d[27]^d[29]
r[7]=r[2]^r[3]^r[5]^r[6]^r[8]^r[10]^r[11]^r[12]^r[14]^d[2]^d[6]^d[7]^d[10]^d[11]^d[13]^d[14]^d[15]^d[18]^d[19]
^d[21]^d[22]^d[24]^d[26]^d[27]^d[28]^d[30]
r[8]=r[0]^r[3]^r[4]^r[6]^r[7]^r[9]^r[11]^r[12]^r[13]^r[15]^d[3]^d[7]^d[8]^d[11]^d[12]^d[14]^d[15]^d[16]^d[19]
^d[20]^d[22]^d[23]^d[25]^d[27]^d[28]^d[29]^d[31]
r[9]=r[0]^r[1]^r[4]^r[5]^r[7]^r[8]^r[10]^r[12]^r[13]^r[14]^d[4]^d[8]^d[9]^d[12]^d[13]^d[15]^d[16]^d[17]^d[20]
^d[21]^d[23]^d[24]^d[26]^d[28]^d[29]^d[30]
r[10]=r[0]^r[1]^r[2]^r[5]^r[6]^r[8]^r[9]^r[11]^r[13]^r[14]^r[15]^d[5]^d[9]^d[10]^d[13]^d[14]^d[16]^d[17]^d[18]
^d[21]^d[22]^d[24]^d[25]^d[27]^d[29]^d[30]^d[31]
r[11]=r[1]^r[2]^r[3]^r[6]^r[7]^r[9]^r[10]^r[12]^r[14]^r[15]^d[6]^d[10]^d[11]^d[14]^d[15]^d[17]^d[18]^d[19]^d[22]
^d[23]^d[25]^d[26]^d[28]^d[30]^d[31]
r[12]=r[0]^r[2]^r[6]^r[7]^r[8]^r[12]^r[13]^r[15]^d[0]^d[4]^d[7]^d[8]^d[15]^d[16]^d[18]^d[22]^d[23]^d[24]^d[28]
^d[29]^d[31]
r[13]=r[0]^r[1]^r[3]^r[7]^r[8]^r[9]^r[13]^r[14]^d[1]^d[5]^d[8]^d[9]^d[16]^d[17]^d[19]^d[23]^d[24]^d[25]^d[29]
^d[30]
r[14]=r[1]^r[2]^r[4]^r[8]^r[9]^r[10]^r[14]^r[15]^d[2]^d[6]^d[9]^d[10]^d[17]^d[18]^d[20]^d[24]^d[25]^d[26]^d[30]
^d[31]
r[15]=r[2]^r[3]^r[5]^r[9]^r[10]^r[11]^r[15]^d[3]^d[7]^d[10]^d[11]^d[18]^d[19]^d[21]^d[25]^d[26]^d[27]^d[31]
Wherein, ^ represents different or computing. Input data are 32 valid data.
In the design of the present invention, CRC check results can keep, as long as namely mcu does not send clear instruction, then check results register keeps the result of last verification and this result is used for calculating next time, so can support the continuous verification of any n 32 bit data in theory, the data that actual meaning is the integral multiple that can be 32 to any length verify.
Its system frameFigure is such as Fig. 2Shown in.
Such as Fig. 2Shown in, mcu is input to 32 bit data input registers by the data that data bus will verify, after data have write, CRC parallel computation module is taken out data from input register and is calculated, then check results is input to check results register, whole calculating completes in one-period, if now mcu needs to check check results, check results register can be carried out read request. Check results register is used for preserving the result of verification, when needing feedback, check results is supplied to simultaneously calculate module be used on verify calculation once.
The verification preserved in check results register is exported, mcu can be read by data interface and then be contrasted with the check code in data source, or check code is input to verification module carry out once verification (check code is 16, the zero padding of low position forms 32 bit data sources), the check results now obtained is 0.
CRC16 verification has sufficiently high verification accuracy rate, and when not having repetition rate, CRC16 100% can detect out odd numberMistakeBit causesMistake, and length be less than 16 suddenMistake, and length be greater than 16 suddenMistakeIn, only new numerical value differs with former numerical value just to be divided exactly by the 16 of CRC_CCITT formula and just can not be detected, and this probability is very low.
Computationally, the present invention adopts parallel computation mode, it is possible within one-period, and 32 bit parallel input data are carried out verify calculation, timing requirements harsh in SoC system is provided and supports significantly by undoubtedly, is verification mode very useful in 32 mcu systems.
Comparing software CRC mode, the mode that the present invention realizes verification by hardware circuit has speed faster, higher stability, and the space that computing velocity can promote is also very big, and meanwhile, the resource taken is also less.
Claims (2)
1. the verification method of a SoC system, it is characterised in that, comprise the following steps:
1) micro-chip mcu is input to 32 bit data input registers by the data that data bus will verify;
2) CRC parallel computation module takes out data from input register;
3) CRC parallel computation module carries out the CRC16 verify calculation based on CRC_CCITT standard;
4) check results is input to check results register by parallel computation module;
5) calculation result that check results register feedback is last calculates to calculating module next time;
6) result is returned to mcu data bus by check results register.
2. the verification method of a kind of SoC system as claimed in claim 1, it is characterised in that: described CRC16 verify calculation formula is: CRC_CCITT=X16+X12+X5+1.
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109936376A (en) * | 2019-01-31 | 2019-06-25 | 西南电子技术研究所（中国电子科技集团公司第十研究所） | The method of byte-oriented operation cyclic code CRC16-CCITT verification |
| CN113608917A (en) * | 2021-06-23 | 2021-11-05 | 苏州浪潮智能科技有限公司 | Method and device for calculating CRC value of any data |
| CN114124401A (en) * | 2021-11-02 | 2022-03-01 | 佛吉亚歌乐电子(丰城)有限公司 | Data authentication method, device, equipment and storage medium |
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| CN102891685A (en) * | 2012-09-18 | 2013-01-23 | 国核自仪系统工程有限公司 | Parallel cyclic redundancy check (CRC) operation circuit based on field programmable gate array (FPGA) |
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Patent Citations (4)
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| US6560746B1 (en) * | 1998-08-26 | 2003-05-06 | Telefonaktiebolaget Lm Ericsson | Parallel CRC generation circuit for generating a CRC code |
| CN101783688A (en) * | 2010-03-05 | 2010-07-21 | 苏州和迈微电子技术有限公司 | Design method of 64-bit parallel multi-mode CRC code generation circuit |
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Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109936376A (en) * | 2019-01-31 | 2019-06-25 | 西南电子技术研究所（中国电子科技集团公司第十研究所） | The method of byte-oriented operation cyclic code CRC16-CCITT verification |
| CN113608917A (en) * | 2021-06-23 | 2021-11-05 | 苏州浪潮智能科技有限公司 | Method and device for calculating CRC value of any data |
| CN113608917B (en) * | 2021-06-23 | 2023-07-14 | 苏州浪潮智能科技有限公司 | Method and device for calculating CRC value of arbitrary data |
| CN114124401A (en) * | 2021-11-02 | 2022-03-01 | 佛吉亚歌乐电子(丰城)有限公司 | Data authentication method, device, equipment and storage medium |
| CN114124401B (en) * | 2021-11-02 | 2023-11-17 | 佛吉亚歌乐电子(丰城)有限公司 | Data authentication method, device, equipment and storage medium |
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Application publication date: 20160608 |