CN112036117A - CRC check control system suitable for multiple bit width parallel input data - Google Patents
CRC check control system suitable for multiple bit width parallel input data Download PDFInfo
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Abstract
The invention discloses a CRC check control system suitable for multi-bit-width parallel input data.A AHB interface unit realizes the analysis of an AHB access protocol; after CRC calculation is carried out on the data source by the CRC calculation unit, a CRC value is output; the CRC preset value unit is used for comparing with the result of CRC calculation; the comparison unit is used for comparing the check value with a preset value; the counting unit is used for counting the overtime of the verification process and counting the data source and generating the conditions required by the interrupt generating unit; the interrupt generating unit realizes the generation of external interrupt of the control system. By adopting a mechanism for selecting the optimal calculation polynomial based on the verification data source, a data parallel verification mechanism, an interrupt control processing mechanism and the like, the quick parallel verification of different polynomials for different data sources is realized, meanwhile, the working reliability of a control system is improved through the interrupt processing mechanism, and the problem of data reliability in an embedded system and an SoC system is solved.
Description
Technical Field
The invention belongs to the technical field of embedded systems and integrated circuit design, and particularly relates to a CRC check control system suitable for multiple bit width parallel input data.
Background
The high-security and high-reliability SoC has extremely high requirements on reliability, which means that very high requirements are put on the reliability of data in the storage system. Generally, a storage system is implemented by common storage devices such as an SRAM and a FLASH, and the devices are affected by internal system transmission or external uncertain factors during data storage, so that the problems of inconsistency between stored data and original data and the like often occur. In order to solve the above problems, a Cyclic Redundancy Check (CRC) mechanism is usually introduced in the design to Check data in the storage system to ensure the reliability of the data. Therefore, it is important to design a CRC check control system, especially a high-pass control system.
Currently, the mainstream CRC check control structures all use a single computational polynomial, and do not fully consider the characteristics of data (such as bit width and data amount) and the operational reliability of the controller, so that the control structures have poor versatility, poor check performance and poor operational reliability. Therefore, a verification control system that can verify a data source with the shortest time overhead and select multiple calculation polynomials to improve the universality is urgently needed, and a robust and reliable guarantee mechanism that allows the verification system to work stably and reliably is also needed. At present, the existing conversion structures can not consider the problems, the defects of the corresponding technologies are reflected on different levels, and a method for well solving the problems is not available after relevant documents are searched.
Disclosure of Invention
The technical problem to be solved by the present invention is to provide a CRC check control system suitable for parallel input data with multiple bit widths, aiming at the characteristic that reliability requirements of large quantities of data in SoC storage system are high, by adopting a mechanism for selecting an optimal calculation polynomial based on a check data source, a data parallel check mechanism, an interrupt control processing mechanism, etc., fast parallel check of different polynomials for different data sources can be realized, and meanwhile, by an interrupt processing mechanism, the reliability of the control system can be improved, and the problem of data reliability in embedded system and SoC system can be solved.
The invention adopts the following technical scheme:
a CRC check control system suitable for multiple bit width parallel input data comprises an AHB interface unit,
one end of the AHB interface unit is connected with an AHB bus, the other end of the AHB interface unit is respectively connected with input ends of a CRC calculation unit and a CRC preset value unit, output ends of the CRC calculation unit and the CRC preset value unit are connected with an interrupt generation unit through a comparison unit, the interrupt generation unit is connected with a counting unit, a checked data source is analyzed through the AHB interface unit, data are input into the CRC calculation unit, calculation is achieved through a CRC calculation polynomial, a CRC value is obtained, the calculation value is compared with the preset value of the CRC preset value unit through the comparison unit, a result is obtained, the interrupt generation unit outputs the result, and CRC control of the data is achieved finally.
Specifically, the CRC computation polynomial includes 8, 16, 32, and 64-bit wide computation polynomials.
Further, the 8, 16, 32, and 64-bit wide calculation polynomials are specifically:
f_crc8(x)＝x8+x2+x+1
f_crc16(x)＝x16+x15+x2+x+1
f_crc32(x)＝x32+x26+x23+x22+x16+x12+x11+x10+x8+x7+x5+x4+x2+x+1
f_crc64(x)＝x64+x4+x3+x+1。
specifically, the AHB interface unit implements analysis of an AHB access protocol, and is used for processing an AHB interface signal;
CRC calculation unit, which selects the best calculation polynomial from the polynomial selection structure, and outputs the CRC value after CRC calculation for the data source;
CRC preset value unit, which writes in the correct check result of original data source in advance by AHB interface for comparing with the result of CRC calculation;
the comparison unit is used for comparing the check value with a preset value and outputting a comparison result;
the counting unit is used for realizing overtime counting on the checking process and counting the data source and generating the conditions required by the interrupt generating unit;
and the interrupt generating unit is used for judging the interrupt condition and realizing the generation of external interrupt of the control system.
Compared with the prior art, the invention has at least the following beneficial effects:
the CRC check control system applicable to the parallel input data with various bit widths can realize the rapid parallel check of the data with different bit widths, and the universality of the check system is improved by adopting a mechanism of selecting an optimal calculation polynomial based on a check data source. According to the bit width characteristic of the data source, the corresponding calculation polynomial can be flexibly selected, so that the verification system can be used for verifying various data sources, and the verification efficiency is effectively improved by adopting a data parallel verification mechanism. The verification of mass data can be realized rapidly, and the time overhead is reduced greatly; and an interrupt control processing mechanism is adopted, so that the safety and reliability of the work of the control system are ensured. The interrupt processing mechanism can process and report abnormal conditions in the verification system in time, effectively avoids the 'crash' condition of the control system, and greatly improves the working reliability of the control system.
Furthermore, the CRC calculation polynomial comprises 8, 16, 32 and 64 bit data bit width calculation polynomials, and the corresponding calculation polynomial can be flexibly selected according to the bit width characteristics of the data source, so that the checking system can be used for checking various data sources, and the universality of the checking system is improved.
Further, 8, 16, 32 and 64 bit data bit width calculation polynomials specifically give a mathematical algorithm of the calculation polynomials, and realize rapid parallel verification of data with different bit widths.
Further, the AHB interface unit realizes the analysis of an AHB access protocol and is used for processing an AHB interface signal; CRC calculation unit, which selects the best calculation polynomial from the polynomial selection structure, and outputs the CRC value after CRC calculation for the data source; CRC preset value unit, which writes in the correct check result of original data source in advance by AHB interface for comparing with the result of CRC calculation; the comparison unit is used for comparing the check value with a preset value and outputting a comparison result; the counting unit is used for realizing overtime counting on the checking process and counting the data source and generating the conditions required by the interrupt generating unit; and the interrupt generating unit is used for judging the interrupt condition and realizing the generation of external interrupt of the control system. The units are organically interconnected and work coordinately, so that the rapid parallel verification of different polynomials for different data sources is realized, and meanwhile, the working reliability of the control system can be improved through an interrupt processing mechanism.
In conclusion, the invention has the advantages of flexible and simple structure, high working efficiency, suitability for the verification of various data with different bit widths, easy transplantation and expansion, strong universality and high reliability.
The technical solution of the present invention is further described in detail by the accompanying drawings and embodiments.
Drawings
FIG. 1 is a CRC check control system of the present invention;
fig. 2 shows a CRC calculation polynomial shift register implementation.
Wherein: an AHB interface unit; a CRC calculation unit; a CRC preset value unit; 400. a comparison unit; 500. a counting unit; 600. an interrupt generation unit.
Detailed Description
The invention provides a CRC check control system suitable for multiple bit width parallel input data, which adopts a mechanism for selecting an optimal calculation polynomial based on a check data source, a data parallel check mechanism and an interrupt control processing mechanism, realizes the rapid parallel check of different polynomials for different data sources, and improves the reliability of data in an embedded system and an SoC system.
Referring to fig. 1, the CRC check control system for multiple bit-width parallel input data according to the present invention can implement the check on the data in the SoC memory system; including AHB interface unit 100, CRC calculation unit 200, CRC preset value unit 300, comparison unit 400, count unit 500, and interrupt generation unit 600.
One end of the AHB interface unit 100 is connected with the AHB bus, the other end is connected with the input ends of the CRC calculation unit 200 and the CRC preset value unit 300, the output ends of the CRC calculation unit 200 and the CRC preset value unit 300 are connected with the interrupt generation unit 600 through the comparison unit 400, the interrupt generation unit 600 is connected with the counting unit 500, the checked data source is analyzed through the AHB interface unit 100, the data is input to the CRC calculation unit 200, calculation is achieved through the optimal calculation polynomial, a CRC value is obtained, the calculated value is compared with the preset value of the CRC preset value unit 300 through the comparison unit 400, a comparison result is generated, result output is achieved through the interrupt generation unit 600, and finally CRC check control of the data is achieved.
The AHB interface unit 100 is used for analyzing an AHB access protocol and processing an AHB interface signal;
a CRC calculation unit 200 for selecting the optimal calculation polynomial from the polynomial selection structure, performing CRC calculation on the data source, and outputting a CRC value;
CRC preset value unit 300, which is written in the correct check result of the original data source in advance by the AHB interface for comparing with the result of CRC calculation;
the comparison unit 400 is used for comparing the check value with a preset value and outputting a comparison result;
the counting unit 500 is used for counting the overtime in the checking process and counting the data source and generating the conditions required by the interrupt generating unit;
the interrupt generating unit 600 discriminates the interrupt condition, so as to realize the generation of the external interrupt of the control system and ensure the reliability of the operation of the control system.
8. The CRC polynomial corresponding to 16, 32, 64 bits realizes four kinds of polynomial with different bit widths, and selects the corresponding optimal polynomial for CRC check according to the characteristics of the checked data to generate a CRC value, specifically:
f_crc8(x)＝x8+x2+x+1
f_crc16(x)＝x16+x15+x2+x+1
f_crc32(x)＝x32+x26+x23+x22+x16+x12+x11+x10+x8+x7+x5+x4+x2+x+1
f_crc64(x)＝x64+x4+x3+x+1
referring to fig. 2, the CRC polynomial is implemented by a shift register structure, and four kinds of polynomials with different bit widths are implemented by a multi-stage shift register structure, so as to achieve the purpose of hardware to implement CRC calculation quickly.
CRC8 shift register structures, interconnected by 8 registers and 3 exclusive or gates. In the CRC8 shift register structure, the 7 th bit, the 1 st bit, and the 0 th bit are exclusive-ored in accordance with the CRC8 polynomial.
CRC16 shift register structures, interconnected by 16 registers and 4 exclusive or gates. In the CRC16 shift register structure, the 15 th, 14 th, 1 st, and 0 th bits are exclusive-ored in accordance with the CRC16 polynomial.
CRC32 shift register structures, interconnected by 32 registers and 14 exclusive or gates. In the CRC32 shift register structure, corresponding to the CRC32 polynomial, the xor operation is performed on the 31 st, 25 th, 22 th, 21 st, 15 th, 11 th, 10 th, 9 th, 7 th, 6 th, 4 th, 3 rd, 1 st, and 0 th bits.
CRC64 shift register structures, interconnected by 64 registers and 4 exclusive or gates. In the CRC64 shift register structure, the 63 rd bit, 3 rd bit, 2 nd bit, and 0 th bit are exclusive-ored according to the CRC64 polynomial.
In order to make the objects, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are some, but not all, embodiments of the present invention. The components of the embodiments of the present invention generally described and illustrated in the figures herein may be arranged and designed in a wide variety of different configurations. Thus, the following detailed description of the embodiments of the present invention, presented in the figures, is not intended to limit the scope of the invention, as claimed, but is merely representative of selected embodiments of the invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
The invention realizes the analysis of the AHB access protocol through the AHB interface unit 100; the CRC calculation unit 200 selects a CRC calculation polynomial, and performs CRC check on the original data to generate a CRC check value; the CRC preset value unit 300 stores the correct check result to be compared; the comparison unit 400 compares the check value with the preset value and outputs a comparison result; the counting unit 500 is used for counting the overtime of the verification process and counting the data sources and generating the conditions required by the interrupt generating unit; the interrupt generation unit 600 implements generation of control system interrupts.
The invention is successfully applied to a high-performance SoC chip based on an ARM Cortex-R4 processor core. The check calculation of the storage space data such as FLASH, SRAM and the like in the SoC chip is realized, the optimal characteristic polynomial can be selected for CRC check according to the characteristics of the storage space data, the whole calculation efficiency is high, and the reliability and the safety of the data in the chip are ensured.
According to the CRC check control structure in fig. 1, the CRC check control system applicable to multiple bit widths of parallel input data according to the present invention can be obtained by using the implementation structure of the computational polynomial shift register in fig. 2.
In summary, the CRC check control system for multiple bit-width parallel input data of the present invention can not only realize the check on the data source with the shortest time overhead, but also select multiple computational polynomials to improve the versatility, and further has a robust reliability guarantee mechanism and a stable and reliable operation mechanism. The system has simple structure, is easy to realize, and can be transplanted to an integrated circuit system with the requirement on data verification.
The above-mentioned contents are only for illustrating the technical idea of the present invention, and the protection scope of the present invention is not limited thereby, and any modification made on the basis of the technical idea of the present invention falls within the protection scope of the claims of the present invention.
Claims (4)
1. A CRC check control system for multiple bit wide parallel input data, comprising an AHB interface unit (100),
one end of an AHB interface unit (100) is connected with an AHB bus, the other end of the AHB interface unit is respectively connected with input ends of a CRC calculation unit (200) and a CRC preset value unit (300), output ends of the CRC calculation unit (200) and the CRC preset value unit (300) are respectively connected with an interrupt generation unit (600) through a comparison unit (400), the interrupt generation unit (600) is connected with a counting unit (500), a checked data source is analyzed through the AHB interface unit (100), data are input into the CRC calculation unit (200), calculation is achieved through a CRC calculation polynomial, a CRC value is obtained, a result is obtained through comparison of the calculation value and the preset value of the CRC preset value unit (300) through the comparison unit (400), the result is output through the interrupt generation unit (600), and CRC control of the data is finally achieved.
2. The CRC check control system for multiple bit-wide parallel input data according to claim 1, wherein the CRC computation polynomials comprise 8, 16, 32 and 64 bit-wide computation polynomials.
3. The CRC check control system for multiple bit-wide parallel input data according to claim 2, wherein the 8, 16, 32 and 64 bit-wide calculation polynomials are specifically:
f_crc8(x)＝x8+x2+x+1
f_crc16(x)＝x16+x15+x2+x+1
f_crc32(x)＝x32+x26+x23+x22+x16+x12+x11+x10+x8+x7+x5+x4+x2+x+1
f_crc64(x)＝x64+x4+x3+x+1。
4. the CRC check control system for multiple bit widths of parallel input data according to claim 1, wherein the AHB interface unit (100) implements an analysis of an AHB access protocol for processing AHB interface signals;
a CRC calculation unit (200) for selecting the optimal calculation polynomial from the polynomial selection structure, performing CRC calculation on the data source, and outputting a CRC value;
CRC preset value unit (300), which writes the correct check result of the original data source in advance by AHB interface for comparing with the result of CRC calculation;
the comparison unit (400) is used for comparing the check value with a preset value and outputting a comparison result;
the counting unit (500) is used for realizing overtime counting on the checking process and counting on the data source and generating the conditions required by the interrupt generating unit;
and the interrupt generating unit (600) is used for judging the interrupt condition and realizing the generation of external interrupt of the control system.
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