CN115904798A - Error correction and detection method and system of memory and controller - Google Patents
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Abstract
The invention discloses an error correction and detection method, a system and a controller of a memory, wherein the method comprises the following steps: carrying out error detection code EDC encoding and error detection and correction ECC encoding on user data in sequence to obtain first encoded data; writing the user data and the first encoded data to a memory; and carrying out ECC (error correction code) check and EDC (electronic data correction) check on the data stored in the memory in sequence to obtain an error correction and detection result. The method can ensure single-bit error correction and simultaneously has better error checking capability of multi-bit errors, thereby ensuring normal use of the memory, having stronger protection capability no matter the memory is in transient or permanent failure and avoiding system breakdown.
Description
Technical Field
The invention relates to the technical field of microcontrollers, in particular to a method, a system and a controller for error correction and detection of a memory.
Background
In a general-purpose Microcontroller (MCU), an erasable non-volatile memory such as Flash memory (Flash memory) is the most common instruction memory, which is an electronically erasable read-only memory, allowing multiple erasures in operation. In actual use, the Flash memory array may gradually lose stored data due to device aging, noise interference, ray interference, and the like, causing transient errors or permanent errors of array content data, and further causing a Central Processing Unit (CPU) execution error, which may cause a system crash effect. Therefore, it becomes very important to protect the data correctness and timely check for errors in the array.
In order to ensure the reliability of Flash memory data storage, an instruction Error correction (ECC) check circuit is added into a Flash controller in the related technology, and original data and ECC check bits are burnt and written into a Flash memory array together when data are burnt and written; and performing ECC (error correction code) check on the original data again during reading, and comparing the ECC check bits with the read ECC check bits, so that the functions of single-bit error correction and double-bit error detection are realized.
However, in order to achieve a very strong error detection capability, the above verification scheme needs to occupy more array space of Flash, and the hardware overhead is very large; by adopting the code with very weak error detection capability, although the code occupies a smaller array space of Flash, the risk of system crash is greatly increased.
Disclosure of Invention
The present invention is directed to solving, at least to some extent, one of the technical problems in the related art. Therefore, an object of the present invention is to provide a method, a system and a controller for error correction and detection of a memory, so as to effectively improve the capability of checking the correctness of data in the memory, and facilitate reducing the risk of system crash.
In a first aspect, the present invention provides a method for error correction and detection of a memory, where the method includes: carrying out error detection code EDC encoding and error detection and correction ECC encoding on user data in sequence to obtain first encoded data; writing the user data and the first encoded data to a memory; and carrying out ECC (error correction code) check and EDC (EDC) check on the data stored in the memory in sequence to obtain an error correction and detection result.
In addition, the error correction and detection method of the memory according to the above embodiment of the present invention may further have the following additional technical features:
according to an embodiment of the present invention, the user data includes target data and an address of the target data.
According to an embodiment of the present invention, the successively performing error detection code EDC encoding and error check and correction ECC encoding on the user data to obtain first encoded data includes: performing EDC encoding on the target data and the address thereof to obtain second encoded data; and carrying out ECC coding on the target data and the second coded data to obtain the first coded data.
According to an embodiment of the invention, said writing said user data and said first encoded data to a memory comprises: writing target data in the user data and the first coded data into a memory; the method further comprises the following steps: and writing the second coded data into a memory.
According to an embodiment of the present invention, the sequentially performing ECC check and EDC check on the data stored in the memory to obtain an error correction and detection result includes: ECC decoding the second coded data in the memory, and repairing the target data and the first coded data by using an ECC decoding result; and performing EDC (electronic data detection) check on the repaired target data by using the repaired first coding data to obtain the error correction and detection result.
According to an embodiment of the present invention, before obtaining the error correction and detection result, the method further includes: segmenting the repaired target data to obtain a plurality of sub-segment data; respectively carrying out ECC coding on each subsegment data to obtain corresponding third coded data; and performing ECC check on the corresponding subsegment data by using the third coded data.
According to an embodiment of the invention, the method further comprises: judging whether the data stored in the memory has errors or not according to the error correction and detection result; if the error exists, sending out interrupt information.
According to an embodiment of the invention, the method further comprises: confirming that a write request is received before error detection code EDC encoding and error check and correction ECC encoding are carried out on user data in sequence; and confirming that the read request is received before the ECC check and the EDC check are carried out on the data stored in the memory successively.
In a second aspect, the present invention provides a controller, which includes a storage medium, a memory, and a computer program stored on the storage medium, and when the computer program is executed by the processor, the method for error correction and detection of the memory of the first aspect is implemented.
In a third aspect, the present invention provides an error correction and detection system for a memory, including: a memory and a controller according to an embodiment of the second aspect described above.
The error correction and detection method, the error correction and detection system and the controller of the memory of the embodiment of the invention adopt a mixed coding mode of EDC and ECC to carry out data error correction and detection, can effectively improve the checking capability of data correctness in the memory, and are beneficial to reducing the risk of system crash.
Drawings
FIG. 1 is a flow chart of a method for error correction and detection of a memory according to an embodiment of the present invention;
FIG. 2 is a flow chart of a method for error correction and detection of a memory according to a specific example of the present invention;
FIG. 3 is a block diagram of a controller according to an embodiment of the present invention;
FIG. 4 is a block diagram of an error correction and detection system for a memory according to an embodiment of the present invention.
Detailed Description
Reference will now be made in detail to embodiments of the present invention, examples of which are illustrated in the accompanying drawings, wherein like or similar reference numerals refer to the same or similar elements or elements having the same or similar function throughout. The embodiments described below with reference to the drawings are illustrative and intended to be illustrative of the invention and are not to be construed as limiting the invention.
The error correction and detection method, system and controller of the memory according to the embodiment of the present invention are described below with reference to the accompanying drawings.
Fig. 1 is a flowchart of an error correction and detection method for a memory according to an embodiment of the present invention.
In embodiments of the invention, the memory may be an erasable non-volatile memory, such as Flash memory.
As shown in fig. 1, the error correction and detection method of the memory includes:
s1, carrying out error detection code EDC coding and error detection and correction ECC coding on user data in sequence to obtain first coded data.
Specifically, the error detection code EDC encoding and error check and correction ECC encoding are successively performed on the user data to obtain first encoded data, and the method includes: EDC encoding is carried out on the user data to obtain second encoding data, and then ECC encoding is carried out on the second encoding data to obtain first encoding data.
Wherein, the user Data (which may also be referred to as Data information to be written) may include target Data (which may be referred to as Data to be written, such as 128b Data shown in fig. 2) and an Address (such as 20b Address shown in fig. 2) where the target Data is located, where b represents a bit; the EDC code may use Cyclic Redundancy Check (CRC) coding.
And S2, writing the user data and the first coded data into a memory.
Wherein the user data and the first encoded data can be written into the memory through a debugger JTAG or SWD or the like. Alternatively, only target data among the user data may be written when the user data is written to the memory.
And S3, sequentially carrying out ECC (error correction code) check and EDC (EDC) check on the data stored in the memory to obtain an error correction and detection result.
The data stored in the memory at least comprises the user data and the first encoding data.
Specifically, the performing ECC check and EDC check on the data stored in the memory sequentially includes: and sequentially performing ECC (error correction code) check and EDC (extractive digital coding) check on the user data and the first coded data in the memory, if the first coded data is subjected to ECC decoding, simultaneously performing EDC coding on the user data, further repairing the EDC coded data by using a decoding result, and then performing EDC check on the user data by using the repaired EDC coded data.
Taking a memory as an example, when a CPU receives user data, a Flash controller writes the user data (which can include target data and the address thereof) into a control logic of the Flash controller through a debugger such as JTAG/SWD, performs EDC coding and ECC coding on the user data in sequence, and then writes the user data and the coded data into a Flash array together through the control of the debugger JTAG/SWD. After programming is completed, the CPU starts to execute the program, and performs ECC (error correction code) check and EDC (electronic data correction) check on the data stored in the memory in sequence to obtain an error correction and detection result, so that whether the data in the memory is abnormal or not can be determined according to the error correction and detection result. When ECC check is carried out, if errors exist in the Flash array, corresponding data can be repaired or corrected.
In this embodiment, ECC encoding, typically implemented by an extended hamming code or Hsiao code, enables 1-bit error correction and warning and 2-bit error warning of the original data. The use of ECC is an effective guarantee for memory storage safety, when the memory begins to lose data due to device aging or interference of rays, electromagnetism, noise and the like, the occurrence probability of single-bit errors is far greater than that of multi-bit errors, but if the memory is not processed, the occurrence probability of the multi-bit errors is obviously improved along with the deepening of aging degree or continuous noise interference, and further software execution errors are caused. For multi-bit errors, ECC encoding alone risks that no errors are checked.
Therefore, the invention adopts mixed coding of ECC and EDC, firstly uses ECC to correct the error in the memory array of the memory, thereby prolonging the service life of the memory. And then performing EDC check to judge whether the memory array is successfully recovered, and if the memory array is successfully recovered, the memory can still be used. Therefore, the error checking method can ensure that single bit error correction is carried out and simultaneously has better error checking capability of multi-bit errors, thereby ensuring the normal use of the memory, ensuring that the memory has stronger protection capability no matter the memory is in transient state or permanent failure and avoiding system crash.
It should be noted that, because the number of ECC error correction bits is limited, if EDC check is performed first and then ECC error correction is performed, there is no way to further check the ECC error correction result.
In some embodiments, the execution of step S1 above may be triggered when a write request is received; the execution of step S3 above may be triggered when a read request is received.
It should be noted that the data written into the memory may be stored in an array form, or stored in a storage array of the memory, and when the reading in step S3 is performed, the array data may be read in rows, and the content of each row of data includes the user data + the CRC check code (i.e., the second encoded data) + the ECC check code (i.e., the first encoded data).
In some embodiments, successively performing error detection code EDC encoding and error check and correction ECC encoding on the user data to obtain first encoded data, includes: performing EDC encoding on the target data and the address thereof to obtain second encoded data; and carrying out ECC coding on the target data and the second coded data to obtain first coded data.
For example, as shown in fig. 2, EDC encoding is performed on user Data, including target Data (128 b Data) and the Address (20 b Address) thereof, to obtain second encoded Data (4-8 b CRC); the target Data (128 b Data) and the second encoded Data (4-8 b CRC) are ECC-encoded to obtain first encoded Data (9 b ECC).
In this embodiment, referring to FIG. 2, while the target Data (128 b Data) and the first encoded Data (4-8 b CRC) are written to the memory, the second encoded Data (9 b ECC) can also be written to the memory.
In some embodiments, the performing ECC check and EDC check on the data stored in the memory sequentially to obtain the error correction and detection result includes: ECC decoding is carried out on the second coded data in the memory, and the target data and the first coded data are repaired by utilizing the ECC decoding result; and performing EDC (electronic data interchange) check on the repaired target data by using the repaired first encoding data to obtain an error correction and detection result.
In particular, ECC encoding is achieved by adding redundancy to the information transmitted using an algorithm, the redundant bits possibly being a complex function of many original information bits. The original information may or may not literally appear in the encoded output; codes that contain unmodified inputs in the output are systematic, while those that contain modified inputs are non-systematic. ECC coding takes the example of redundant 3-time coding, i.e., each data bit is transmitted 3 times, and is referred to as a (3, 1) repetition code. Through a noisy channel, the receiver may see 8 versions of the output, as follows:
000 0 (error-free)
001 0 (error)
010 0 (error)
100 0 (error)
111 1 (error-free)
110 1 (error)
101 1 (error)
011 1 (error)
For the errors described above, correction by "majority voting" or "democratic voting" may be allowed. The ECC error correction capability is as follows: data repair can be achieved by this error correction capability, with at most 1-bit triplet errors, or, with at most 2-bit triplets omitted (not shown in the 8 versions above). It should be noted that such triple modular redundancy described above is a relatively inefficient ECC, and a more efficient ECC would typically examine the last tens or even hundreds of previously received bits to determine how to decode the current small number of bits (typically in groups of 2 to 8 bits).
EDC checking process: a CRC-enabled device computes a short, fixed-length binary sequence, called a check value or CRC, for each block of data to be transmitted or stored and appends it to the data, forming a codeword. When a codeword is received or read, the device either compares its check value with the newly calculated check value from the data block or equivalently performs a CRC on the entire codeword and compares the resulting check value with the expected residual constant. If the CRC values do not match, the block contains a data error. The device may take corrective action such as re-reading the block or requesting that the block be sent again. Otherwise, the data is assumed to be error free.
Based on this, performing EDC check (i.e. CRC check in fig. 2) on the repaired target data by using the repaired first encoded data means performing EDC encoding on the repaired target data to obtain a CRC check value, and comparing the check value with the repaired first encoded data. If the two are the same, i.e. no exception is checked, the target Data (128 b Data) can be obtained. Correspondingly, if the check is abnormal, the data in the memory is abnormal, the interrupt information can be sent out, the system reading operation is interrupted in time, and the corrective action is taken.
Due to the above EDC check, although the check is free of anomalies, i.e. the data is assumed to be error-free, it may still contain undetected errors (although with a small probability), which is inherent to the nature of the error check. To this end, in some embodiments, before obtaining the error correction and detection result, the method for error correction and detection of a memory further includes: segmenting the repaired target data to obtain a plurality of sub-segment data; respectively carrying out ECC coding on each subsegment data to obtain corresponding third coded data; and performing ECC check on the corresponding subsegment data by using the third coded data.
For example, referring to fig. 2, 128b Data may be divided into two segments, resulting in two 64b Data subsegment Data. And carrying out ECC (error correction code) coding on the 64b Data to obtain third coded Data (8 b ECC), and further carrying out ECC checking on the corresponding subsegment Data by using the third coded Data (8 b ECC), so that the checking accuracy can be improved, and the accuracy of reading the Data to the CPU (Central processing Unit) is ensured.
The error correction and detection method of the memory provided by the embodiment of the invention adopts a mixed coding mode of EDC and ECC to carry out data error correction and detection, has strong data protection capability, can effectively find error points in read data and send out interrupt information, is convenient for a system to timely make corresponding response, and avoids risks if safety measures are taken. And the occupied array space is small, and only more than ten redundant bits are used.
Based on the error correction and detection method of the memory of the above embodiment, the invention provides a controller.
Fig. 3 is a block diagram of a controller according to an embodiment of the present invention.
As shown in fig. 3, the controller 300 includes: a processor 301 and a storage medium 303. Wherein the processor 301 is coupled to the storage medium 303, such as via a bus 302. Optionally, the controller 300 may also include a transceiver 304. It should be noted that the transceiver 304 is not limited to one in practical applications, and the structure of the controller 300 is not limited to the embodiment of the present invention.
The processor 301 may be a CPU (central processing unit), a general-purpose processor, a DSP (digital signal processor), an ASIC (application specific integrated circuit), an FPGA (field programmable gate array) or other programmable logic device, a transistor logic device, a hardware component, or any combination thereof. Which may implement or execute the various illustrative logical blocks, modules, and circuits described in connection with the disclosure. The processor 301 may also be a combination of computing functions, e.g., comprising one or more microprocessors, a combination of a DSP and a microprocessor, or the like.
The storage medium 303 is used for storing a computer program corresponding to the error correction and detection method of the memory of the above-described embodiment of the present invention, and the computer program is controlled by the processor 301 to execute. The processor 301 is configured to execute a computer program stored in the storage medium 303 to implement the content shown in the foregoing method embodiments.
The invention also provides an error correction and detection system of the memory.
Fig. 4 is a block diagram of an error correction and detection system of a memory according to an embodiment of the present invention.
As shown in fig. 4, the error correction and detection system 400 of the memory includes: a memory 100 and a controller 300 of the above-described embodiment.
In summary, the error correction and detection method, the system and the controller of the memory in the embodiments of the present invention perform error correction and detection on data by using a mixed coding mode of EDC and ECC, so as to effectively improve the checking capability of data correctness in the memory, and facilitate reducing the risk of system crash.
Although embodiments of the present invention have been shown and described above, it is understood that the above embodiments are exemplary and should not be construed as limiting the present invention, and that variations, modifications, substitutions and alterations can be made to the above embodiments by those of ordinary skill in the art within the scope of the present invention.
Claims (10)
1. A method for error correction and detection of a memory, the method comprising:
carrying out error detection code EDC encoding and error detection and correction ECC encoding on user data in sequence to obtain first encoded data;
writing the user data and the first encoded data to a memory;
and carrying out ECC (error correction code) check and EDC (EDC) check on the data stored in the memory in sequence to obtain an error correction and detection result.
2. The method of claim 1, wherein the user data includes target data and an address of the target data.
3. The method of claim 2, wherein the sequentially performing error detection code EDC encoding and error check and correction ECC encoding on the user data to obtain first encoded data comprises:
performing EDC encoding on the target data and the address thereof to obtain second encoded data;
and carrying out ECC coding on the target data and the second coded data to obtain the first coded data.
4. The method of claim 3, wherein writing the user data and the first encoded data to the memory comprises:
writing target data in the user data and the first encoding data into a memory;
the method further comprises the following steps:
and writing the second coded data into a memory.
5. The method of claim 4, wherein the performing an ECC check and an EDC check on the data stored in the memory sequentially to obtain an error correction and detection result comprises:
ECC decoding the second encoding data in the memory, and repairing the target data and the first encoding data by using an ECC decoding result;
and performing EDC check on the repaired target data by using the repaired first encoding data to obtain the error correction and detection result.
6. The method of claim 5, wherein before obtaining the error detection and error correction result, the method further comprises:
segmenting the repaired target data to obtain a plurality of sub-segment data;
respectively carrying out ECC coding on each subsegment data to obtain corresponding third coded data;
and performing ECC check on the corresponding subsegment data by using the third encoding data.
7. The method of claim 1, wherein the method further comprises:
judging whether the data stored in the memory has errors according to the error correction and detection result;
if the error exists, sending out interrupt information.
8. The method of claim 1, wherein the method further comprises:
confirming that a write request is received before error detection code EDC encoding and error checking and correcting ECC encoding are carried out on user data in sequence;
and confirming that the read request is received before the ECC check and the EDC check are carried out on the data stored in the memory successively.
9. A controller comprising a storage medium, a processor and a computer program stored on the storage medium, wherein the computer program, when executed by the processor, implements a method of error correction and detection for a memory according to any of claims 1-8.
10. An error correction and detection system for a memory, comprising: a memory and a controller according to claim 9.
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