CN101114888A

CN101114888A - Method for producing cycle error examination code

Info

Publication number: CN101114888A
Application number: CNA2007101371808A
Authority: CN
Inventors: 秦鹏; 张斌
Original assignee: Via Technologies Inc
Current assignee: Via Technologies Inc
Priority date: 2007-07-30
Filing date: 2007-07-30
Publication date: 2008-01-30
Anticipated expiration: 2027-07-30
Also published as: CN101114888B

Abstract

The invention discloses a generation method of a cyclic error check code, which is finished by a first cyclic error check code generator and a second cyclic error check code generator. Firstly, a responding signal is transmitted to the first cyclic error check code generator and the second cyclic error check code generator. Then a buffer released signal to the second cyclic error check code generator. And then according to the responding signal, a first cyclic error check code corresponding to a first code is generated and according to the buffer released signal and the responding signal, the second cyclic error check code corresponding to a second signal is generated. Finally the first cyclic error check code is input into a first operation unit to compute a third cyclic error check code corresponding to a third signal, wherein, at least one bit difference exists between the first signal and the third signal.

Description

The production method of cycle error examination code

Technical field

The present invention relates to a kind of production method of cycle error examination code, particularly relate to a kind of production method that reduces the cycle error examination code of cycle error examination code generator quantity.

Background technology

Fig. 1 is the schematic diagram of an existing cycle error examination code production method.In HyperTransport 3.0 high speed transmission systems, because have five kinds of different ignore instructions (No Operation, NOP), at corresponding cycle error examination code (the cyclic redundancy check that produces these NOP, CRC) time, must utilize five different cycle error examination code generators to produce cycle error examination code.In Fig. 1, NOP is sent in a CRC generator 11, the 2nd CRC generator 12, the 3rd CRC generator 13, the 4th CRC generator 14 and the 5th CRC generator 15, produces different cycle error examination codes, and is sent to multiplexer 16.Then, by selecting signal Select, make the correct cycle error examination code of multiplexer 16 outputs.Utilize existing cycle error examination code production method, at the same time, five cycle error examination code generators can move simultaneously, and therefore the power that is consumed increases.And, also can make gate number (gate count) increase because need arrive five cycle error examination code generators.And under the common situation, the cycle error examination code that has only a CRC generator to produce is required, therefore with existing cycle error examination code production method, is very inefficent, and the resource of waste software and hardware and the time of computing.

Summary of the invention

The purpose of one embodiment of the invention is for providing a kind of production method that reduces the cycle error examination code of cycle error examination code generator quantity.

The present of another embodiment of the present invention is to reduce the required gate number of cycle error examination code generator.

One embodiment of the invention are a kind of production method of cycle error examination code, finished with one first cycle error examination code generator and one second cycle error examination code generator, this method comprises that transmission one response signal is to this first cycle error examination code generator and this second cycle error examination code generator; Transmit a buffer release signal to this second cycle error examination code generator; According to one first cycle error examination code of this response signal generation corresponding to one first signal; Produce one second cycle error examination code according to this buffer release signal and this response signal corresponding to a secondary signal; This first cycle error examination code is imported one first arithmetic element, use in the hope of one the 3rd cycle error examination code corresponding to one the 3rd signal, wherein, this first signal and the 3rd signal have the difference of the value of at least one.

Another embodiment of the present invention is a kind of production method of cycle error examination code, comprises selecting one first bag and one second bag, and wherein, the data value that this first bag is stored second wraps in the data value of being stored and has at least the value of a position different with this; Utilize a cycle error examination code generator to produce corresponding to this first one first cycle error examination code that wraps; Produce corresponding to this second one second cycle error examination code that wraps according to this first cycle error examination code and a reference signal.

Description of drawings

Fig. 1 is the schematic diagram of an existing cycle error examination code production method.

Fig. 2 is the schematic diagram according to an embodiment of cycle error examination code production method of the present invention.

Fig. 3 is the schematic diagram according to another embodiment of cycle error examination code production method of the present invention

Fig. 4 is the schematic diagram according to another embodiment of cycle error examination code production method of the present invention.

The reference numeral explanation

11,21-the one CRC generator

12,22-the 2nd CRC generator

13-the 3rd CRC generator

14-the 4th CRC generator

15-the 5th CRC generator

16,2 6-multiplexers

23-first arithmetic element

24-second arithmetic element

25-the 3rd arithmetic element

31,41-bag detecting unit

32,42-CRC generator

Embodiment

Fig. 2 is the schematic diagram according to an embodiment of cycle error examination code production method of the present invention.In the present embodiment, be to be the example explanation with HyperTransport 3.0 high speed transmission systems.In HyperTransport 3.0 high speed transmission systems, the NOP packet format is defined as follows:

Bit-Tim e	7	6	5	4	3	2	1	0
Bit-Tim e	7	6	5	4	3	2	1	0	0	Rsv	DisCon	Cmd[5:0]:000000
1	ResponseData[1: 0]		Response[1:0 ]		PostData[1:0]		PostCmd[1:0]		0	Rsv	DisCon	Cmd[5:0]:000000
1	ResponseData[1: 0]		Response[1:0 ]		PostData[1:0]		PostCmd[1:0]		2	0	Diag	Isoc	Rsv	NonPostData[1:0 ]	NonPostCmd[1:0 ]
3	RxNextPktToAck[7:0]								2	0	Diag	Isoc	Rsv	NonPostData[1:0 ]	NonPostCmd[1:0 ]

If the bag of NOP is to belong to general controlling packet (normal control packet), then its corresponding CTL signal is four signals [1111].If the bag of NOP is to belong to insert controlling packet (insert controlpacket), then its corresponding CTL signal is four signals [0111].The purpose of CTL signal can be inserted in the packet for allowing controlling packet, and packet is made the mistake in computation cycles error checking sign indicating number or influences originally correct cycle error examination code.

In the present embodiment, need a buffer release signal (buffer release message), its signal name is NopData, and in the present embodiment, its signal definition is as follows:

NopData＝{NonPostData[1:0]，NonPostCmd[1:0]，ResponseData[1:0]，Response[1:0]，PostData[1:0]，PostCmd[1:0]}

In addition, the numbering of the stream data bag that transmits by delivery port is named as CPUPKtToAck.Also be exactly RxNextPktToAck in the present embodiment.

The input of CRC generator can be defined as follows:

{Ctl3，CPUPKtToAck，1’b1，4’b0，NopData[11:8]，1’b1，NopData[7:0]，1’b1，1’b0，DisCon，6’b0}

In HyperTransport 3.0 high speed transmission systems, always have five kinds of different NOP, be listed below:

General controlling packet and do not have the buffer release signal: Ctl3=1 ' b1, DisCon=1 ' b0

General controlling packet and the buffer release signal is arranged: Ctl3=1 ' b1, DisCon=1 ' b0

Insert controlling packet and do not have the buffer release signal: Ctl3=1 ' b0, DisCon=1 ' b0

Insert controlling packet and the buffer release signal is arranged: Ctl3=1 ' b0, DisCon=1 ' b0

Broken string (Disconnect) NOP:Ctl0=1 ' b1, DisCon=1 ' b1

In the present embodiment, broken string NOP only just can produce after the bag transmission finishes, and broken string NOP also represents that this broken string NOP bag must be dropped (discard).Therefore, in broken string NOP, do not discuss whether have the buffer release signal, and this broken string NOP also belongs to general controlling packet.

In the prior art, five kinds of different NOP must rely on five kinds of different CRC generators to produce corresponding CRC, and this can make the gate number increase, and please waste software and hardware resources.Therefore one embodiment of the invention provide cycle error examination code production method as shown in Figure 2, can reduce the required quantity of CRC generator.Because insert control NOP and generally control NOP in the input of CRC generator, have only a position difference, therefore can utilize a CRC generator and an arithmetic element to produce two kinds of corresponding CRC.In the present embodiment, first arithmetic element 23 and the 3rd arithmetic element 25 are an XOR gate (XOR Gate), receive the CRC that a CRC generator 21 and the 2nd CRC generator 22 are produced respectively.Then, first arithmetic element 23 and the 3rd arithmetic element 25 are carried out XOR with the CRC and the reference signal that receive again, to obtain another CRC.In one embodiment,, the reference signal that first arithmetic element 23 and the 3rd arithmetic element 25 are received can be defined as follows:

32’b0000_0100_1100_0001_0001_1101_1011_0111

Moreover, because existing input signal in order to the CRC generator that produces broken string NOP and the general controlling packet of generation and do not have in the input signal of CRC generator of buffer release signal and have only 1 position different, so we can utilize a CRC generator and an arithmetic element to produce both CRC.In the present embodiment, finish with a CRC generator 21 and second arithmetic element 24 exactly.Second arithmetic element 24 is carried out XOR with the CRC and the reference signal that receive, again to obtain another CRC after receiving the CRC that a CRC generator 21 produced.In one embodiment, reference signal can be defined as follows:

32’b1110_1110_0010_1000_0101_1011_0100_0110

Utilize above-mentioned function mode just can utilize two CRC generators (a CRC generator 21 and the 2nd CRC generator 22), and the crc value that produces corresponding to five kinds of different N OP of arithmetic element 23 to 25.In the embodiment shown in Figure 2, a CRC generator 21 is the CRC that inserts controlling packet and do not have the buffer release signal in order to produce.The 2nd CRC generator 22 is the CRC that inserts controlling packet and the buffer release signal is arranged in order to produce.First arithmetic element 23 is in order to produce general controlling packet and not have the CRC of buffer release signal.Second arithmetic element 24 is in order to produce the CRC of broken string NOP.The 3rd arithmetic element 25 is in order to produce general controlling packet and the CRC of buffer release signal is arranged.

In the present embodiment, the input signal of a CRC generator 21 can be defined as follows:

{1’b0，CPUPktToAck，1’b1，8’b0，1’b1，8’b0，1’b1，8’b0}

The input signal of the 2nd CRC generator 22 can be defined as follows:

{1’b0，CPUPktToAck，1’b1，{4b’b0，NopData[11:8]}，1’b1，NopData[7:0]，1’b1，8’b0}

In cycle error examination code production method shown in Figure 2, more can utilize a multiplexer 26 to receive five different CRC, select signal Select to decide which CRC of output by one again.

Fig. 3 is the schematic diagram according to another embodiment of cycle error examination code production method of the present invention.In Fig. 3, ignore instruction NOP is sent to bag detecting unit 31 earlier in order to distinguish its packet format.Then be sent to again in the corresponding CRC generator 32 in order to produce corresponding CRC.In the present embodiment, the framework of CRC generator 32 can be as shown in Figure 2.And utilize the testing result of wrapping detecting unit 31, select and enable the CRC generator and the arithmetic element of correspondence, in order to produce required CRC.

Fig. 4 is the schematic diagram according to another embodiment of cycle error examination code production method of the present invention.Ignore instruction NOP is sent to CRC generator 42 and produces five kinds of possible CRC, and the same time, ignore instruction NOP also is sent to bag detecting unit 41 in order to after distinguishing its packet format, produces one and selects signal Select.Then CRC generator 42 is again according to selecting signal Select to export corresponding CRC.In the present embodiment, the framework of CRC generator 32 can be as shown in Figure 2.

Though the present invention discloses as above with specific embodiment; so it is only in order to be easy to illustrate technology contents of the present invention; and be not with narrow sense of the present invention be defined in this embodiment; have in the technical field under any and know the knowledgeable usually; without departing from the spirit and scope of the present invention; when can doing a little change and retouching, so protection scope of the present invention is as the criterion when looking the claim person of defining of the present invention.

Claims

1. the production method of a cycle error examination code is finished with one first cycle error examination code generator and one second cycle error examination code generator, and this method comprises:

Transmit a response signal to this first cycle error examination code generator and this second cycle error examination code generator;

Transmit a buffer release signal to this second cycle error examination code generator;

According to one first cycle error examination code of this response signal generation corresponding to one first signal;

Produce one second cycle error examination code according to this buffer release signal and this response signal corresponding to a secondary signal; And

This first cycle error examination code is imported one first arithmetic element, use in the hope of one the 3rd cycle error examination code corresponding to one the 3rd signal, wherein, this first signal and the 3rd signal have the difference of the value of at least one.

2. the production method of cycle error examination code as claimed in claim 1, wherein, this first arithmetic element is an XOR gate.

3. the production method of cycle error examination code as claimed in claim 2, wherein, the 3rd cycle error examination code is the result that this first cycle error examination code and one first reference signal are carried out XOR.

4. the production method of a cycle error examination code comprises:

Select one first bag and one second bag, wherein, this data value of being stored of first bag second wraps in the data value of being stored and has at least the value of a position different with this;

Utilize a cycle error examination code generator to produce corresponding to this first one first cycle error examination code that wraps; And

Produce corresponding to this second one second cycle error examination code that wraps according to this first cycle error examination code and a reference signal.

5. the production method of cycle error examination code as claimed in claim 4, wherein, this second cycle error examination code is the result that this first cycle error examination code and this reference signal are carried out XOR.

6. the production method of cycle error examination code as claimed in claim 4, wherein, this reference signal is that form and this first cycle error examination code according to form of this first bag, second bag determines.