CN100368997C - Encoder for correcting static data storage fault - Google Patents
Encoder for correcting static data storage fault Download PDFInfo
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- CN100368997C CN100368997C CNB200510083858XA CN200510083858A CN100368997C CN 100368997 C CN100368997 C CN 100368997C CN B200510083858X A CNB200510083858X A CN B200510083858XA CN 200510083858 A CN200510083858 A CN 200510083858A CN 100368997 C CN100368997 C CN 100368997C
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Abstract
An error-correction coding device of static data storage is prepared as generating six digit calibration code by detecting and error-correcting circuit of sixteen parallel bit error according to sixteen digit data, generating control time sequence of automatic error-correction coding by time sequence circuit, isolating buses of storage and processor to each other by data bus isolation unit, using signal line to connect said unit and said circuits, sending control signal to said detecting and error-correcting circuit as well as said unit by said control circuit, using data bus to connect said unit to said detecting and error-correcting circuit.
Description
Technical field
The present invention relates to a kind of encoder for correcting, particularly a kind of encoder for correcting of static data storage.
Background technology
Compare under the condition of severe in electromagnetic environment, large scale integrated circuit usually can be interfered, so that cisco unity malfunction.For the device that utilizes bistable state to store as RAM one class, tend under strong jamming the bombardment of high energy particle (as be subjected to) and overturn, make " 0 " of original storage become " 1 ", perhaps " 1 " is become " 0 ", this phenomenon is called single-particle inversion.Single-particle inversion can produce serious consequence, makes the control procedure of control program make a mistake, and perhaps the critical data of storing among the RAM is made mistakes.Particularly in space environment, the single-particle inversion effect that space high energy particle radiation causes can make the data among the static memory SRAM on the aerospace computer small probability mistake can occur, and this mistake is if untimelyly correct the normal operation that will influence computer system.High reliability is a basic demand of spaceborne computer, in case spaceborne computer breaks down, its consequence is with hardly imaginable.
On the spacecraft of various orbit altitudes, the probability of single-particle inversion is higher, in order to guarantee the reliability of carry-on computing machine, must have relevant device to realize the Error Correction of Coding that data are stored.
In the prior art, the error in data that solves in the storer usually adopts software approach to realize, adopt this method to be easy to realize, but speed is slow, is not suitable for the real-time higher system.
Summary of the invention
The purpose of this invention is to provide a kind of encoder for correcting of static data storage, realize error correction the data storage errors.
To achieve these goals, the invention provides a kind of encoder for correcting of static data storage, this device is applied on the computing machine, comprise 16 bit parallel Error detection and error correction circuit 1, data bus isolated location 3, it is characterized in that, comprise that also sequential control circuit 2,16 bit parallel Error detection and error correction circuit 1 generate 6 bit check sign indicating numbers according to 16 bit data word; Sequential control circuit 2 generates the control timing that is used for automatic Error Correction of Coding; Data bus isolated location 3 is realized the data bus of storer and the mutual isolation of processor data bus; Be connected by signal wire respectively between sequential control circuit 2 and 16 bit parallel Error detection and error correction circuit 1, the data bus isolated location 3, by signal wire, sequential control circuit 2 transmits control signal to 16 bit parallel Error detection and error correction circuit 1 and data bus isolated location 3; Data bus isolated location 3 and 16 bit parallel Error detection and error correction circuit 1 link to each other by data bus.
In the technique scheme, described 16 bit parallel Error detection and error correction circuit 1 adopts improved Hamming code to generate 6 check code according to 16 bit data word and be stored in the static memory of computing machine at the write cycle time of the microprocessor of computing machine, in the read cycle of computer microprocessor, check code and data word are read simultaneously to detect error code.
In the technique scheme, the control timing that described sequential control circuit 2 generates comprises the mode of operation switching and the steering logic of read-write logic, Error detection and the error correction circuit of computer memory.
In the technique scheme, described data bus isolated location 3 adopts bidirectional bus transceiver 54HC245.
Described 16 bit parallel Error detection and error correction circuit 1 adopt the special IC of radioresistance dosage greater than 300K RAD.
The invention has the advantages that:
1, the encoder for correcting of static data of the present invention storage has solved the problem that the data of storing among the SRAM that causes owing to single-particle inversion make a mistake, and has realized the purpose of error in data among the real-time SRAM of correction.
2, apparatus of the present invention are based upon on the basis of digital logic hardware circuit, so reliability, stability access sufficient assurance.
Description of drawings
Fig. 1 is the structural drawing of the encoder for correcting of static data storage of the present invention;
Fig. 2 is the time sequential routine figure of 16 bit parallel Error detection and error correction circuit.
Embodiment
Below in conjunction with the drawings and specific embodiments, the encoder for correcting that static data of the present invention is stored is described.
As shown in Figure 1, the encoder for correcting of static data storage comprises 16 bit parallel Error detection and error correction circuit 1, sequential control circuit 2, data bus isolated location 3, and this device is the part that the frame of broken lines among Fig. 1 is surrounded.The effect of 16 bit parallel Error detection and error correction circuit 1 is to generate 6 bit check sign indicating numbers according to 16 bit data word.The effect of sequential control circuit 2 is to generate the control timing that is used for automatic Error Correction of Coding.The effect of data bus isolated location 3 is to realize the data bus of storer and the mutual isolation of processor data bus.Encoder for correcting of the present invention can not use separately in computing machine, need use with microprocessor, storer etc. are common.Be connected with signal wire respectively between sequential control circuit 2 and 16 bit parallel Error detection and error correction circuit 1, data bus isolated location 3, the storer, by signal wire, sequential control circuit 2 transmits control signal to both; Sequential control circuit 2 also links to each other by control bus with microprocessor, and microprocessor transmits control signal to sequential control circuit 2 by control bus.Data bus isolated location 3 is connected between the two segment data buses, one piece of data bus one end is connected on the microprocessor, the other end is connected to data bus isolated location 3, and another segment data bus one end is connected to data bus isolated location 3, and the other end is connected on the storer; With data bus that storer links to each other on, also be connected with 16 bit parallel Error detection and error correction circuit 1 and sequential control circuit 2.Also be connected with address bus between microprocessor and the storer.Below in conjunction with microprocessor and storer, the various piece of encoder for correcting is elaborated.
16 bit parallel Error detection and error correction circuit (being called for short EDAC) 1 selected the special IC of radioresistance dosage greater than 300K RAD (Si) for use, and it has four kinds of mode of operations, and these mode of operations are as shown in table 1.The sequential that 16 words are write is fairly simple, and the WriteMode in only need carry out table 1 get final product, and typically " word is read " time sequential routine then needs the combination of other three kinds of mode of operations, as shown in Figure 2.At first enter S1S0 (01) pattern, data word on the bus and check word are simultaneously from importing 16 bit parallel Error detection and error correction circuit (being called for short EDAC) 1.Enter S1S0 (11) pattern then, 16 bit parallel Error detection and error correction circuit (be called for short EDAC) 1 internal circuit latch data word and check word, and produce new check word and compare with the check word that latchs and enable the output of error code sign.Enter S1S0 (11) pattern at last, new and old two check words are carried out xor operation generate the output of diagnosis sign indicating number, and according to diagnosing sign indicating number to exporting after the data word error correction.
Table 1 EDAC mode of operation
| Memory cycle | Control signal | The EDAC function | Data I/O | Check word | The error code sign | ||
| S1 | S0 | One | | ||||
| Write | |||||||
| 0 | 0 | Produce check code | The input data | The |
0 | 0 | |
| Read | 0 | 1 | Read data words and check word | The input data | The |
0 | 0 |
| Read | 1 | 1 | Latch and export the error code sign | Latch data | Latch check word | Enable | Enable |
| Read | 1 | 0 | The correction of data word also produces the diagnosis sign indicating number | Data after the output error correction | Output diagnosis sign indicating number | Enable | Enable |
Sequential control circuit 2 is connected by control bus with microprocessor, and sequential control circuit 2 utilizes convertible control signal S1 and the S0 that goes out 16 bit parallel Error detection and error correction circuit (EDAC) 1 of the memory read/write cycle sequential of microprocessor.In addition, sequential control circuit 2 also links to each other with data bus isolated location 3 with storer, sends read-write control signal to storer, sends enable signal to bus isolated location 3, and realizes the read-write of byte by the combination of signal.Sequential control circuit 2 can be realized its function to Programmable Logic Device (FPGA) programming.
Data bus isolated location 3 can adopt bidirectional bus transceiver 54HC245 to realize its function.
Microprocessor can be divided into four kinds of situations to data write in the storer, is respectively that word (WORD) is write, word (WORD) is read, byte (BYTE) is write, byte (BYTE) is read, and illustrates respectively in conjunction with the workflow of encoder for correcting of the present invention to four kinds of situations.
1), word is write.It is will be with in the data word write store that word writes.At first, microprocessor outputs to data word on the data bus, 16 bit parallel Error detection and error correction circuit 1 obtain data word from data bus, 2 pairs 16 bit parallel Error detection of sequential control circuit and error correction circuit 1 output valve are 00 control signal S1S0, as shown in Table 1, under this mode of operation, 16 bit parallel Error detection and error correction circuit 1 are according to the numeral of input, the generation check word also outputs in the data bus, sequential control circuit 2 sends memory write signals, together in the write store, data word is identical with the address of check word institute memory storing unit with data word and check word.
2), word is read.It is will be with data word from the storer reading into the microprocessor that word is read.Microprocessor sends the read operation order to sequential control circuit 2, sequential control circuit 2 is 01 control signal S1S0 to 16 bit parallel Error detection and error correction circuit 1 value of sending according to this read operation order, according to this control signal sense data word and check word and deposit in the storage unit in 16 bit parallel Error detection and the error correction circuit 1 from storer, sequential control circuit 2 values of sending are 11 control signal S1S0 then, under the effect of this control signal, 16 bit parallel Error detection and error correction circuit 1 latch data word and check word.Coding rule according to Hamming code, 16 bit parallel Error detection and error correction circuit 1 utilize data word to regenerate check word, then check word that regenerates and the check word that latchs are compared, if both differences, illustrate that the error code phenomenon has taken place for latched data word and check word, the output error sign.Sequential control circuit 2 is if receive error flag, then the value of sending is 10 control signal, 16 bit parallel Error detection and error correction circuit 1 enter error correction mode, principle according to Hamming code, if an error code is arranged in the discovery data word, can correct automatically, if find to have an error code in check word, then only sign is not corrected.With data word after the error correction and the output of diagnosis sign indicating number, sequential control circuit 2 is latched in the data word after the error correction in the internal register of sequential control circuit 2 simultaneously, and sends microprocessor to by bus isolated location 3.At last, sequential control circuit 2 generation values are 00 control signal S1S0, re-execute the word write operation, regenerate check word with the data word after the error correction, utilize the data word and the check word of new data word and check word refresh memory unit.
3) byte is write.It is with in the data byte write store that byte is write.16 bit parallel Error detection and error correction circuit 1 can only be carried out 16 word operation, so microprocessor the time need be combined into word with byte and operates doing the byte read-write.That is to say, the word at byte place will be read together when from storer, reading byte that then the byte of microprocessor output is covered the respective byte of word, another byte is constant in the maintenance data word, at last this byte is write back storer, realizes byte write operations.
Its specific operation process is: sequential control circuit 2 generation values are 01 control signal S1S0, data word and check word are read from storer, be input in 16 bit parallel Error detection and the error correction circuit 1, sequential control circuit 2 generation values are 11 control signal S1S0 then, 16 bit parallel Error detection and error correction circuit 1 are according to this control signal latch data word and check word, be under the effect of 00 control signal S1S0 in value then, regenerate check word by data word.Check word that regenerates and the check word that latchs are compared, whether check produces error code according to comparative result, if there is the error code phenomenon to produce, then send error flag to sequential control circuit 2, after sequential control circuit 2 is received error flag, to 16 bit parallel Error detection and error correction circuit 1 transmission value is 10 control signal, and 16 bit parallel Error detection and error correction circuit 1 enter error correction mode, the data word after the error correction are latched in the internal register of sequential control circuit 2.Then, sequential control circuit 2 produces bytes and selects signals that the data byte that microprocessor will write store is outputed on the bus from bus isolated location 3, and the output of another byte of bus isolated location 3 is set to high-impedance state; Simultaneously, output on the bus from the internal register of sequential control circuit 2 writing another irrelevant byte with byte in the data word after the error correction, two bytes on the bus form a new data word, then, time sequence control logic 2 generation values are 00 control signal S1S0, new data word on the bus is sent in 16 bit parallel Error detection and the error correction circuit 1, regenerate check word according to revised data word, at last new data word and check word are sent in the storer, finished byte write operations.
4), byte is read.It is that data byte is read from storer that byte is read.Same, because 16 bit parallel Error detection and error correction circuit 1 can only be carried out 16 word operation, so the byte operation of reading needs that also byte is combined into word and operates.Its specific operation process is as follows.Sequential control circuit 2 generation values are 01 control signal S1S0, and data word and check word are read from storer, are input in 16 bit parallel Error detection and the error correction circuit 1.High byte in the described data word or low byte include the data byte that microprocessor will be read.Sequential control circuit 2 transmission values are 11 control signal S1S0, latch data word and check word, 16 bit parallel Error detection and error correction circuit 1 regenerate check word by data word, check word that regenerates and the check word that latchs are compared, whether check produces error code according to comparative result, if there is the error code phenomenon to produce, then send error flag to sequential control circuit 2, after sequential control circuit 2 is received error flag, it to 16 bit parallel Error detection and error correction circuit 1 transmission value 10 control signal, 16 bit parallel Error detection and error correction circuit 1 enter error correction mode, the data word after the error correction are latched in the internal register of sequential control circuit 2.Sequential control circuit 2 produces byte and selects the desired byte of signal output microprocessor, and is sent in the microprocessor by the bus isolated location, realizes microprocessor reading the data byte.At last, sequential control circuit 2 also will the generation value be 00 control signal, re-executes a secondary word write operation, with the data word after the error correction and the check word data word and the check word of refresh memory unit again.
Claims (5)
1. the encoder for correcting of static data storage, this device is applied on the computing machine, comprise 16 bit parallel Error detection and error correction circuit (1), data bus isolated location (3), it is characterized in that, also comprise sequential control circuit (2), 16 bit parallel Error detection and error correction circuit (1) generate 6 bit check sign indicating numbers according to 16 bit data word; Sequential control circuit (2) generates the control timing that is used for automatic Error Correction of Coding; Data bus isolated location (3) is realized the data bus of storer and the mutual isolation of processor data bus; Sequential control circuit (2) is connected by signal wire respectively between (3) with 16 bit parallel Error detection and error correction circuit (1), data bus isolated location, by signal wire, sequential control circuit (2) transmits control signal to 16 bit parallel Error detection and error correction circuit (1) and data bus isolated location (3); Data bus isolated location (3) links to each other by data bus with error correction circuit (1) with 16 bit parallel Error detection.
2. the encoder for correcting of static data storage according to claim 1, it is characterized in that, described 16 bit parallel Error detection and error correction circuit (1) adopt improved Hamming code to generate 6 check code according to 16 bit data word and be stored in the static memory of computing machine at the write cycle time of the microprocessor of computing machine, in the read cycle of computer microprocessor, check code and data word are read simultaneously to detect error code.
3. the encoder for correcting of static data storage according to claim 1, it is characterized in that, the control timing that described sequential control circuit (2) generates comprises the mode of operation switching and the steering logic of read-write logic, Error detection and the error correction circuit of computer memory, and utilizes and can only carry out 16 bit parallel Error detection of word operation and the read-write that error correction circuit (1) has been realized octet.
4. the encoder for correcting of static data storage according to claim 1 is characterized in that, described data bus isolated location (3) adopts bidirectional bus transceiver 54HC245.
5. the encoder for correcting of static data storage according to claim 2 is characterized in that, described 16 bit parallel Error detection and error correction circuit (1) adopt the special IC of radioresistance dosage greater than 300K RAD.
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| CNB200510083858XA CN100368997C (en) | 2005-07-12 | 2005-07-12 | Encoder for correcting static data storage fault |
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| CN101493804B (en) * | 2008-01-24 | 2011-07-20 | 国际商业机器公司 | Data bus system, coder/decoder thereof and coding/decoding method |
| CN101551763B (en) * | 2009-05-15 | 2010-10-20 | 中国人民解放军国防科学技术大学 | Method and device for repairing single event upset in field programmable logic gate array |
| CN103885850B (en) * | 2013-03-01 | 2016-12-28 | 上海富欣智能交通控制有限公司 | Memorizer On line inspection system and method |
| CN103279440A (en) * | 2013-05-10 | 2013-09-04 | 北京宇航系统工程研究所 | Bus communication method between single-machine modules |
| CN104597807B (en) * | 2014-12-10 | 2018-03-13 | 深圳航天东方红海特卫星有限公司 | A kind of spaceborne integrated electronicses CPU upset hardened systems and method |
| CN106328209B (en) * | 2015-06-30 | 2020-01-21 | 中国科学院电子学研究所 | Memory single-particle multi-bit upset fault-tolerant method and circuit |
| CN106407037B (en) * | 2015-07-27 | 2019-04-02 | 中国科学院电子学研究所 | A kind of dual-ported memory Word line control circuit |
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| US5701314A (en) * | 1995-12-21 | 1997-12-23 | Cirrus Logic, Inc. | On-the-fly error correction using thermal asperity erasure pointers from a sampled amplitude read channel in a magnetic disk drive |
| CN1173668A (en) * | 1996-08-06 | 1998-02-18 | 三星电子株式会社 | Error correcting apparatus and method of digital processing system |
| CN1635477A (en) * | 2003-12-30 | 2005-07-06 | 中国科学院空间科学与应用研究中心 | Real-time error detection and correction chip |
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Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5701314A (en) * | 1995-12-21 | 1997-12-23 | Cirrus Logic, Inc. | On-the-fly error correction using thermal asperity erasure pointers from a sampled amplitude read channel in a magnetic disk drive |
| CN1173668A (en) * | 1996-08-06 | 1998-02-18 | 三星电子株式会社 | Error correcting apparatus and method of digital processing system |
| CN1635477A (en) * | 2003-12-30 | 2005-07-06 | 中国科学院空间科学与应用研究中心 | Real-time error detection and correction chip |
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