CN101493804B - Data bus system, coder/decoder thereof and coding/decoding method - Google Patents
Data bus system, coder/decoder thereof and coding/decoding method Download PDFInfo
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Abstract
The invention relates to a data bus system and a coder/decoder and a method thereof. The data bus coder comprises: a bus transition coder for carrying out bus transition coding to data according to a preset bus transition coding scheme so as to generate encoding data and transition indicting information; a virtual byte generator for converting the transition indicting information into virtual bytes according to a preset coding mapping; and an error correcting and detecting encoder for generating the error correcting and detecting codes of a virtual character according to a preset error correction and detection coding scheme, wherein the detecting bit number of the preset error correcting and detecting coding scheme is at least one bit more than the error correcting bit number; the mapping leads the hamming distance between all the possible values of the virtual bytes and the referential virtual bytes beyond the conversion of the mapping to be a fixed value and not more than the correcting bit number of the error correcting and detecting coding scheme; and the virtual character contains data to be output, virtual bytes corresponding to the data and stuff bits needing to be allocated with fixed values according to the requirements of the error correcting and detecting coding scheme.
Description
Technical field
The present invention relates to computer data bus, relate in particular to based on bus upset coded data bus system and scrambler, demoder, coding method and coding/decoding method.
Background technology
Computer technology rapid development, popularizing day by day of especially portable computing application impels people to pay close attention to low-power large scale integrated circuit (VLSI) design more.
" the Bus-Invert Coding for Low-Power I/O " of Mircea R.Stan and Wayne P. Burleson, IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL.3, NO.I discloses a kind of bus upset (Bus-Invert) coding techniques that is used to reduce the data bus power consumption March nineteen ninety-five.
Fig. 1 schematically shows the architecture that relates to based on the data highway system of the data bus encoder of this bus turnover technology.As shown in Figure 1, processor 10 is via data bus 20 and Memory Controller 30 reference-to storage 40.When processor 10 when storer 40 writes data, in processor 10, bus transition coder 12 generates upset coded data and corresponding upset indicating bit (INV_IND) according to the data in the data buffer 11, is sent to bus in the Memory Controller 30 demoder 31 that overturns via will overturn coded data and upset indicating bit of data bus 20.Bus upset demoder 31 is decoded to the upset coded data that receives according to the upset indicating bit, and in the writing data into memory 40 with decoding.Because this technology is for the bus better effects if of less figure place, therefore also having proposed the bus that figure place is more is divided into the less hyte of figure place, at overturn the respectively improvement project of coding of hyte.But this scheme need provide a upset indicating bit for each hyte, and described upset indication constitutes the upset indication information.This needs extra circuit to transmit the upset indication information.
Recognize the above-mentioned deficiency of prior art, the inventor considers improving based on bus upset coded data bus.
Summary of the invention
The purpose of this invention is to provide a kind of based on bus upset coded data bus system and scrambler, demoder, coding method and coding/decoding method, to reduce the cost that transmits the upset indication information.
One embodiment of the present of invention provide a kind of data bus scrambler, comprise: bus transition coder is configured to treat coded data according to predetermined bus upset encoding scheme and carries out bus upset coding, to produce coded data and upset indication information; Virtual hyte generator is configured to convert described upset indication information to virtual hyte according to predictive encoding mapping; With the error correcting and detecting scrambler, be configured to generate the error correcting and detecting sign indicating number of virtual word according to predetermined error correcting and detecting encoding scheme, the error detection figure place of described predetermined error correcting and detecting encoding scheme is Duoed one at least than the error correction figure place, wherein, the mapping of described predictive encoding make the institute of described virtual hyte might value and according to described predictive encoding shine upon change less than the virtual hyte of reference between Hamming distance be fixed value and the error correction figure place that is not more than described predetermined error correcting and detecting encoding scheme, and wherein, described virtual word comprise described coded data and with the corresponding virtual hyte of described coded data, if and have unappropriated one or more other position, then described one or more other position fixed values of respectively asking in the described virtual word.
In a preferred embodiment, the data bus scrambler can also comprise: outlet selector is configured to control described data bus scrambler and export described data to be encoded when mode control signal indication normal mode; When mode control signal indication low-power mode, control described data bus scrambler and export described coded data; With the virtual bit group selector, be configured to control, make that described virtual word comprises described data to be encoded and fixing virtual hyte when mode control signal indication normal mode; When mode control signal indication low-power mode, described virtual word comprise described coded data and with the corresponding virtual hyte of described coded data.
One embodiment of the present of invention provide a kind of data bus demoder, comprise: the error correcting and detecting demoder, be configured to virtual word be carried out verification according to predetermined error correcting and detecting encoding scheme with the corresponding error correcting and detecting sign indicating number of input data, the error detection figure place of described predetermined error correcting and detecting encoding scheme is Duoed one at least than the error correction figure place, described virtual word comprises described input data and the virtual hyte of reference, if and have unappropriated one or more other position, then described one or more other position fixed values of respectively asking in the described virtual word; Upset indication information generator, be configured to convert the upset indication information to according to the predetermined decoding mapping hyte that position in the virtual word of verification is corresponding with the virtual hyte of described reference, the virtual hyte of wherein said reference can not be changed according to described predictive encoding mapping, and according to the mapping of described predetermined decoding, the hyte that is converted might value and the virtual hyte of described reference between Hamming distance be fixed value and the error correction figure place that is not more than described predetermined error correcting and detecting encoding scheme; With bus upset demoder, be configured to the data that will decode accordingly be carried out bus upset decoding according to described upset indication information.
In a preferred embodiment, the data bus demoder can also comprise: outlet selector, be configured to when mode control signal indication normal mode, control described data bus demoder output through in the described virtual word of described error correcting and detecting demoder verification with the corresponding data of described input data; When mode control signal indication low-power mode, control the data that described data bus scrambler output produces through described bus upset decoder decode; With the hyte selector switch, be configured to control, make that described virtual word comprises described input data and the virtual hyte of described reference when mode control signal indication low-power mode; When mode control signal indication normal mode, described virtual word comprises described input data and described fixing virtual hyte, and the virtual hyte of wherein said reference is different from described fixing virtual hyte.When the virtual hyte of reference was identical with fixing virtual hyte, the data bus demoder can not comprise the hyte selector switch.
One embodiment of the present of invention provide a kind of coding method of data bus, comprise: treat coded data according to predetermined bus upset encoding scheme and carry out bus upset coding, to produce coded data and upset indication information; Mapping converts described upset indication information to virtual hyte according to predictive encoding; With the error correcting and detecting sign indicating number that generates virtual word according to predetermined error correcting and detecting encoding scheme, the error detection figure place of described predetermined error correcting and detecting encoding scheme is Duoed one at least than the error correction figure place, wherein, the mapping of described predictive encoding make the institute of described virtual hyte might value and according to described predictive encoding shine upon change less than the virtual hyte of reference between Hamming distance be fixed value and the error correction figure place that is not more than described predetermined error correcting and detecting encoding scheme, and wherein, described virtual word comprise described coded data and with the corresponding virtual hyte of described coded data, if and have unappropriated one or more other position, then described one or more other position fixed values of respectively asking in the described virtual word.
One embodiment of the present of invention provide a kind of coding/decoding method of data bus, comprise: virtual word is carried out verification according to predetermined error correcting and detecting encoding scheme with the corresponding error correcting and detecting sign indicating number of input data, the error detection figure place of described predetermined error correcting and detecting encoding scheme is Duoed one at least than the error correction figure place, described virtual word comprises described input data and the virtual hyte of reference, if and have unappropriated one or more other position, then described one or more other position fixed values of respectively asking in the described virtual word; Convert the upset indication information to according to the predetermined decoding mapping hyte that position in the virtual word of verification is corresponding with the virtual hyte of described reference, the virtual hyte of wherein said reference can not be changed according to described predictive encoding mapping, and according to the mapping of described predetermined decoding, the hyte that is converted might value and the virtual hyte of described reference between Hamming distance be fixed value and the error correction figure place that is not more than described predetermined error correcting and detecting encoding scheme; With according to described upset indication information the data that will decode are accordingly carried out bus upset decoding.
One embodiment of the present of invention provide a kind of data highway system, comprise: the bus transmitting apparatus comprises above-mentioned data bus scrambler; The bus interface receiving unit comprises above-mentioned data bus demoder; And data bus, connect described bus transmitting apparatus and bus interface receiving unit.
According to embodiments of the invention, owing to transmit the upset indication information by ECC verification agency, and do not lose the basic function of ECC verification agency, therefore can under the situation that does not influence the data bus transmission reliability, omit the special circuit that transmits the upset indication information.
According to a preferred embodiment of the invention, owing under the situation of low transmission error frequency, utilize ECC verification agency to transmit the upset indication information, and under transmission error frequency condition with higher, recover the normal function of ECC verification agency, can realize stronger adaptability.
Description of drawings
With reference to below in conjunction with the explanation of accompanying drawing to the embodiment of the invention, can understand above and other purpose of the present invention, characteristics and advantage more easily, in the accompanying drawings:
Fig. 1 schematically shows the architecture that relates to based on the data highway system of the data bus encoder of bus turnover technology;
Fig. 2 be schematically illustrated based on the embodiment of the invention the data bus scrambler and the block diagram of the structure of data bus demoder;
Fig. 3 shows the process flow diagram of the coding method of carrying out in the data bus scrambler;
Fig. 4 shows the process flow diagram of the coding/decoding method of carrying out in the data bus demoder;
The Data View of Fig. 5 schematically shows the data of handling through according to the coding/decoding method of the embodiment of the invention;
Fig. 6 be schematically illustrated based on the preferred embodiment of the present invention the data bus scrambler and the block diagram of the structure of data bus demoder.
Embodiment
Embodiments of the invention are described with reference to the accompanying drawings.Should be noted that for purpose clearly, omitted the parts that have nothing to do with the present invention, those of ordinary skills are known and the expression and the description of processing in accompanying drawing and the explanation.
The structure of schematically illustrated data bus scrambler and the data bus demoder based on the embodiment of the invention of Fig. 2.As shown in Figure 2, processor 210 is via data bus 220 and Memory Controller 230 reference-to storage 240.Except that other parts, processor 210 comprises data buffer 211 and data bus scrambler 218.Except that other parts, Memory Controller 230 comprises data bus demoder 238.
The detail of relevant ECC coding techniques can be referring to following document.For example at " the A class of optimal minimum odd-weight-column sec-ded codes " of M.Y.Hsiao, IBMJ.Res Develop, 14 (4), in July, 1970, with the unit error correction has been described in the U.S. Pat 4334309, dibit error detection (SECDED) scheme, and the ECC encoder in the storer.The type of ECC encoding scheme also comprises three error detections of unit error correction (SEC-TED), three error detections of dibit error correction (DEC-TED), three four error detections of error correction (TEC-QED) or the like.The technology of utilizing the ECC sign indicating number that fault-tolerant ability is provided for data bus has for example been described in U.S. Pat 5630056.The ECC encoding scheme can adopt Hamming code, best strange weighted code, but is not limited to these sign indicating numbers.
The figure place of data bus 220 (promptly will carry out the figure place of bus upset coded data) can be divided into N hyte for M and data.So, at data to be sent from data buffer 211, N hyte of 212 pairs of data of the bus transition coder coding that overturns respectively, produce the upset indication information (INV_IND) of coded data and corresponding N position, the rollover states of the corresponding hyte of each indication of the indication information that wherein overturns.Therefore, the upset indication information may get 0～2
N-12
NOne of individual value.
The source that should be noted that data to be sent is not limited to data buffer 211.This source can be the other parts that bus transition coder 212 can have access to.
The codomain of virtual hyte can comprise 2
NIndividual mutually different J position bit string.The mapping of the predictive encoding of 214 bases of virtual hyte generator comprise this 2
NIndividual J position bit string and 2 of upset indication information
NThe one-to-one relationship of individual possibility value.With reference to virtual hyte REF is the J position bit string of value outside above-mentioned codomain, wherein this 2
NIndividual J position bit string is constant with the number K (that is, Hamming distance) of the difference position of comparing with reference to virtual hyte REF, and K≤H.Illustrated as the back, when K=H, the error correcting capability of ECC encoding scheme is used to transmit the upset indication information, and remains with basic error detecing capability (I-H position); And when K＜H, a part of error correcting capability of ECC encoding scheme is used to transmit the upset indication information, and all the other error correcting capabilities are used for the error correction of data, and keep certain error detecing capability (I-H position).
Fig. 3 shows the process flow diagram of the coding method of carrying out in the data bus scrambler 218 100.As shown in Figure 3, method 100 is from step S10.At step S12, bus transition coder 212 data that 211 acquisitions will send from the data buffer.At step S14, bus transition coder 212 produces the upset coded data and the indication information that overturns accordingly of the data that will send.At step S16, virtual hyte generator 214 shines upon the indication information that will overturn according to predictive encoding and converts virtual hyte to.At step S18, form virtual word in ECC scrambler 213, this virtual word comprises upset coded data from bus transition coder 212, from the virtual hyte of virtual hyte generator 214 and the filler (not shown) of getting fixed value that disposes under the situation of needs.Need to prove,,, do not need filler in the then virtual word if M+J equals L for filler; If M+J less than L, needs (L-M-J) individual filler in the then virtual word.Filler can be stored within the ECC scrambler 213 or outside.At step S20, ECC scrambler 213 generates the ECC sign indicating number of virtual word according to predetermined ECC encoding scheme.Method 100 finishes at step S22.
Coded data through data bus scrambler 218 is sent to data bus demoder 238 via data bus 220.The ECC coding that ECC scrambler 213 produces also is sent to data bus demoder 238.
In ECC demoder 232, from the M position coded data of bus transition coder 212, the L position is formed in the J position in conjunction with one or more filler of the possible identical value of ECC scrambler 213 descriptions with reference to virtual hyte REF and front virtual word.Need to prove,,, do not need filler in the then virtual word if M+J equals L for filler; If M+J less than L, needs (L-M-J) individual filler in the then virtual word.ECC demoder 232 is carried out verification according to the ECC sign indicating number of this virtual word and reception.Coded data herein, with reference to virtual hyte REF and the filler position in virtual bit distribute with ECC scrambler 213 in M bit data, the virtual hyte in J position identical with the position distribution of one or more filler in virtual word.It can also can be other order arbitrarily according to the series arrangement of listed type that the position distributes, for example with bit interleave, change order, or the like.Because virtual hyte with different with reference to the value that has and only have K position between virtual hyte REF certainly, therefore causes K faults artificially.Under the situation of figure place smaller or equal to H of makeing mistakes that detects, ECC demoder 232 can be corrected this K faults at least, thereby recovers the value of virtual hyte.With reference to virtual hyte REF and filler can be stored within the ECC demoder 232 or outside.
As previously mentioned, when K=H, the error correcting capability of ECC encoding scheme is used to transmit the upset indication information, and remains with basic error detecing capability (I-H position).In this case, the input of bus upset demoder can be direct data (as shown in Figure 2) from data bus, also can be the data (not shown) through verification from the ECC demoder.When K＜H, a part of error correcting capability of ECC encoding scheme is used to transmit the upset indication information, and all the other error correcting capabilities are used for the error correction of data, and keep certain error detecing capability (I-H position).In this case, the input of bus upset demoder should be the data (not shown) through verification from the ECC demoder.These two kinds of situations all are suitable for for the embodiment of Fig. 2 and 6.
Upset indication information generator 233 is according to the predetermined decoding mapping, i.e. the virtual hyte that the inverse mapping of predictive encoding mapping will recover converts the upset indication information to.
If K＜H, promptly a part of error correcting capability of ECC encoding scheme is used to the error correction of data, and then in one embodiment, the data that bus upset demoder is decoded are the data through the verification of ECC demoder.
Fig. 4 shows the process flow diagram of the coding/decoding method of carrying out in the data bus demoder 238 200.As shown in Figure 4, method 200 is from step S30.At step S32, in ECC demoder 232, form virtual word.At step S34, ECC demoder 232 is carried out verification according to the ECC sign indicating number of virtual word of forming and reception, to recover virtual hyte.At step S36, the upset indication information generator 233 virtual hyte that mapping will recover according to predetermined decoding converts the upset indication information to.At step S38, bus transition coder 231 according to the upset indication information to the upset coded data that the receives decoding of overturning.At step S40, method 200 finishes.
The Data View of Fig. 5 schematically shows the data of handling through according to the coding/decoding method of the embodiment of the invention.In situation shown in Figure 5, data are 64 (M=64), are divided into 6 hytes (N=6,16/16/8/8/8/8).Virtual hyte based on 64 ONE-HOT sign indicating numbers (J=64, K=1).The ECC encoding scheme be 9 SECDED ECC sign indicating numbers (L=128, H=1, I=2).The ONE-HOT sign indicating number is that a kind of figure place equals denotable state number, each yard has and a position is only arranged is 1 sign indicating number.The virtual hyte REF of reference is 64 bit strings of complete 0.
At situation shown in Figure 5, manner of execution 100.Be convenient expression, hereinafter use " 0x " expression sexadecimal number, with " 0b " expression binary number.Behind execution in step S12, the data that send of acquisition are 0x0000000000000000, i.e. G0=0x0000, G1=0x0000, G2=0x00, G3=0x00, G4=0x00, G5=0x00 (shown in L1 among Fig. 5 is capable).Suppose that last transmission data are 0x00000000000000FF, then behind upset coding (shown in S14 among Fig. 5) through step S14, the coded data that obtains overturning is 0x00000000000000FF, i.e. G0 '=0x0000, G1 '=0x0000, G2 '=0x00, G3 '=0x00, G4 '=0x00, G5 '=0xFF, the upset indication information is 0b000001, and the ONE-HOT sign indicating number " one-hot " that is converted to behind the process step S16 is 0x0000000000000002 (shown in L2 among Fig. 5 is capable).At step S20, the virtual word that upset coded data 0x00000000000000FF and " one-hot "=0x0000000000000002 constitute obtains ECC sign indicating number (shown in L2 among Fig. 5 is capable) through the ECC coding.
Continuation is with reference to figure 5, manner of execution 200.Virtual word before the decoding comprises coded data 0x00000000000000FF, i.e. G0 '=0x0000, G1 '=0x0000, G2 '=0x00, G3 '=0x00, G4 '=0x00, G5 '=0xFF and reference virtual hyte REF 0x0000000000000000 (shown in L3 among Fig. 5 is capable).To virtual word being carried out verification (shown in S34 among Fig. 5) according to the ECC sign indicating number.Virtual word through verification comprises coded data 0x00000000000000FF and ONE-HOT sign indicating number " one-hot "=0x0000000000000002.The ONE-HOT of process step S36 decodes and obtains overturning indication information 0b000001.Be decoded as 0x0000000000000000 (shown in L4 among Fig. 5 is capable) according to the upset indication information 0b000001 coded data 0x00000000000000FF that will overturn.
The structure of schematically illustrated data bus scrambler and the data bus demoder based on the preferred embodiment of the present invention of Fig. 6.As shown in Figure 6, processor 310 is via data bus 320 and Memory Controller 330 reference-to storage 340.Except that other parts, processor 310 comprises data buffer 311, data bus scrambler 318 and condition detector 315.Except that other parts, Memory Controller 330 comprises data bus demoder 338.Data bus scrambler 318 comprises bus transition coder 312, virtual hyte generator 314, ECC scrambler 313, outlet selector 316 and virtual bit group selector 317.Data bus demoder 338 comprises bus upset demoder 331, ECC demoder 332, upset indication information generator 333, hyte selector switch 334 and outlet selector 335.
Bus transition coder 312, virtual hyte generator 314, ECC scrambler 313, bus upset demoder 331, ECC demoder 332, upset indication information generator 333 are basic identical with bus transition coder 212, virtual hyte generator 214, ECC scrambler 213, bus upset demoder 231, ECC demoder 232, upset indication information generator 233 respectively, therefore are not described in detail here.
As known in the art, when take over party's ECC demoder is found to correct the mistake of (figure place of for example finding mistake equals the error detection figure place) by verification, can report ECC verification mistake.The mode of report can adopt zone bit, interruption, signal wire or the like.Transmit leg is general retransmission data and ECC sign indicating number after learning ECC verification mistake.
In the embodiment shown in Figure 2, if increase, then can carry out data re-transmitting more frequently owing to factors such as environment cause the occurrence frequency of the random error of data bus transmission.When occurrence frequency increased to a certain degree, retransmission overhead can be offseted the power reduction benefit that bus upset coding is brought, even causes power consumption to rise.Under these circumstances, stop the normal function that the bus upset is encoded and recovery ECC encodes on the contrary and can produce better effect.
In the embodiment shown in fig. 6, condition detector 315 is collected the information of relevant ECC verification mistake, according to the wrong occurrence frequency of the current ECC verification of the Information Statistics of collecting.As an alternate embodiment, condition detector 315 also can be collected the environmental baseline that related sensor measures (for example temperature in chassis etc.) data, determines corresponding ECC verification mistake occurrence frequency according to the wrong occurrence frequency of the ECC verification of measuring in advance and the relation curve of environmental baseline.
Termly or the renewal of response occurrence frequency, condition detector 315 is compared the wrong occurrence frequency of the ECC verification that obtains with predetermined threshold.If the wrong occurrence frequency of ECC verification surpasses predetermined threshold, mode control signal ENAB then is set with the indication normal mode, otherwise mode control signal ENAB is set with the indication low-power mode.
Outlet selector 316 is the selector switchs that are subjected to mode control signal ENAB control, can be for example switch, multiplexer etc.When mode control signal ENAB indication low-power mode, outlet selector 316 outputs are from the coded data of bus transition coder 312.When mode control signal ENAB indication normal mode, outlet selector 316 outputs are from the data of data buffer 311.Outlet selector 316 also can be implemented in the bus transition coder 312.
Virtual bit group selector 317 is and outlet selector 316 similar selector switchs.When mode control signal ENAB indication low-power mode, virtual bit group selector 317 makes the virtual hyte from virtual hyte generator 314 be imported into ECC scrambler 313.When mode control signal ENAB indication normal mode, virtual bit group selector 317 makes the J position hyte (fixing virtual hyte CONST) with fixed value be imported into ECC scrambler 313, makes that the virtual word in the ECC scrambler 313 comprises not through upset coded data, this J position hyte and possible filler.Virtual bit group selector 317 also can be implemented in the ECC scrambler 313.
Outlet selector 335 is and outlet selector 316 similar selector switchs.When mode control signal ENAB indication low-power mode, outlet selector 335 outputs are from the decoded data of bus upset demoder 331.When mode control signal ENAB indication normal mode, outlet selector 335 outputs are from the decoded data of ECC demoder 332.Outlet selector 335 also can be implemented in bus upset demoder 331 or the ECC demoder 332.
Hyte selector switch 334 is and outlet selector 316 similar selector switchs.When mode control signal ENAB indication low-power mode, hyte selector switch 334 makes with reference to virtual hyte REF and is imported into ECC demoder 332.When mode control signal ENAB indication normal mode, hyte selector switch 334 makes above-mentioned J position hyte (fixing virtual hyte CONST) with fixed value be imported into ECC demoder 332, makes that the virtual word in the ECC demoder 332 comprises data, this J position hyte and the possible filler that is received from bus.Hyte selector switch 334 also can be implemented in the ECC demoder 332.
Should be noted that hyte selector switch 334 can be omitted when the virtual hyte REF of reference is identical with fixing virtual hyte CONST.
Under most conditions of work, the frequency that mistake takes place in the data bus transmission is very low.Therefore, under normal conditions, the ability of an error detection just can satisfy the minimum requirements of data bus transmission reliability, and higher error correction and error detecing capability in fact have been wasted.The embodiment that describes with reference to Fig. 6 then can avoid this waste.
Though be that example illustrates embodiments of the invention with the data bus I/O between processor and the storer in the description in front, yet data bus scrambler of the present invention and data bus demoder are applicable to any functional unit that carries out I/O by data bus.In addition, these functional units can be on same chip, also can be on different chips.Data bus scrambler and data bus demoder can be in functional units, or separate with it.
Though the situation at unidirectional I/O in the description has in front illustrated embodiments of the invention, however data bus scrambler of the present invention and data bus demoder can be incorporated in the same functional unit, to realize two-way I/O.
In addition, data bus scrambler of the present invention and parts thereof, data bus demoder and parts thereof, the condition detector can be by realizing based on hardware (for example logical circuit, FPGA (Field Programmable Gate Array) etc.), software (for example program of moving on the processing unit) or the mode of its combination.
Therefore, though by concrete structure example embodiments of the invention are described in the description in front, data bus scrambler of the present invention and data bus demoder are not limited to described concrete structure.In fact in data bus scrambler of the present invention and data bus demoder, can make up arbitrarily each parts as required.Similarly, be in the processor though in the description in front the condition detector is exemplified as, yet the condition detector can be arranged in any position that obtains Report of Discrepancy of bus system.For example, the condition detector can be implemented in the Memory Controller or as unit independently, obtains Report of Discrepancy by zone bit, interruption, signal wire etc., and to the data bus encoder control signal that supplies a pattern.In addition, the condition detector can respond from the external control of switch, button, operating system, application program or the like and the switch mode control signal.
With reference to specific embodiment the present invention has been described in the instructions in front.Yet those of ordinary skill in the art understands, and can carry out various modifications and change under the prerequisite that does not depart from the scope of the present invention that proposes as following claims.
Claims (23)
1. data bus scrambler comprises:
Bus transition coder is configured to treat coded data according to predetermined bus upset encoding scheme and carries out bus upset coding, to produce coded data and upset indication information;
Virtual hyte generator is configured to convert described upset indication information to virtual hyte according to predictive encoding mapping; With
The error correcting and detecting scrambler is configured to according to being scheduled to the error correcting and detecting sign indicating number that the error correcting and detecting encoding scheme generates virtual word, and the error detection figure place of described predetermined error correcting and detecting encoding scheme is Duoed one at least than the error correction figure place,
Wherein, the mapping of described predictive encoding make the institute of described virtual hyte might value and according to described predictive encoding shine upon change less than the virtual hyte of reference between Hamming distance be fixed value and the error correction figure place that is not more than described predetermined error correcting and detecting encoding scheme, and
Wherein, described virtual word comprise described coded data and with the corresponding virtual hyte of described coded data, and if have unappropriated one or more other position, then described one or more other position fixed values of respectively asking in the described virtual word.
2. data bus scrambler as claimed in claim 1 also comprises:
Outlet selector is configured to control described data bus scrambler and export described data to be encoded when mode control signal indication normal mode; When mode control signal indication low-power mode, control described data bus scrambler and export described coded data; With
The virtual bit group selector is configured to control, and makes that described virtual word comprises described data to be encoded and fixing virtual hyte when mode control signal indication normal mode; When mode control signal indication low-power mode, described virtual word comprise described coded data and with the corresponding virtual hyte of described coded data.
3. data bus scrambler as claimed in claim 1 or 2, the ability of wherein said predetermined error correcting and detecting encoding scheme are at least two error detections of an error correction.
4. data bus scrambler as claimed in claim 1 or 2, the coding that wherein said predetermined error correcting and detecting encoding scheme is adopted are selected from the group that comprises Hamming code and best strange weighted code.
5. data bus scrambler as claimed in claim 1 or 2, wherein said predictive encoding mapping comprises the one-hot coding.
6. data bus scrambler as claimed in claim 1 or 2, wherein said predetermined error correcting and detecting encoding scheme is the best strange weighted code of two error detections of an error correction, described predictive encoding is mapped as 64 one-hot codings, described data to be encoded are 64, and described predetermined bus upset encoding scheme is divided into 6 hytes to carry out bus upset coding respectively with described data to be encoded.
7. data bus scrambler as claimed in claim 2 also comprises the bus state detector, is used to calculate the occurrence frequency of the error correcting and detecting verification mistake of the data bus data transmission that can not correct, and determines described mode control signal according to described occurrence frequency.
8. data bus scrambler as claimed in claim 7, wherein the bus state detector is configured to determine described occurrence frequency according to the environmental baseline of data bus.
9. data bus demoder comprises:
The error correcting and detecting demoder, be configured to virtual word be carried out verification according to predetermined error correcting and detecting encoding scheme with the corresponding error correcting and detecting sign indicating number of input data, the error detection figure place of described predetermined error correcting and detecting encoding scheme is Duoed one at least than the error correction figure place, described virtual word comprises described input data and the virtual hyte of reference, if and have unappropriated one or more other position, then described one or more other position fixed values of respectively asking in the described virtual word;
Upset indication information generator, be configured to convert the upset indication information to according to the predetermined decoding mapping hyte that position in the virtual word of verification is corresponding with the virtual hyte of described reference, the virtual hyte of wherein said reference can not be changed according to described predetermined decoding mapping, and according to the mapping of described predetermined decoding, the hyte that is converted might value and the virtual hyte of described reference between Hamming distance be fixed value and the error correction figure place that is not more than described predetermined error correcting and detecting encoding scheme; With
Bus upset demoder is configured to according to described upset indication information the data that will decode accordingly be carried out bus upset decoding.
10. data bus demoder as claimed in claim 9 also comprises:
Outlet selector is configured to when mode control signal indication normal mode, control described data bus demoder output through in the described virtual word of described error correcting and detecting demoder verification with the corresponding data of described input data; When mode control signal indication low-power mode, control the data that described data bus demoder output produces through described bus upset decoder decode; With
The hyte selector switch is configured to control, and makes that described virtual word comprises described input data and the virtual hyte of described reference when mode control signal indication low-power mode; When mode control signal indication normal mode, described virtual word comprises described input data and fixing virtual hyte, and the virtual hyte of wherein said reference is different from described fixing virtual hyte.
11. data bus demoder as claimed in claim 9 also comprises:
Outlet selector is configured to when mode control signal indication normal mode, control described data bus demoder output through in the described virtual word of described error correcting and detecting demoder verification with the corresponding data of described input data; When mode control signal indication low-power mode, control the data that described data bus demoder output produces through described bus upset decoder decode, wherein when mode control signal indication low-power mode, described virtual word comprises described input data and the virtual hyte of described reference; When mode control signal indication normal mode, described virtual word comprises described input data and fixing virtual hyte, and the virtual hyte of wherein said reference is identical with described fixing virtual hyte.
12. as claim 9 or 10 described data bus demoders, the ability of wherein said predetermined error correcting and detecting encoding scheme is at least two error detections of an error correction.
13. as claim 9 or 10 or 11 described data bus demoders, the coding that wherein said predetermined error correcting and detecting encoding scheme is adopted is selected from the group that comprises Hamming code and best strange weighted code.
14. as claim 9 or 10 or 11 described data bus demoders, wherein said predetermined decoding mapping comprises the one-hot coding.
15. as claim 9 or 10 described data bus demoders, wherein said predetermined error correcting and detecting decoding scheme is the best strange weighted code of two error detections of an error correction, described predetermined decoding is mapped as 64 one-hot codings, the described data that will decode are 64, and the described data that will decode are divided into 6 hytes to carry out bus upset decoding respectively.
16. data bus demoder as claimed in claim 10, also comprise the bus state detector, be used to calculate the occurrence frequency of the error correcting and detecting verification mistake of the data bus data transmission that can not correct, and determine described mode control signal according to described occurrence frequency.
17. data bus demoder as claimed in claim 16, wherein the bus state detector is configured to determine described occurrence frequency according to the environmental baseline of data bus.
18. data bus demoder as claimed in claim 9, the wherein said data that will decode are described input data, and described Hamming distance equals the error correction figure place of described predetermined error correcting and detecting encoding scheme.
19. the coding method of a data bus comprises:
Treat coded data according to predetermined bus upset encoding scheme and carry out bus upset coding, to produce coded data and upset indication information;
Mapping converts described upset indication information to virtual hyte according to predictive encoding; With
According to being scheduled to the error correcting and detecting sign indicating number that the error correcting and detecting encoding scheme generates virtual word, the error detection figure place of described predetermined error correcting and detecting encoding scheme is Duoed one at least than the error correction figure place,
Wherein, the mapping of described predictive encoding make the institute of described virtual hyte might value and according to described predictive encoding shine upon change less than the virtual hyte of reference between Hamming distance be fixed value and the error correction figure place that is not more than described predetermined error correcting and detecting encoding scheme, and
Wherein, described virtual word comprise described coded data and with the corresponding virtual hyte of described coded data, and if have unappropriated one or more other position, then described one or more other position fixed values of respectively asking in the described virtual word.
20. the coding/decoding method of a data bus comprises:
According to predetermined error correcting and detecting encoding scheme with the corresponding error correcting and detecting sign indicating number of input data virtual word is carried out verification, the error detection figure place of described predetermined error correcting and detecting encoding scheme is Duoed one at least than the error correction figure place, described virtual word comprises described input data and the virtual hyte of reference, if and have unappropriated one or more other position, then described one or more other position fixed values of respectively asking in the described virtual word;
Convert the upset indication information to according to the predetermined decoding mapping hyte that position in the virtual word of verification is corresponding with the virtual hyte of described reference, the virtual hyte of wherein said reference can not be changed according to described predetermined decoding mapping, and according to the mapping of described predetermined decoding, the hyte that is converted might value and the virtual hyte of described reference between Hamming distance be fixed value and the error correction figure place that is not more than described predetermined error correcting and detecting encoding scheme; With
According to described upset indication information the data that will decode are accordingly carried out bus upset decoding.
21. a data highway system comprises:
The bus transmitting apparatus comprises data bus scrambler as claimed in claim 1;
The bus interface receiving unit comprises data bus demoder as claimed in claim 9; With
Data bus connects described bus transmitting apparatus and bus interface receiving unit.
22. data highway system as claimed in claim 21, wherein said data bus scrambler also comprises:
Outlet selector is configured to control described data bus scrambler and export described data to be encoded when mode control signal indication normal mode; When mode control signal indication low-power mode, control described data bus scrambler and export described coded data; With
The virtual bit group selector is configured to control, and makes that described virtual word comprises described data to be encoded and fixing virtual hyte when mode control signal indication normal mode; When mode control signal indication low-power mode, described virtual word comprise described coded data and with the corresponding virtual hyte of described coded data,
Described data bus demoder also comprises:
Outlet selector is configured to when mode control signal indication normal mode, control described data bus demoder output through in the described virtual word of described error correcting and detecting demoder verification with the corresponding data of described input data; When mode control signal indication low-power mode, control the data that described data bus demoder output produces through described bus upset decoder decode; With
The hyte selector switch is configured to control, and makes that described virtual word comprises described input data and the virtual hyte of described reference when mode control signal indication low-power mode; When mode control signal indication normal mode, described virtual word comprises described input data and described fixing virtual hyte, and the virtual hyte of wherein said reference is different from described fixing virtual hyte.
23. data highway system as claimed in claim 22 also comprises the bus state detector, is used to calculate the occurrence frequency of the error correcting and detecting verification mistake of the data bus data transmission that can not correct, and determines described mode control signal according to described occurrence frequency.
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| CN101848059B (en) * | 2010-04-09 | 2013-08-14 | 西安电子科技大学 | Adaptive time coding/decoding device for inhibiting bus interference and coding/decoding method thereof |
| US9189051B2 (en) * | 2012-12-14 | 2015-11-17 | International Business Machines Corporation | Power reduction by minimizing bit transitions in the hamming distances of encoded communications |
| US9842020B2 (en) | 2014-11-26 | 2017-12-12 | Qualcomm Incorporated | Multi-wire symbol transition clocking symbol error correction |
| US9800271B2 (en) * | 2015-09-14 | 2017-10-24 | Qualcomm Incorporated | Error correction and decoding |
| TWI631830B (en) * | 2016-12-30 | 2018-08-01 | 慧榮科技股份有限公司 | Decoding method and related apparatus |
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| US5694405A (en) * | 1995-03-23 | 1997-12-02 | Kabushiki Kaisha Toshiba | Encoder and decoder of an error correcting code |
| CN2641931Y (en) * | 2003-09-24 | 2004-09-15 | 中国电子科技集团公司第五十四研究所 | Multifunctinoal programable asychronous transmission mode source unit interface module |
| CN1896959A (en) * | 2005-07-12 | 2007-01-17 | 中国科学院空间科学与应用研究中心 | Encoder for correcting static data storage fault |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5694405A (en) * | 1995-03-23 | 1997-12-02 | Kabushiki Kaisha Toshiba | Encoder and decoder of an error correcting code |
| CN2641931Y (en) * | 2003-09-24 | 2004-09-15 | 中国电子科技集团公司第五十四研究所 | Multifunctinoal programable asychronous transmission mode source unit interface module |
| CN1896959A (en) * | 2005-07-12 | 2007-01-17 | 中国科学院空间科学与应用研究中心 | Encoder for correcting static data storage fault |
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