CN103036739B - Formalization method for verification and performance analysis of high reliable communication system - Google Patents

Formalization method for verification and performance analysis of high reliable communication system Download PDF

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CN103036739B
CN103036739B CN201210533633.XA CN201210533633A CN103036739B CN 103036739 B CN103036739 B CN 103036739B CN 201210533633 A CN201210533633 A CN 201210533633A CN 103036739 B CN103036739 B CN 103036739B
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model
method
module
verification
state
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CN103036739A (en
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李晓娟
关永
施智平
王瑞
张�杰
赵春娜
华伟
董玲玲
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首都师范大学
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Abstract

Provided is a formalization method for verification and performance analysis of a high reliable communication system. The formalization method includes five steps. The formalization method is a method for communication system formal verification and analysis based on the combination of model testing and theorem proving. Based on the method of hypothesis guarantee, an environmental state machine is established to achieve layering modeling for design of a network communication system, the formal verification for determinant attributes is achieved, high order logical formalization with a random variable statistic character is achieved for protocol transmission processes and the method and design of attributive high order logical formal modeling, and based on the high-order logic model and the correlation theorem which are established on HOL4, automatic verification and dynamic performance analysis based on the formal model are achieved. The formalization method has good practical value and wide application prospects in the technical field of formal verification engineering.

Description

A kind of formalization method for high reliable communication system verification and performance evaluation

Technical field

The present invention relates to a kind of formalization method for high reliable communication system verification and performance evaluation, it is the reliability demonstration (Reliability of Communication in embedded system, Maintainability and Supportability, be called for short RMS) with the integrated implementation method of performance evaluation, particularly based on checking and the system quantifies performance evaluation integrated process construction method of formalization method, belong to Formal Verification engineer applied technical field.

Background technology

In the SOC (system on a chip) of many key application, communication system has the requirements such as high functional reliability, hard real time usually.The SOC (system on a chip) of crucial application lost efficacy and causes the example of life and property heavy losses piece to be lifted very; The method of inspection that SOC (system on a chip) is traditional is test or fault simulation, and its main limitation is to have passed test to data-oriented collection, but can not ensure not make a mistake to other input in actual motion; And be difficult to the potential unreasonable design of discovery system or implicit mistake.The system that how to ensure meets given function simultaneously and nonfunction requirement is one of key issue studied in highly reliable upper calculating field always.Based on formal method communication system correctness verified and performance evaluation will to guarantee chip-on communication system correctness and reliability significant.Transfer of data or extensive use that is concurrent, distributed process is realized towards SOC (system on a chip), and the Formal Verification of the functional attributes of these application all adopts the method for model testing usually, but because Model Checking abstraction hierarchy is lower, qualitative reaction can only be carried out, if abstract improper or agreement is more complicated, be easy to cause state too much, the even problem of state explosion.At present its correctness only being verified to the formalization method of network communicating system, if realize quantitative analysis, then being undertaken by setting up simulation model.

Summary of the invention

1, object: the object of this invention is to provide a kind of formalization method for high reliable communication system verification and performance evaluation, it is a kind of based on model testing and theorem proving the form of communications system chemical examination card combined and the method analyzed.Intend the method ensured based on hypothesis, set up ambient condition machine, hierarchical modeling is carried out to the design of network communicating system, Formal Verification is carried out to determinant attribute, the higher-order logic Formal Modeling of the transmitting procedure of agreement, attribute, design are realized to the higher-order logic formalization of stochastic variable statistical nature, and based on the higher-order logic model set up at HOL4 and correlation theorem, realize automatic Verification and the quantification Dynamic Performance Analysis based on formal model.

2, technical scheme: to achieve these goals, a kind of formalization method for high reliable communication system verification and performance evaluation of the present invention, the method concrete steps are as follows:

Step one: analyzing communication system SOC functional realiey structure, and extract crucial functional module; Carry out authentication module decomposition, modeling.Higher-order logic theorem proving and symbol model verify are combined, carries out combining form chemical examination card.

Step 2: the interface attributes between module, I/O mouth and physical layer function are realized, Formal Verification is carried out by the method for model testing, based on symbolic Model verifying bench, realize by interface attributes, I/O mouth and the physical layer function between Model Checking authentication module by different level.

Step 3: the problem that state may be caused too much for sophisticated functions module, carries out stratification abstract, theoretical based on hypothesis-guarantee, sets up ambient condition machine model, carries out combined authentication strategy.

Step 4: the checking by the method for theorem proving, data communication protocol, Parallel application process being carried out to logic, functional realiey.Based on higher-order logic, Formal Representation is carried out to SOC (system on a chip) tense attribute and random behavior;

Step 5: in the logic analysis expression parsing of system, the mathematical logic form of extraction system process statistical property expresses function, realizes the dynamic quantization performance evaluation of identifying object process.

Wherein, " the functional module that extraction is crucial described in step one; Carry out authentication module decomposition, modeling; Higher-order logic theorem proving and symbolic model checking are combined, carries out combining form chemical examination card; " its specific implementation process is as follows: extract modules such as the transmission in communication system, reception, link management, error control, flow controls, carry out the division of authentication module, contrast Protocol Design specification, extracts target and the sub-goal of checking.Function comparatively independently module abstracts is independent Verification Components, lower coupling module interface is carried out abstract modeling and state description; Set up the state machine model of sending/receiving controller, form the formalized model of system, adopt the method for model testing to verify.To processes such as Data Transport Protocol and parallel distributed components on HOL4 platform, set up higher-order logic model, adopt the method for theorem proving to verify.

Wherein, described in step 3 " carry out stratification abstract, theoretical based on hypothesis-guarantee, set up ambient condition machine model, carry out combined authentication strategy; " its specific implementation process is as follows: the problem that the state produced when the sophisticated functions attribute be coupled into for multiple module-cascade is verified is too much, adopt hypothesis to ensure the method for reasoning, abstract ambient condition machine, carries out with different levels checking to whole system.Suppose to ensure that reasoning process is as follows:

If two subsystems S1, S2 have attribute: (1) S1 meets Property P 1(2) when the environment of S2 meets Property P 1, S2 meets Property P 2.So the combination S 1||S2 of subsystem S1 and S2 meets Property P 2.The advantage of carrying out in this way verifying is: need not set up state machine to the combination of S1 and S2 and verify, only need verify P1 with S2, then abstract for the hypothesis P1 environment for S2 is verified P2.Suppose that P1 with S1 compares, state space lacks a lot, is conducive to processing large-scale Circuits System.The present invention is by above step, give the method for a kind of form of communications system chemical examination card model testing and theorem proving two kinds of formalization methods combined with performance evaluation, provide the comparatively general flow and method corresponding to form of communications system chemical examination card simultaneously.

3, advantage and effect: major advantage of the present invention is: the formalization verification method that the stratification under different abstraction level of the communication system of a kind of SOC is provided, and the performance evaluation realizing system concurrency attribute.Realize the comparatively general communication system functionality correctness of SOC and the automatic Verification technology of fail-safe analysis, the designer being convenient to SOC can find leak or the logic error of system design stage in early days.

Accompanying drawing explanation

The form of communications system chemical examination card that Fig. 1 combines based on model testing and theorem proving realizes overall diagram with the method analyzed

Fig. 2 is FB(flow block) of the present invention

Fig. 3 is typical SOC system model inspection checking implementing procedure template

Fig. 4 is the flow template of the higher-order logic theorem proving of typical SOC system

Fig. 5 is for sending control module state transition diagram

Embodiment

For making feature of the present invention and advantage obtain clearer understanding, below in conjunction with accompanying drawing, be described in detail below: Fig. 1 describes the overall architecture that the present invention realizes.

When SOC designer carries out behavior, function accuracy checking to chip-on communication system that is designed or that realize, a kind of formalization verification method of the present invention can realize system and verifies at the attribute of different abstraction hierarchy and based on set up formalized model, carry out performance evaluation:

See Fig. 2, a kind of formalization verification method for high reliable communication systematic function Inspection and Analysis of the present invention, its concrete implementation step is:

Step one: Analytical System Design, carries out checking and decomposes.As shown in Figure 2, according to systemic-function, implementation feature, carry out the decomposition of validation task.

(1) attribute of each key modules of labor or process, functional description and realization thereof, extract target and the sub-goal of checking,

(2) carry out the division of system function module and the abstract of checking attribute thereof, by function comparatively independently module abstracts be independent Verification Components, lower coupling module interface is carried out abstract modeling and state description, sets up abstract state machine.

(3) higher-order logic model is set up to processes such as Data Transport Protocol and parallel distributed components, adopts the method for theorem proving to verify,

(4) for function comparatively independently assembly and low coupling module interface, this project is intended adopting the method for model testing to verify.

Step 2: the interface attributes between module, I/O mouth and physical layer function are realized, Formal Verification is carried out by the method for model testing, based on symbol model verify platform, realize by interface attributes, I/O mouth and the physical layer function between Model Checking authentication module by different level.The process of model testing comprises modeling, the description of character and automatic Verification three processes, as shown in Figure 3, realizes carrying out abstract and Formal Representation, use the finite state space of the Kripke representation system of 5 tuples to the system of identifying object module; With the attribute calculating the expectation of tree temporal logic (CTL) descriptive system, this process need describes accurately, avoids ambiguity.Utilize symbol model verify instrument SMV (the Symbolic Modeling Verifier) attribute that proof by exhaustion is expected automatically whether to set up on state space, if set up, then illustrate that design realization meets the desired attribute.If be false, then export counter-example, can again according to emulation testing, Wrong localization.This can be one and verify → report an error → cyclic process of error message analysis and model modification → verify again.Such as, in Fig. 5, transmitter is in wait state in the reset state, (1) if from the Tick_IN(request transmission time code of host computer system) signal is high, and have sent ESC signal (namely ESC_Gone_internal signal is for high), then transmitter can arrive locking time code state (Provide_TimeCode is set to 1 in this case, send transmitter register submodule to), then unconditional arrival transmitting time code state .(2) if Send_FCT(is from control module) be 1 and EightMore=1(illustrates that receiver has more than the space of 8 to store data) and if ESC_Gone_internal=0(ESC_Gone_internal=1, then ESC+FCT is a null character (NUL)), so transmitter can arrive locking flow control flag state (Provide_FCT is set to 1 in this case, send transmitter register submodule to), then unconditional arrival sends normal character mode.(3) if Send_NULL(is from control module)=1 and ESC_Gone_internal=1, so transmitter can arrive locking flow control flag state (Provide_FCT is set to 1 in this case, sends transmitter register submodule to).(4) if Send_All(is from control module)=1 and NoCredit=0, so transmitter can arrive locking flow control flag state, (Provide_ESC is set to 1 in this case, sends transmitter register submodule to).(5) if Send_EEP=1, so transmitter can arrive locking erroneous packets end mark state, (Provide_EEP is set to 1 in this case, sends transmitter register submodule to).(6) if Send_EOP=1, so transmitter can arrive the correct end-of-packet flag states of locking, (Provide_EOP is set to 1 in this case, sends transmitter register submodule to).(7) if Send_NChar_Flag=1, so transmitter can arrive the normal character mode of locking, (Provide_NChar is set to 1 in this case, sends transmitter register submodule to).

The implication of some main input variables in figure:

1 protocol specification must meet alternative, because there is the problem of priority, so timing code, normal character and flow control flag can not send simultaneously.

Property 1:assert G~(!TX_Reset&Provide_TimeCode&Provide_NChar&Provide_FCT);

Have the relation of priority between 2 characters sent, so must verify the problem of priority, character 2 represents when to want transmitting time code and FCT simultaneously, preferential transmitting time code.

Property2:SPEC AG(!TX_Reset&TX_ClockEnable&(Tick_IN&ESC_Gone_internal)&(Send_FCT&EightMore&!ESC_Gone_internal)->AF Provide_TimeCode);

3 according to protocol specification, whether each state that the character verified relates generally in state transitions can enter corresponding state and under corresponding state, output signal whether meet protocol specification requirements after condition meets, and extracts altogether 7 computational tree logic formula character according to demand.

Property3:SPEC AG(AG Send_NChar_Flag->AF present_state=1&AF present_state=2&AF Provide_NChar&AF NCharOnTrip&AF DCReg_Read);

Property4:SPEC AG(AG ESC_Gone_internal->AF present_state=3&AF present_state=4&AF Provide_TimeCode);

Property5:SPEC AG(AG Send_FCT->AF present_state=5&AF present_state=9&AFpresent_state=10&AF Provide_FCT);

Property6:SPEC AG (AG Send_EOP->AF present_state=6&AF present_state=9&AFpresent_state=10&AF Provide_EOP&AF DCReg_Read&AF NCharOnTrip);

Property7:SPEC AG(AG Send_EEP->AF present_state=7&AF present_state=9&AFpresent_state=10&AF Provide_EOP&AF DCReg_Read&AF NCharOnTrip);

Property8:SPEC AG (AG Send_NULL->AF_present_state=8&AF present_state=9&AFpresent_state=10&AF Provide_ESC);

Mainly verify with formula Property3 to the Property8 of upper part and to send after control module when sending request to enter, can whether control module enter corresponding state and export corresponding transmitting control signal in this condition, and whether can return the initial condition resetting and reset after entering these states.

Property9:SPEC AG(AG(!ESC_Gone_internal&Send_FCT&EightMore&present_state=5)->AF EightMoreAcknowledge);

The reception buffering that computational tree logic formula Property9 have expressed host A also has space-reception data, request transmission current control symbol FCT is to the host B of transmitting terminal, at this moment A hold the transmission control module of main frame to produce register that a confirmation control code that can receive unnecessary eight normal characters gives transmitter, finally sends a FCT identifier to main frame.

Step 3: after verifying respectively the local attribute of modules, will test to the global property of intermodule combination.When the sophisticated functions attribute be coupled into for multiple module-cascade is verified, there will be the problems such as state is too much, adopt and ensure inference method to carry out, set up ambient condition machine, and identifying object is communicated with ambient condition machine abstract based on hypothesis.Such as, sending/receiving device buffer memory is abstracted into the memory interface etc. of data character.In connected state, transmitter export data and filtering signal should meet DS coding.If the value of continuous two bits of data-signal is identical, the state of filtering signal after transport a bit time change, otherwise filtering signal remains unchanged in these two bit-time.The prerequisite that this character is set up is flow control signal Provide_FCT is true; this is controlled by controller; therefore; increase the hypothesis P1 of a relevant contexts; in connection status; link keep-alive and flow control label must have one to be true, and such guarantee in this case Provide_FCT is true.By checking, controller N meets Property P 1, then transmitter module is embedded in the environment meeting above-mentioned hypothesis, just can detect the correctness of this character by the method for modelling verification.And the problem avoiding state too much.

Step 4: theorem proving derives based on the axiom of formal logical system the character that system has.It can dependency structure induction technique at the enterprising line justification of infinite field, can directly process unlimited state space, so just greatly can reduce the status number of a pattern checking device Water demand.It is strong that higher-order logic theorem prover HOL4 has ability to express, type polymorphism feature and had the fundamental theorem storehouse of suitable embedding ML function, utilize HOL4 can in the above-mentioned first step divide module attribute verify, its basic process as shown in Figure 4, formalized model to be verified is with in object form input HOL, this model carries out the task division of sub-goal in HOL interactive, the correctness of the proof procedure of the proof check system meeting each subtask of automatic inspection of HOL4, in this process, the new theorem needing to use and description all first will be set up formalized model and add in HOL4 by us, reusable by the theorem interpolated, very convenient like this reusability with theorem in verification tool and modular Formal Verification.This project plan carries out formalized description to statistical attributes such as the variances of discrete random variable, first sets up formalized model and adds in HOL4; Proof is completed to the variance attribute required for follow-up random attribute quantitative description and performance evaluation, adds in HOL4 as theorem.

In HOL4, set up host-host protocol logical model, and carry out reasoning checking:

1) in HOL4 for transmitting data information, control information, transmission time, bag number define data type respectively;

2) be respectively the transmission of channel and communicating pair, receiving process sets up higher-order logic predicate (function) expression formula;

Step 5: Formal Representation agreement initial condition and constraints in HOL4, and be expressed as with the predicate function in the 4th step expression formula of extracting.Host-host protocol is by with sending packet to receiving the time of confirmation whether in the scope of expection, judges whether data are correctly transmitted, and employing makes mistakes and adds retransmission mechanism and carry out error correction.If the probability of makeing mistakes is p, the number of times that channel retransmits is index fraction cloth, then data transmission delay can be expressed as:

D=t r+d tran+d prog+(t r+t timer)(G (1p)-1)

T r: resend data time,

T timer: transmit leg from the Packet Generation complete time to time-out,

D tran: Packet Generation required time

D prog: signal is in propagated between nodes time delay

If G in above formula xthe probability that Gaussian distributed stochastic variable successfully sends is x.

The time delay average then transmitting a packet can be expressed as:

((t r+ t timer) p/ (1-p))+t r+ d tran+ d prog: utilize stochastic variable and statistical attribute theorem thereof in HOL4 to carry out expression sum functions to agreement time delay and extract, and realize performance evaluation.

Claims (1)

1., for a formalization method for high reliable communication system verification and performance evaluation, it is characterized in that: the method concrete steps are as follows:
Step one: analyzing communication system SOC functional realiey structure, and extract crucial functional module, carry out authentication module decomposition, modeling, higher-order logic theorem proving and symbol model verify are combined, carry out combining form chemical examination card;
Step 2: the interface attributes between module, I/O mouth and physical layer function are realized, Formal Verification is carried out by the method for model testing, based on symbolic Model verifying bench, realize by interface attributes, I/O mouth and the physical layer function between Model Checking authentication module by different level;
Step 3: the problem that state may be caused too much for sophisticated functions module, carries out stratification abstract, theoretical based on hypothesis-guarantee, sets up ambient condition machine model, carries out combined authentication strategy;
Step 4: the checking by the method for theorem proving, data communication protocol, Parallel application process being carried out to logic, functional realiey; Based on higher-order logic, Formal Representation is carried out to SOC (system on a chip) tense attribute and random behavior;
Step 5: in the logic analysis expression parsing of system, the mathematical logic form of extraction system process statistical property expresses function, realizes the dynamic quantization performance evaluation of identifying object process;
Wherein, " extracting crucial functional module, carrying out authentication module decomposition, modeling, higher-order logic theorem proving and symbolic model checking are combined, carrying out combining form chemical examination card described in step one; " its specific implementation process is as follows: extract the transmission in communication system, reception, link management, error control, flow-control module, carry out the division of authentication module, contrast Protocol Design specification, extracts target and the sub-goal of checking; Function comparatively independently module abstracts is independent Verification Components, lower coupling module interface is carried out abstract modeling and state description; Set up the state machine model of sending/receiving controller, form the formalized model of system, adopt the method for model testing to verify; To Data Transport Protocol and parallel distributed component process on HOL4 platform, set up higher-order logic model, adopt the method for theorem proving to verify;
Wherein, described in step 3 " carry out stratification abstract, theoretical based on hypothesis-guarantee, set up ambient condition machine model, carry out combined authentication strategy; " its specific implementation process is as follows: the problem that the state produced when the sophisticated functions attribute be coupled into for multiple module-cascade is verified is too much, adopt hypothesis to ensure the method for reasoning, abstract ambient condition machine, carries out with different levels checking to whole system; Suppose to ensure that reasoning process is as follows: if two subsystems S1, S2 have attribute: (1) S1 meets Property P 1; (2) when the environment of S2 meets Property P 1, S2 meets Property P 2; So the combination S 1||S2 of subsystem S1 and S2 meets Property P 2; The advantage of carrying out in this way verifying is: need not set up state machine to the combination of S1 and S2 and verify, only need verify P1 with S2, then abstract for the hypothesis P1 environment for S2 is verified P2; Suppose that P1 with S1 compares, state space lacks a lot, is conducive to processing large-scale Circuits System.
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