CN106788878B - A kind of Parallel CRC error correction method with monobit errro correction function - Google Patents
A kind of Parallel CRC error correction method with monobit errro correction function Download PDFInfo
- Publication number
- CN106788878B CN106788878B CN201510824266.2A CN201510824266A CN106788878B CN 106788878 B CN106788878 B CN 106788878B CN 201510824266 A CN201510824266 A CN 201510824266A CN 106788878 B CN106788878 B CN 106788878B
- Authority
- CN
- China
- Prior art keywords
- crc
- data
- multinomial
- check
- transmission
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L1/00—Arrangements for detecting or preventing errors in the information received
- H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
- H04L1/0056—Systems characterized by the type of code used
- H04L1/0061—Error detection codes
Abstract
The present invention relates to fields of communication technology, and in particular to a kind of monobit errro correction method based on Parallel CRC.The low problem of the slow and data transmission efficiency based on packet loss, re-transmission of the operation that the slow serial CRC algorithm based on serial transmission of speed caused by a data line is limited to the purpose of the present invention is to solve transmission speed during serial data transmission.
Description
Technical field:
The present invention relates to fields of communication technology, and in particular to a kind of monobit errro correction method based on Parallel CRC.
Background technique:
The world today is an information-based world, and the information exchange of all trades and professions, exchange all can't do without communicating.The school CRC
It tests and has been widely used in Various types of data interaction as a kind of data pouch-type that soft and hardware is all easy to implement verification strategy,
However most of CRC algorithm is used for the verification of data.Data re-transmission or packet loss are replaced using data automatic error correction function,
Can effective improve data transfer network energy consumption and data transmission efficiency.And in the relatively good situation of environment,
Monobit errro correction suffers from the inherent advantage of oneself in terms of the reliability of the realization of soft and hardware and error correction.
Assuming that transmission process is p using binary coding mode and the bit error rate, the data volume of a packet number is n bits, then passes
The correct probability of complete package data is (1-p) during defeatedn, then the probability of data transmission fault is Pe=1- (1-p)n.And it transmits
Occurring the probability that mistake is single-bit error in the process is Pe1=Cn 1p(1-p)n-1.It is total so as to obtain single-bit error Zhan
The ratio of mistake is R=Pe1/Pe=np (1-p)n/(1-(1-p)n).It is calculated according to corresponding, it is available in bit error rate decline
In the case of, single-bit error accounts for the ratio that whole packet miscounts mistake and increases rapidly, especially when the bit error rate is lower than 10-4When, single-bit error
It accounts for the ratio that whole packet miscounts mistake and has been already higher than 90%, and when the bit error rate is lower than 10-6When, single-bit error accounts for whole packet and miscounts mistake
Ratio is already higher than 99.95% (it is that 1024bits is calculated that calculating here, which is according to packet length).Therefore, it can be seen that
When the bit error rate in message transmitting procedure is lower, the ratio that single-bit error accounts in whole packet mistake increases rapidly, calculation shows that,
It is lower than 10 in the bit error rate-6When, 3 orders of magnitude of Packet Error Ratio or more can be effectively reduced by monobit errro correction technology.
In order to improve the transmittability and processing capacity of data, parallel CRC algorithm, the introducing of monobit errro correction function are effective
Limited resource is utilized and improves data reliability and safety.
Summary of the invention:
A data line is limited to the purpose of the present invention is to solve transmission speed during serial data transmission to cause
Speed serial CRC algorithm slow, based on serial transmission operation it is slow and based on packet loss, re-transmission data transmission efficiency it is low
Problem.
The present invention is a kind of Parallel CRC error correction method with monobit errro correction function, comprising the following steps:
Step 1: it selects suitable CRC check multinomial, calculate corresponding parallel algorithm;
According to data transportation requirements and data packet length requirement, suitable CRC check multinomial CRC16.X25=X is selected16
+X12+X5+ 1, X in formulaiIt is the label of element position, it indicates corresponding position locating for the symbol value determined by its coefficient.
According to corresponding CRC check multinomial, 16 CRC concurrent operation formulas are obtained by interative computation
R [0]=D [12] ^D [11] ^D [8] ^D [4] ^D [0] ^R [0] ^R [4] ^R [8] ^R [11] ^R [12]
R [1]=D [13] ^D [12] ^D [9] ^D [5] ^D [1] ^R [1] ^R [5] ^R [9] ^R [12] ^R [13]
R [2]=D [14] ^D [13] ^D [10] ^D [6] ^D [2] ^R [2] ^R [6] ^R [10] ^R [13] ^R [14]
R [3]=D [15] ^D [14] ^D [11] ^D [7] ^D [3] ^R [3] ^R [7] ^R [11] ^R [14] ^R [15]
R [4]=D [15] ^D [12] ^D [8] ^D [4] ^R [4] ^R [8] ^R [12] ^R [15]
R [5]=D [13] ^D [12] ^D [11] ^D [9] ^D [8] ^D [5] ^D [4] ^D [0] ^R [0] ^R [4] ^R [5] ^R [8] ^
R[9]^R[11]^R[12]^R[13]
R [6]=D [14] ^D [13] ^D [12] ^D [10] ^D [9] ^D [6] ^D [5] ^D [1] ^R [1] ^R [5] ^R [6] ^R [9]
^R[10]^R[12]^R[13]^R[14]
R [7]=D [15] ^D [14] ^D [13] ^D [11] ^D [10] ^D [7] ^D [6] ^D [2] ^R [2] ^R [6] ^R [7] ^R
[10]^R[11]^R[13]^R[14]^R[15]
R [8]=D [15] ^D [14] ^D [12] ^D [11] ^D [8] ^D [7] ^D [3] ^R [3] ^R [7] ^R [8] ^R [11] ^R
[12]^R[14]^R[15]
R [9]=D [15] ^D [13] ^D [12] ^D [9] ^D [8] ^D [4] ^R [4] ^R [8] ^R [9] ^R [12] ^R [13] ^R
[15]
R [10]=D [14] ^D [13] ^D [10] ^D [9] ^D [5] ^R [5] ^R [9] ^R [10] ^R [13] ^R [14]
R [11]=D [15] ^D [14] ^D [11] ^D [10] ^D [6] ^R [6] ^R [10] ^R [11] ^R [14] ^R [15]
R [12]=D [15] ^D [8] ^D [7] ^D [4] ^D [0] ^R [0] ^R [4] ^R [7] ^R [8] ^R [15]
R [13]=D [9] ^D [8] ^D [5] ^D [1] ^R [1] ^R [5] ^R [8] ^R [9]
R [14]=D [10] ^D [9] ^D [6] ^D [2] ^R [2] ^R [6] ^R [9] ^R [10]
R [15]=D [11] ^D [10] ^D [7] ^D [3] ^R [3] ^R [7] ^R [10] ^R [11]
Wherein, R represents the numerical value in corresponding registers, and D represents the numerical value of corresponding input data, and ^ indicates XOR operation.
Step 2: look-up table is established;
If G (X) is the check polynomial of CRC, k is the length for transmitting data, and n is the length for sending data, then check bit
Length be n-k.At this point, setting the multinomial for sending data as v (x), error of transmission data polynomial is e (x) and receives data
Multinomial is r (x), and there are following relationships between them
R (x)=v (x)+e (x)
CRC check and calculating is enabled to be expressed as follows CRCG(x){ v (x) } is calculated in the case where G (x), v (x), n and k certain
It as a result should be one 0.In receiving end, calculated with identical CRC check multinomial, it is available to draw a conclusion
CRCG(x){ r (x) }=CRCG(x){ v (x)+e (x) }=CRCG(x){e(x)}
This illustrates the CRC check for obtaining different type of error mistakes if there is a suitable multinomial verification formula of CRC
As a result different between two, then the position of mistake occurs in data can be obtained by the CRC check result generated.
According to packet length and corresponding Parallel CRC arithmetic expression, crc value when everybody generation mistake of the length is calculated, and
The value is stored stand-by to corresponding memory space.
Step 3: correcting data error;
Corresponding CRC is added in transmission data through the above way, data are carried out using identical CRC in recipient
The resolving of CRC, if data in transmission process there is no error code, the CRC calculated should be 0;If the CRC calculated
Value is not zero, then is compared the value with the look-up table stored before, if matching is generated, by the correspondence position in look-up table
XOR operation is carried out with the corresponding position of data, correct data can be obtained after resolving;If not generating matching, illustrate data
The data transmission fault of unknown digit has occurred, it should abandon.
The present invention has the advantages that
(1) present invention uses 16 parallel-by-bit transmission modes and 16 parallel-by-bit CRC check operations, remains unchanged in working frequency
In the case where, transmission speed and operational capability effectively can be promoted to original 16 times.It is provided in only lift portion logic
Whole data transmission, processing capacity are effectively improved in the case where source;
(2) present invention replaces data packetloss, re-transmission using the error correction of data, can effectively improve the efficiency of transmission of data
And reliability, the data throughput capabilities of whole system can be effectively improved in this way;
(3) present invention uses monobit errro correction function, does so the Packet Error Ratio that can be effectively reduced under good environment, together
When can effectively reduce look-up table needed for storage space, reduce hardware spending.
Detailed description of the invention
Fig. 1 is step schematic diagram of the invention.
Fig. 2 is parallel CRC algorithm schematic diagram of the invention.
Subordinate list explanation
Table 1 is that single-bit error of the invention searches schematic table.
Specific embodiment
Below in conjunction with attached drawing and subordinate list, the present invention is described in further detail.
The present invention is a kind of Parallel CRC error correction method with monobit errro correction function, with reference to the accompanying drawing, to the present invention
Technical solution is described in detail.
Fig. 1 gives the specific schematic diagram of each step in the present invention, be specifically divided into the suitable CRC multinomial of selection,
Single-bit error look-up table and the several steps of correcting data error are established in parallel CRC algorithm operation.
The corresponding CRC check multinomial that required Parallel CRC digit is looked for from International Standards Organization, due to International Standards Organization
The error rate for the CRC multinomial covering given is higher than the multinomial that arbitrarily writes out, in conjunction with oneself be specifically designed to choose, this
In we choose CRC check multinomial CRC16.X25=X16+X12+X5+1。
As shown in Fig. 2, using parallel algorithm according to corresponding CRC check multinomial, first is first calculated in serial algorithm
Data in each register of theory of clock cycle;The number in each register of theory of second clock cycle is calculated again
According to;And so on, the data in each register of theory in the 16th period are calculated, this data is also last parallel output
Data, algorithm should also be final the parallel combined logical algorithm:
R [0]=D [12] ^D [11] ^D [8] ^D [4] ^D [3] ^R [0] ^R [4] ^R [8] ^R [11] ^R [12]
R [1]=D [13] ^D [12] ^D [9] ^D [5] ^D [1] ^R [1] ^R [5] ^R [9] ^R [12] ^R [13]
R [2]=D [14] ^D [13] ^D [10] ^D [6] ^D [2] ^R [2] ^R [6] ^R [10] ^R [13] ^R [14]
R [3]=D [15] ^D [14] ^D [11] ^D [7] ^D [3] ^R [3] ^R [7] ^R [11] ^R [14] ^R [15]
R [14]=D [15] ^D [12] ^D [8] ^D [4] ^R [4] ^R [8] ^R [12] ^R [15]
R [5]=D [13] ^D [12] ^D [11] ^D [9] ^D [8] ^D [5] ^D [4] ^D [0] ^R [0] ^R [4] ^R45] ^R [8] ^
R[9]^R[11]^R[12]^R[13]
R [6]=D [14] ^D [13] ^D [12] ^D [10] ^D [9] ^D [6] ^D [5] ^D [1] ^R [1] ^R [5] ^R [6] ^R [9]
^R[10]^R[12]^R[13]^R[14]
R [7]=D [15] ^D [14] ^D [13] ^D [11] ^D [10] ^D [7] ^D [6] ^D [2] ^R [2] ^R [6] ^R [7] ^R
[10]^R[11]^R[13]^R[14]^R[15]
R [8]=D [15] ^D [14] ^D [12] ^D [11] ^D [8] ^D [7] ^D [3] ^R [3] ^R [7] ^R [8] ^R [11] ^R
[12]^R[14]^R[15]
R [9]=D [15] ^D [13] ^D [12] ^D [9] ^D [8] ^D [4] ^R [4] ^R [8] ^R [9] ^R [12] ^R [13] ^R
[15]
R [10]=D [14] ^D [13] ^D [10] ^D [9] ^D [5] ^R [5] ^R [9] ^R [10] ^R [13] ^R [14]
R [11]=D [15] ^D [14] ^D [11] ^D [10] ^D [6] ^R [6] ^R [10] ^R [11] ^R [14] ^R [15]
R [12]=D [15] ^D [8] ^D [7] ^D [4] ^D [0] ^R [0] ^R [4] ^R [7] ^R [8] ^R [15]
R [13]=D [9] ^D [8] ^D [5] ^D [1] ^R [1] ^R [5] ^R [8] ^R [9]
R [14]=D [10] ^D [9] ^D [6] ^D [2] ^R [2] ^R [6] ^R [9] ^R [10]
R [15]=D [11] ^D [10] ^D [7] ^D [3] ^R [3] ^R [7] ^R [10] ^R [11]
Respectively each bit-errors of data are set out to come respectively, and carry out corresponding Parallel CRC operation, it will be corresponding
The look-up table such as table 1 is established in operation, and opens up corresponding resource within hardware and corresponding data are stored to the storage sky opened up
Between, data are ranked up according to ascending order or descending and indicate single-bit error position in the data field.
It receives data and carries out corresponding CRC parallel computing operation, then by the value when crc value finally obtained is not 0
It is compared with the storage data of data field, due to being arranged using ascending order or descending, then it is not small for inquiring required number
In the integer of log2 (M), M is data length.If query result mistake, carries out packet loss or retransmit (due to digital ratio
Calculating before the percentage that spy accounts for packet mistake passes through is very high, and it is very big to carry out the storage space needed when more bit error corrections).
z1 | 16’hf0ba |
z2 | 16’hf049 |
z3 | 16’hf034 |
z4 | 16’h781a |
z5 | 16’h3c0d |
z6 | 16’h9616 |
z7 | 16’h4b0b |
z8 | 16’had95 |
...... | …… |
z1037 | 16’h8108 |
z1038 | 16’h4084 |
z1039 | 16’h2042 |
z1040 | 16’h1021 |
Table 1
Example 1
An inquiry table is initially set up, sets ' 1 ' for some bit in a bag data, other bits are all set
It is set to ' 0 ', calculate separately the numerical value of CRC in the case that different bits are ' 1 ' and places them in corresponding inquiry epitope
It sets for the inquiry after resolving later.Here z is setiThe case where for i-th of bit in data packet being ' 1 ', T [CRCG
(zi)] it is calculated CRC numerical value in the case that i-th of bit is ' 1 '.Illustrate to look into used here as a simply example
Look for how table generates, if CRC check multinomial is G=x3+ x+1 can be expressed as 1011, and the data of transmission are 4, this
In we need check bit of 3 CRC as data, then z1=1000000, we have CRC at this timeG(z1)=5, similarly we
Available CRCG(z2)=7, CRCG(z3)=6, CRCG(z4)=3, CRCG(z5)=4, CRCG(z6)=2 and CRCG(z7)=1.
If the operation result of any two CRC is not identical, one can consider that CRCGFor ziWith single mapping to get arriving
The available corresponding bit error message of corresponding CRC result.According to operation result above, we are available entangles
Wrong table T={ 5,7,6,3,4,2,1 } can determine single in recipient according to the value in final calculated CRC control error correction table
Bit occurs the position of mistake and carries out the error correction of corresponding error bit position.The CRC check position for being n for length, longest can be with
The data bit length having is L=2n-n-1。
Statement above is proved below by way of a specific example, it is assumed that the data of required transmission are M=1101,
CRC, i.e. CRC is calculatedG(1101)=001, then the data transmitted should be M '=1101001, it is assumed that in transmission process
In the second bit occur mistake, then the data received should be M "=1001001, calculated, can be obtained by CRC check
To CRCG(M ")=7 can be seen that T [2]=7 by tabling look-up, then illustrating that second bit of the data received occurs
Mistake, by correcting the bit-errors obtains correctly receiving data 1101001.
Claims (1)
1. a kind of Parallel CRC error correction method with monobit errro correction function, which is characterized in that
Step 1: it selects suitable CRC check multinomial, calculate corresponding parallel algorithm;
According to data transportation requirements and data packet length requirement, suitable CRC check multinomial CRC16.X25=X is selected16+X12+
X5+ 1, X in formulaiIt is the label of element position, it indicates corresponding position locating for the symbol value determined by its coefficient;According to
Corresponding CRC check multinomial, obtains 16 CRC concurrent operation formulas by interative computation
R [0]=D [12] ^D [11] ^D [8] ^D [4] ^D [0] ^R [0] ^R [4] ^R [8] ^R [11] ^R [12]
R [1]=D [13] ^D [12] ^D [9] ^D [5] ^D [1] ^R [1] ^R [5] ^R [9] ^R [12] ^R [13]
R [2]=D [14] ^D [13] ^D [10] ^D [6] ^D [2] ^R [2] ^R [6] ^R [10] ^R [13] ^R [14]
R [3]=D [15] ^D [14] ^D [11] ^D [7] ^D [3] ^R [3] ^R [7] ^R [11] ^R [14] ^R [15]
R [4]=D [15] ^D [12] ^D [8] ^D [4] ^R [4] ^R [8] ^R [12] ^R [15]
R [5]=D [13] ^D [12] ^D [11] ^D [9] ^D [8] ^D [5] ^D [4] ^D [0] ^R [0] ^R [4] ^R [5] ^R [8] ^R [9]
^R[11]^R[12]^R[13]
R [6]=D [14] ^D [13] ^D [12] ^D [10] ^D [9] ^D [6] ^D [5] ^D [1] ^R [1] ^R [5] ^R [6] ^R [9] ^R
[10]^R[12]^R[13]^R[14]
R [7]=D [15] ^D [14] ^D [13] ^D [11] ^D [10] ^D [7] ^D [6] ^D [2] ^R [2] ^R [6] ^R [7] ^R [10] ^R
[11]^R[13]^R[14]^R[15]
R [8]=D [15] ^D [14] ^D [12] ^D [11] ^D [8] ^D [7] ^D [3] ^R [3] ^R [7] ^R [8] ^R [11] ^R [12] ^R
[14]^R[15]
R [9]=D [15] ^D [13] ^D [12] ^D [9] ^D [8] ^D [4] ^R [4] ^R [8] ^R [9] ^R [12] ^R [13] ^R [15]
R [10]=D [14] ^D [13] ^D [10] ^D [9] ^D [5] ^R [5] ^R [9] ^R [10] ^R [13] ^R [14]
R [11]=D [15] ^D [14] ^D [11] ^D [10] ^D [6] ^R [6] ^R [10] ^R [11] ^R [14] ^R [15]
R [12]=D [15] ^D [8] ^D [7] ^D [4] ^D [0] ^R [0] ^R [4] ^R [7] ^R [8] ^R [15]
R [13]=D [9] ^D [8] ^D [5] ^D [1] ^R [1] ^R [5] ^R [8] ^R [9]
R [14]=D [10] ^D [9] ^D [6] ^D [2] ^R [2] ^R [6] ^R [9] ^R [10]
R [15]=D [11] ^D [10] ^D [7] ^D [3] ^R [3] ^R [7] ^R [10] ^R [11]
Wherein, R represents the numerical value in corresponding registers, and D represents the numerical value of corresponding input data, and ^ indicates XOR operation;
Step 2: look-up table is established;
If G (X) is the check polynomial of CRC, k is the length for transmitting data, and n is the length for sending data, then the length of check bit
Degree is n-k;At this point, setting the multinomial for sending data as v (x), error of transmission data polynomial is e (x) and reception data are multinomial
Formula is r (x), and there are following relationships between them
R (x)=v (x)+e (x)
CRC check and calculating is enabled to be expressed as follows CRCG(x){ v (x) }, in the case where G (x), v (x), n and k certain, calculated result
It should be one 0;In receiving end, calculated with identical CRC check multinomial, it is available to draw a conclusion
CRCG(x){ r (x) }=CRCG(x){ v (x)+e (x) }=CRCG(x){e(x)}
This illustrates the CRC check result for obtaining different type of error mistakes if there is a suitable multinomial verification formula of CRC
It is different between two, then the position of mistake occurs in data can be obtained by the CRC check result generated;
According to packet length and corresponding Parallel CRC arithmetic expression, crc value when everybody generation mistake of the length is calculated, and should
Value storage is stand-by to corresponding memory space;
Step 3: correcting data error;
Corresponding CRC is added in transmission data through the above way, CRC is carried out to data using identical CRC in recipient
Resolving, if data in transmission process there is no error code, the CRC calculated should be 0;If the crc value calculated
Be not zero, be then compared the value with the look-up table stored before, if generate matching, by look-up table correspondence position with
The correspondence position of data carries out XOR operation, and correct data can be obtained after resolving;If not generating matching, illustrate that data are sent out
The data transmission fault of unknown digit is given birth to, it should abandon.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
CN201510824266.2A CN106788878B (en) | 2015-11-24 | 2015-11-24 | A kind of Parallel CRC error correction method with monobit errro correction function |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
CN201510824266.2A CN106788878B (en) | 2015-11-24 | 2015-11-24 | A kind of Parallel CRC error correction method with monobit errro correction function |
Publications (2)
Publication Number | Publication Date |
---|---|
CN106788878A CN106788878A (en) | 2017-05-31 |
CN106788878B true CN106788878B (en) | 2019-11-15 |
Family
ID=58964583
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CN201510824266.2A Active CN106788878B (en) | 2015-11-24 | 2015-11-24 | A kind of Parallel CRC error correction method with monobit errro correction function |
Country Status (1)
Country | Link |
---|---|
CN (1) | CN106788878B (en) |
Families Citing this family (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN109474380B (en) * | 2017-09-08 | 2022-05-10 | 华为技术有限公司 | Encoding method and device |
CN109474377A (en) * | 2017-09-08 | 2019-03-15 | 华为技术有限公司 | Coding method and device |
CN107943611B (en) * | 2017-11-08 | 2021-04-13 | 天津国芯科技有限公司 | Control device for quickly generating CRC |
CN113050519B (en) * | 2021-03-31 | 2022-04-12 | 山东商业职业技术学院 | CRC 16-based single-bit error correction FPGA implementation method |
CN113904754A (en) * | 2021-09-29 | 2022-01-07 | 山东云海国创云计算装备产业创新中心有限公司 | CRC error correction method and related device |
Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN1633030A (en) * | 2003-12-22 | 2005-06-29 | 普天信息技术研究院 | A rapid calculation method for cyclic redundant check |
CN103297196A (en) * | 2013-06-20 | 2013-09-11 | 成都国星通信有限公司 | Cyclic redundancy check algorithm of non-integral byte data |
CN103684663A (en) * | 2012-09-10 | 2014-03-26 | 西门子信号有限公司 | Device and method for cyclic redundancy check |
-
2015
- 2015-11-24 CN CN201510824266.2A patent/CN106788878B/en active Active
Patent Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN1633030A (en) * | 2003-12-22 | 2005-06-29 | 普天信息技术研究院 | A rapid calculation method for cyclic redundant check |
CN103684663A (en) * | 2012-09-10 | 2014-03-26 | 西门子信号有限公司 | Device and method for cyclic redundancy check |
CN103297196A (en) * | 2013-06-20 | 2013-09-11 | 成都国星通信有限公司 | Cyclic redundancy check algorithm of non-integral byte data |
Non-Patent Citations (2)
Title |
---|
USB2.0中CRC码的并行算法及硬件实现;陈静瑾;《西安理工大学学报》;20041231;第20卷(第3期);第272-275页 * |
一种CRC并行计算原理及实现方法;朱荣华;《电子学报》;19991231;第27卷(第4期);第1-6页 * |
Also Published As
Publication number | Publication date |
---|---|
CN106788878A (en) | 2017-05-31 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
CN106788878B (en) | A kind of Parallel CRC error correction method with monobit errro correction function | |
CN100492325C (en) | Method and device for correcting/detecting multiple spotty byte errors in bytes of limited number of erroneous bytes | |
CN103281166B (en) | A kind of mixed automatic retransfer request transmission method based on polarization code | |
RU2519524C2 (en) | Methods and apparatus employing fec codes with permanent inactivation of symbols for encoding and decoding processes | |
US6721919B1 (en) | Shared encoder used in error correction having multiple encoders of different maximum error correction capabilities | |
CN111143107B (en) | FPGA single event reversal verification circuit and method | |
CN101814922A (en) | Multi-bit error correcting method and device based on BCH (Broadcast Channel) code and memory system | |
Ye et al. | RESIDENT: a reliable residue number system-based data transmission mechanism for wireless sensor networks | |
CN104378122B (en) | A kind of Compilation Method of variable-length Turbo code | |
CN101296053A (en) | Method and system for calculating cyclic redundancy check code | |
CN102427398B (en) | Error detection and correction method, system and device based on two-way parity check | |
CN103297196A (en) | Cyclic redundancy check algorithm of non-integral byte data | |
CN101207467B (en) | Generation of cyclic redundancy check code as well as method and apparatus for sending and testing data sequence | |
US10686471B2 (en) | One-sub-symbol linear repair schemes | |
CN101803204B (en) | Bit string-error correcting method | |
US8560920B2 (en) | Error correction via lookup in compressed error location data | |
Thakor et al. | On complexity reduction of the LP bound computation and related problems | |
Krishnan et al. | Codes with Combined Locality and Regeneration Having Optimal Rate, $ d_ {\min} $ and Linear Field Size | |
CN103532666B (en) | Improve the method for data transmission efficiency and LT code performance in distributed transmission | |
CN108566210B (en) | LDPC (Low Density parity check) coding system and method compatible with IEEE (institute of Electrical and electronics Engineers) 802.11n standard and LDPC coder | |
CN101355403B (en) | Error-detection error-correction device for universal frame-forming protocol and control method thereof | |
Laih et al. | On the analysis and design of group theoretical t-syEC/AUED codes | |
US20230370092A1 (en) | Error Correction With Fast Syndrome Calculation | |
JP3879082B2 (en) | Byte error correction / detection device | |
Bertram et al. | An improved majority-logic decoder offering massively parallel decoding for real-time control in embedded systems |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
PB01 | Publication | ||
PB01 | Publication | ||
SE01 | Entry into force of request for substantive examination | ||
SE01 | Entry into force of request for substantive examination | ||
GR01 | Patent grant | ||
GR01 | Patent grant |