CN101207467B - Generation of cyclic redundancy check code as well as method and apparatus for sending and testing data sequence - Google Patents
Generation of cyclic redundancy check code as well as method and apparatus for sending and testing data sequence Download PDFInfo
- Publication number
- CN101207467B CN101207467B CN2006101654183A CN200610165418A CN101207467B CN 101207467 B CN101207467 B CN 101207467B CN 2006101654183 A CN2006101654183 A CN 2006101654183A CN 200610165418 A CN200610165418 A CN 200610165418A CN 101207467 B CN101207467 B CN 101207467B
- Authority
- CN
- China
- Prior art keywords
- data
- bit
- cyclic redundancy
- redundancy check
- check code
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
- 125000004122 cyclic group Chemical group 0.000 title claims abstract description 175
- 238000000034 method Methods 0.000 title claims abstract description 63
- 238000012545 processing Methods 0.000 claims description 29
- 230000005540 biological transmission Effects 0.000 description 7
- 238000004364 calculation method Methods 0.000 description 4
- 150000001875 compounds Chemical class 0.000 description 4
- 238000010586 diagram Methods 0.000 description 4
- 238000004891 communication Methods 0.000 description 2
- 230000002411 adverse Effects 0.000 description 1
- FFBHFFJDDLITSX-UHFFFAOYSA-N benzyl N-[2-hydroxy-4-(3-oxomorpholin-4-yl)phenyl]carbamate Chemical compound OC1=C(NC(=O)OCC2=CC=CC=C2)C=CC(=C1)N1CCOCC1=O FFBHFFJDDLITSX-UHFFFAOYSA-N 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 230000008054 signal transmission Effects 0.000 description 1
- 238000012795 verification Methods 0.000 description 1
Images
Landscapes
- Error Detection And Correction (AREA)
- Detection And Correction Of Errors (AREA)
Abstract
The invention discloses a cyclic redundancy check code generating method, which includes the steps that: A. the data sequence is segmented orderly, a cyclic redundancy check code table item the bit of which is uniform with the bit of the segmented data is created; B. the cyclic redundancy check code table item for uniform bit in the first data segment is searched to obtain a r bit search result; C. the search result and the r bit data from the first bit of a second data segment are added up, and the r bit data is replaced by the obtained result; D. the first data segment on the data sequenceis discarded; E. step B to step D are repeated; until the data sequence has only the last segment left, the corresponding cyclic redundancy check code table item in the last data segment is searched to obtain a cyclic redundancy check code. By the invention, a data sequence containing more bits can be rapidly processed.
Description
Technical Field
The invention relates to the technical field of communication and computer data transmission, in particular to a method and a device for generating a cyclic redundancy check code and transmitting and checking a data sequence.
Background
In the data transmission process, some unpredictable errors often occur in the data transmission between the communication devices due to the influence of many factors, such as transmission distance, field conditions, various interferences and the like. In order to reduce the adverse effects caused by these errors, a data checking method is usually adopted to find and/or correct the data transmission, for example, a specific check code is inserted into the data to be transmitted at the transmitting end, the data is checked at the receiving end by using the specific check code in the received data, and then whether the data is erroneous in transmission is determined.
Currently, Cyclic Redundancy Check (CRC) codes are a common type of error control codes used in digital signal transmission. The basic principle of the CRC check is: the sending end divides the data sequence N (x) to be sent by a specific CRC generating polynomial G (x) (such as CRC-5, CRC-8, CRC-16, CRC-32 and the like) to obtain a remainder R (x), wherein the remainder R (x) is a CRC check code. The sending end places the CRC code after the data sequence N (x) to be sent, and sends the CRC code along with the data sequence N (x). And the receiving end divides the received data sequence N (x) by the same generator polynomial G (x) according to the same method as the transmitting end to obtain a new CRC check code. Comparing the new CRC check code with the original CRC check code, and if the new CRC check code is consistent with the original CRC check code, determining that the received data sequence is correct; otherwise, the data is considered to have errors in transmission and the transmitting end is required to retransmit.
The CRC check operation is usually implemented using dedicated hardware circuits, but to reduce cost, many systems are often implemented using single-chip, microprocessor programmed, or programmable devices. Currently, the commonly used CRC check methods include:
the method comprises the following steps: the direct generation method. The direct generation method is to directly calculate and generate CRC check code according to the generation principle of the CRC check code, and the method divides the whole column of data to be transmitted N (x) by a certain specific generating polynomial G (x) until a final result is obtained, and the generated remainder is the CRC check code. The method can only process 1 bit data 1 time by processing bit by bit, so the efficiency of processing data is low, the calculation amount is large, and the method is not suitable for the verification processing of a longer data sequence.
The second method comprises the following steps: and (4) a table look-up method. The table look-up method is to find out the CRC check code corresponding to the data sequence in the CRC table entry and then check according to the CRC check code. The method firstly requires to generate a CRC table entry with the same bit length as the data sequence to be processed, wherein the table entry comprises all the data sequences with the bit number and the corresponding CRC check codes. However, when the data sequence is long, the method occupies a large table entry resource. For example, if a CRC-5 check is performed on a 20-bit binary data sequence, the number of required entries is 2201M, and each table entry occupies 5 bits, so 2 is occupied20The system memory space of 5M Bit is not satisfied by the general FPGA.
Disclosure of Invention
In view of the above, an object of the present invention is to provide a method and an apparatus for generating cyclic redundancy check codes and transmitting and checking data sequences, which occupy less memory cells and can quickly process data sequences with a large number of bits.
In order to solve the above problem, the method for generating a cyclic redundancy check code according to the present invention includes:
A. sequentially segmenting the data sequence, and establishing a cyclic redundancy check code table entry with the same bit as the segmented data segment;
B. searching the same-bit cyclic redundancy check code table entry for the first data segment to obtain an r-bit searching result;
C. performing modulo two addition on the search result and r-bit data from the head of the second data segment, and replacing the r-bit data with the obtained result;
D. discarding a first data segment of the data sequence;
E. repeating the steps B to D; and when only the last segment of the data sequence remains, searching the corresponding cyclic redundancy check code table entry of the segment of data to obtain the cyclic redundancy check code.
Wherein, the step A specifically comprises the following steps:
when the data sequence can be equally divided, the data sequence is sequentially equally divided into n-bit data segments, and n-bit cyclic redundancy check code table entries are established; or
When the data sequence can not be equally divided, dividing the data sequence into a plurality of segments according to the sequence of n bits as one segment, and dividing the rest n1Using the bit data as the last segment, establishing n, n1A cyclic redundancy check code entry for the bit.
In step E, the searching for the corresponding cyclic redundancy check code entry of the segment of data to obtain the cyclic redundancy check code specifically includes:
when the data sequence can be equally divided, searching n-bit cyclic redundancy check code table items of the n-bit data to obtain a cyclic redundancy check code; or
When the data sequence can not be equally divided, dividing the n1Bit data carries out n1And searching the bit cyclic redundancy check code table entry to obtain the cyclic redundancy check code.
Preferably, the following steps are specifically performed until only the last segment of the data sequence remains: until the data sequence length is less than or equal to n bits.
Preferably, the method further comprises, between the step a and the step B: the initial value of the counter is set to 0.
Wherein, further comprising between step D and step E: the counter value is incremented by 1.
Wherein, the specific steps until the data sequence has only the last segment are: until when the counter value equals the total number of data segments into which the data sequence is divided minus 1.
Based on the above scheme, the apparatus for generating cyclic redundancy check codes provided by the present invention includes:
the register is used for sequentially segmenting the stored data sequence;
the table item generating unit establishes a cyclic redundancy check code table item with the same bit as the data segment in the register and stores the table item into a table look-up unit;
the table look-up unit searches the first data segment in the register for the cyclic redundancy check code table entry with the same bit, and sends the obtained corresponding r-bit search result to the processing unit;
the processing unit carries out modulo two addition on the search result and r bit data from the first bit of the second data segment, and replaces the r bit data in the register according to the corresponding bit;
the register overflows the first data segment of the data sequence;
the judging unit judges the total number of the remaining data segments in the register, and the table look-up unit searches the corresponding cyclic redundancy check code table entry of the segment of data in the register until the data sequence in the register only has the last segment, so as to obtain the cyclic redundancy check code.
Wherein when the data sequence cannot be equally divided, the table look-up unit comprises: the first table look-up unit and the second table look-up unit;
the register divides the stored data sequence into a plurality of segments according to the sequence of a segment with n bits, takes the rest n1 bits data as the last segment,
the table item generating unit establishes the table item with n and n in the register1N, n of the same bit of the bit data segment1A bit cyclic redundancy check code table entry, and the n are used1And the bit cyclic redundancy check code table items are respectively stored in the first table look-up unit and the second table look-up unit.
The first table look-up unit searches a cyclic redundancy check code table entry with n bits for a first data segment in the register and sends an obtained r-bit search result to the processing unit;
the second table look-up unit carries out n on the last data segment in the register1And searching the cyclic redundancy check code table entry of the bit to obtain the cyclic redundancy check code.
Based on the above scheme, the method for sending a data sequence containing a cyclic redundancy check code provided by the invention comprises the following steps:
A. sequentially segmenting the data sequence, and establishing a cyclic redundancy check code table entry with the same bit as the segmented data segment;
B. searching the same-bit cyclic redundancy check code table entry for the first data segment to obtain an r-bit searching result;
C. performing modulo two addition on the search result and r-bit data from the head of the second data segment, and replacing the r-bit data with the obtained result;
D. discarding a first data segment of the data sequence;
E. repeating the steps B to D; when only the last segment of the data sequence remains, searching the corresponding cyclic redundancy check code table entry of the segment of data to obtain a cyclic redundancy check code;
F. and the cyclic redundancy check code is sequentially added after the data sequence and is transmitted along with the data sequence.
Based on the above scheme, the apparatus for transmitting a data sequence including a cyclic redundancy check code according to the present invention includes:
the register is used for sequentially segmenting the stored data sequence;
the table item generating unit generates a cyclic redundancy check code table item with the same bit as the data segment in the register and stores the table item into the table look-up unit;
the table look-up unit searches the first data segment in the register for the cyclic redundancy check code table entry with the same bit, and sends the obtained corresponding r-bit search result to the processing unit;
the processing unit carries out modulo two addition on the search result and r bit data from the first bit of the second data segment, and replaces the r bit data in the register according to the corresponding bit;
the register overflows the first data segment of the data sequence;
the judging unit judges the total number of the remaining data segments in the register, and the table look-up unit searches the corresponding cyclic redundancy check code table item of the data segment in the register until the data sequence in the register only has the last segment, and sends the obtained cyclic redundancy check code to the sending unit;
the transmitting unit adds the cyclic redundancy check codes to the data sequence in sequence and transmits the cyclic redundancy check codes together with the data sequence.
Based on the above scheme, the method for performing cyclic redundancy check on the received data sequence provided by the present invention comprises:
A. sequentially segmenting the data sequence, and establishing a cyclic redundancy check code table entry with the same bit as the segmented data segment;
B. searching the same-bit cyclic redundancy check code table entry for the first data segment to obtain an r-bit searching result;
C. performing modulo two addition on the search result and r-bit data from the head of the second data segment, and replacing the r-bit data with the obtained result;
D. discarding a first data segment of the data sequence;
E. repeating the steps B to D; when only the last segment of the data sequence remains, searching the corresponding cyclic redundancy check code table entry of the segment of data to obtain a cyclic redundancy check code;
F. and performing modulo two addition on the obtained cyclic redundancy check code and the original cyclic redundancy check code, and checking the data sequence according to the result.
Wherein the verifying the data sequence according to the result comprises:
when the obtained result is 0, the data sequence to be processed is considered to be correct;
and when the obtained result is 1, the data sequence to be processed is considered to have errors.
Based on the above scheme, the apparatus for performing cyclic redundancy check on a received data sequence containing a cyclic redundancy check code provided by the present invention includes:
the register is used for sequentially segmenting the stored data sequence;
the table item generating unit generates a cyclic redundancy check code table item with the same bit as the data segment in the register and stores the table item into the table look-up unit;
the table look-up unit searches the first data segment in the register for the cyclic redundancy check code table entry with the same bit, and sends the obtained corresponding r-bit search result to the processing unit;
the processing unit carries out modulo two addition on the search result and r bit data from the first bit of the second data segment, and replaces the r bit data in the register according to the corresponding bit;
the register overflows the first data segment of the data sequence;
the judging unit judges the total number of the remaining data segments in the register, and the table look-up unit searches the corresponding cyclic redundancy check code table items of the data segment in the register until the data sequence in the register only has the last segment, and sends the obtained cyclic redundancy check code to the checking unit;
and the checking unit performs modulo two addition on the obtained cyclic redundancy check code and the original cyclic redundancy check code, checks the data sequence according to the result of the modulo two addition, and outputs the checking result.
Compared with the prior art, the invention firstly groups the data sequence to be processed, divides the data sequence into data segments containing a small number of bits, and then carries out CRC check by table look-up and simple modulo two addition operation on the grouped data. The invention can reduce the operation amount of the system, further improve the processing speed, and is particularly suitable for data sequences with more digits; meanwhile, the invention only inquires the CRC table entry of the grouped data segment, and the bit number of the segmented data is 3-10 bits, so the storage space occupied by the CRC table entry is very small, and the invention can save the storage resource of the system especially for CRC check by adopting a programmable device.
Drawings
FIG. 1 is a flow chart of a method for generating a CRC check code using a direct generation method;
FIG. 2 is a flowchart illustrating a first embodiment of a method for generating a CRC check code according to the present invention;
FIG. 3 is a flowchart illustrating a second embodiment of a method for generating a CRC check code according to the present invention;
FIG. 4 is a flowchart illustrating a third embodiment of a method for generating a CRC check code according to the present invention;
FIG. 5 is a flowchart illustrating a fourth embodiment of a method for generating a CRC check code according to the present invention;
FIG. 6 is a schematic structural diagram of a CRC code generator according to the present invention;
FIG. 7 is a diagram illustrating a transmitting apparatus for transmitting a data sequence with a CRC code according to the present invention;
fig. 8 is a schematic structural diagram of an apparatus for performing CRC check on received data according to the present invention.
Detailed Description
The method for generating the cyclic redundancy check code comprises the following steps:
A. sequentially segmenting the data sequence, and establishing a cyclic redundancy check code table entry with the same bit as the segmented data segment;
B. searching the same-bit cyclic redundancy check code table entry for the first data segment to obtain an r-bit searching result;
C. performing modulo two addition on the search result and r-bit data from the head of the second data segment, and replacing the r-bit data with the obtained result;
D. discarding a first data segment of the data sequence;
E. repeating the steps B to D; and when only the last segment of the data sequence remains, searching the corresponding cyclic redundancy check code table entry of the segment of data to obtain the cyclic redundancy check code.
Wherein, the cyclic redundancy check (hereinafter referred to as CRC) code table item includes all data segments with the same length and corresponding CRC check codes; the CRC check code may be generated using a direct generation method according to a specific CRC generator polynomial. Referring to fig. 1, a flow chart of a method for generating a CRC check code by using a direct generation method is shown, where a data sequence g (x) to be processed is set to m bits, the method includes:
step 101: the value in the register is set to zero.
Step 102: after r zeros are added after a data sequence g (x) of m bits to be processed, storing a segment of data of the data sequence into the register according to the high-low order. Wherein the value of r is equal to the number of bits of the CRC check code to be generated, while the generator polynomial g (x) is also determined from the value of r. For example, when r is 5, then the CRC-5 generator polynomial is selected.
Step 103: judging whether the bit number of the preprocessed data sequence g (x) is less than or equal to r. When the value is larger than r, executing step 104; otherwise, step 107 is performed.
Step 104: determine whether the first bit of the register is 1? If 1, executing step 105; otherwise, step 106 is performed.
Step 105: modulo-two addition of the preprocessed data sequence in the register with the generator polynomial g (x).
Step 106: and shifting the data sequence in the register by 1 bit to the left, reading in a new data following the data segment and placing the new data in the position of a register bit 0. Returning to step 103.
Step 107: is it determined whether the number of bits of the preprocessed data sequence g (x) is equal to r? If r, go to step 108; otherwise, the value in the register is the CRC check code.
Step 108: performing modulo-two addition on the preprocessed r bit data in the register and the generator polynomial G (x), wherein the obtained result is a CRC check code.
The embodiments of the CRC check code generation method according to the present invention are further described in detail below with reference to the accompanying drawings.
Please refer to fig. 2, which is a flowchart illustrating a first embodiment of a CRC check code generation method according to the present invention, wherein the first embodiment specifically includes the following steps:
let the data to be processed be m-bit binary sequence g (x), and the CRC check generator polynomial be g (x) of order r.
Step 201: dividing m data sequences g (x) to be checked into a plurality of data segments from the first bit according to a group of n bits, wherein the value range of the bit n is preferably 3-10.
Step 202: and generating an n-bit CRC check code table entry by using a direct generation method.
The n-bit CRC check code table entry comprises all n-bit binary data sequences and corresponding CRC check codes, and the check codes are calculated by adopting a direct generation method according to a specific CRC generating polynomial.
Specifically, the binary data sequence composed of "0" and "1" of n bits is arranged and combined to obtain all the binary data sequences of n bits, i.e. 2nA binary data sequence of n bits. Then 2 willnThe binary data sequences of n bits are respectively processed by a direct generation method to obtain the corresponding CRC check code. 2 of the generationnAnd filling the CRC check code and the corresponding data sequence into the CRC check code table entry to obtain a two-dimensional n-bit CRC check code table entry. For example, when n is 4 bits, if a CRC generator polynomial of order 5 is used, a 4-bit CRC-5 check code table entry can be generated according to the above method, as shown in table 1 below:
TABLE 14 bit CRC-5 checksum entry
Step 203: and adding r zeros at the end of the m-bit data sequence g (x) to obtain a data sequence with m + r bits. The data sequence of m + r bits is written into a register of m + r bits.
Step 204: determine if the number of bits g (x) is equal to n? If not, go to step 205; otherwise, step 207 is performed.
Step 205: and inquiring the table entry of the n-bit CRC check code for the first n-bit data segment.
And sequentially taking n-bit data from g (x) high bits, and searching a CRC (cyclic redundancy check) code corresponding to the data in the n-bit CRC code table entry, wherein the numerical bit length of the CRC code is r bits.
Step 206: performing modulo two addition on the search result, performing exclusive or operation on the searched r-bit CRC code and r-bit data from the head of a second data segment of the data sequence g (x), and replacing the r-bit data with the obtained result; and shifts the data sequence left by n bits. Returning to step 204.
Step 207: and inquiring an n-bit CRC check code table entry according to the n-bit data in the g (x). And obtaining a result, namely the CRC corresponding to the n-bit data segment.
Please refer to fig. 3, which is a flowchart illustrating a second method embodiment of the present invention. When the m-bit binary data sequence g (x) to be processed cannot be divided by n, the quotient is a, and the remainder is n1. The processing can be performed according to the following method in the second embodiment, and the second embodiment of the CRC check method for the data sequence in the present invention is:
the data segment to be processed is an m-bit binary sequence g (x), and the CRC check generator polynomial is G (x) of r order.
Step 301: dividing m data sequences g (x) to be checked into a group from the head into a plurality of data segments according to n bits, wherein the value range of the bit group n is preferably 3-10. Since the remainder of m/n is n1Then the last group of the m-bit data sequence to be verified is n1A bit data segment. For example, for a 19-bit data sequence, if grouped in groups of 4 bits, the last group of the 19-bit data sequence is n13 bits.
Step 302: generating n, n by direct calculation1A CRC check code entry for the bits. N, n1The CRC check code table entry of the bit comprises all n and n1The CRC check code is obtained by calculating according to a specific CRC generating polynomial by adopting a direct generating method.
Step 303: and adding r zeros at the end of the m-bit data sequence to obtain a data sequence with m + r bits. The data sequence of m + r bits is written into a register of m + r bits.
Step 304: determine g (x) if the number of bits is less than n? If not, go to step 305; otherwise, step 307 is executed.
Step 305: and inquiring the table entry of the n-bit CRC check code for the first n-bit data segment.
And sequentially taking n-bit data from g (x) high bits, and searching a CRC (cyclic redundancy check) code corresponding to the data in the n-bit CRC code table entry, wherein the numerical bit length of the CRC code is r bits.
Step 306: performing modulo two addition on the search result, performing exclusive or operation on the searched r-bit CRC code and r-bit data from the head of a second data segment of the data sequence g (x), and replacing the r-bit data with the obtained result; and shifts the data sequence left by n bits. Returning to step 304.
Step 307: according to n in g (x)1Bit data querying the n1Bit CRC check code table entries. To obtain the compound of formula (I) and the compound of formula (n)1And CRC check codes corresponding to the bit data fields.
Referring to fig. 4, which is a flowchart illustrating a third embodiment of the CRC check code generating method according to the present invention, when the m-bit binary data sequence g (x) to be processed can be divided by n, the quotient is a. The processing may also be performed according to the following method in the third embodiment, where the third embodiment of the method for performing CRC check on a data sequence in the present invention is:
the data segment to be processed is an m-bit binary sequence g (x), and the CRC check generator polynomial is G (x) of r order.
Step 401: dividing m data sequences g (x) to be checked into a plurality of data segments from the head according to a group of n bits, wherein the value range of the bit group n is preferably 3-10.
Step 402: and generating an n-bit CRC check code table entry by using a direct calculation method.
The n-bit CRC check code table entry comprises all n-bit binary data sequences and check codes corresponding to the n-bit binary data sequences, and the check codes are calculated by adopting a direct generation method according to a specific CRC generating polynomial.
Step 403: and adding r zeros at the end of the m-bit data sequence to obtain a data sequence with m + r bits. The data sequence of m + r bits is written into a register of m + r bits.
Step 404: determine if the counter is equal to a-1? If not, go to step 405; otherwise, step 407 is executed.
Step 405: and inquiring the table entry of the n-bit CRC check code for the first n-bit data segment.
And sequentially taking n-bit data from g (x) high bits, and searching a CRC (cyclic redundancy check) code corresponding to the data in the n-bit CRC code table entry, wherein the numerical bit length of the CRC code is r bits.
Step 406: performing modulo two addition on the search result, performing exclusive or operation on the searched r-bit CRC code and r-bit data from the head of a second data segment of the data sequence g (x), and replacing the r-bit data with the obtained result; and shifts the data sequence left by n bits. The counter is incremented by 1. Returning to step 404.
Step 407: and inquiring an n-bit CRC check code table entry according to the n-bit data in the g (x). And obtaining a result, namely the CRC corresponding to the n-bit data segment.
Please refer to fig. 5, which is a method for generating CRC check codes according to the present inventionThe flow chart of the fourth embodiment. When the m-bit binary data sequence g (x) to be processed cannot be divided by n, the quotient is a, and the remainder is n1. The processing may also be performed according to the following method in the fourth embodiment, where the fourth embodiment of the method for performing CRC check on a data sequence in the present invention is:
the data segment to be processed is an m-bit binary sequence g (x), and the CRC check generator polynomial is G (x) of r order.
Step 501: dividing m data sequences g (x) to be checked into a group from the head into a plurality of data segments according to n bits, wherein the value range of the bit group n is preferably 3-10. Since the remainder of m/n is n1Then the last group of the m-bit data sequence to be verified is n1A bit data segment. Are divided into a group a.
Step 502: generating n, n by direct calculation1A CRC check code entry for the bits. N, n1The CRC check code table entry of the bit comprises all n and n1The check code is calculated by a direct generation method according to a specific CRC generator polynomial.
Step 503: and adding r zeros at the end of the m-bit data sequence to obtain a data sequence with m + r bits. The data sequence of m + r bits is written into a register of m + r bits.
Step 504: the initial value of the counter is set to 0.
Step 505: determine if the counter is equal to a? If not, go to step 506; otherwise, step 508 is performed.
Step 506: and inquiring the table entry of the n-bit CRC check code for the first n-bit data segment.
And sequentially taking n-bit data from g (x) high bits, and searching a CRC (cyclic redundancy check) code corresponding to the data in the n-bit CRC code table entry, wherein the numerical bit length of the CRC code is r bits.
Step 507: performing modulo two addition on the search result, performing exclusive or operation on the searched r-bit CRC code and r-bit data from the head of a second data segment of the data sequence g (x), and replacing the r-bit data with the obtained result; and shifts the data sequence left by n bits. The counter value is incremented by 1. Returning to step 504.
Step 508: according to n in g (x)1Bit data querying the n1Bit CRC check code table entries. To obtain the compound of formula (I) and the compound of formula (n)1And CRC check codes corresponding to the bit data fields.
Fig. 6 is a schematic structural diagram of a CRC check code generating device according to the present invention, and based on the above scheme, the CRC check code generating device according to the present invention includes a register 601, a table entry generating unit 602, a table look-up unit 603, a processing unit 604, and a determining unit 605. Wherein,
the register 601 is used for sequentially segmenting the stored data sequence;
the table entry generating unit 602 establishes a cyclic redundancy check code table entry with the same bit as the data segment in the register 601, and stores the table entry into the table look-up unit 603;
the table look-up unit 603 searches the first data segment in the register 601 for the cyclic redundancy check code table entry with the same bit, and sends the obtained corresponding r-bit search result to the processing unit 604;
the processing unit 604 performs modulo two addition on the search result and r-bit data from the first bit of the second data segment, and replaces the r-bit data in the register 601 with the obtained result according to the corresponding bit;
the register 601 overflows the first data segment of the data sequence;
the judging unit 605 judges the total number of the remaining data segments in the register 601, and the table look-up unit 603 performs corresponding lookup of the cyclic redundancy check code table entry on the data segment in the register 601 until only the last segment of the data sequence in the register 601 remains, so as to obtain the cyclic redundancy check code.
When the data sequence cannot be equally divided, the register 601 divides the stored data sequence into a plurality of segments in the order of n bits, and takes the remaining n1 bits as the last segment. In this case, the table look-up unit 603 includes: the first table look-up unit and the second table look-up unit.
The table item generating unit establishes the table item with n and n in the register1N, n of the same bit of the bit data segment1After the bit cyclic redundancy check code table entry, and the n are combined1And the bit cyclic redundancy check code table items are respectively stored in the first table look-up unit and the second table look-up unit.
When the data sequence has more than one segment, selecting the first table look-up unit to carry out n-bit CRC check code table item look-up on the first data segment in the register; and when the data sequence only has the last data segment, selecting a second table look-up unit to look up the last segment of data, wherein the table look-up result is the final CRC check code.
The invention provides a method for sending a data sequence containing a cyclic redundancy check code, which comprises the following steps:
A. sequentially segmenting the data sequence, and establishing a cyclic redundancy check code table entry with the same bit as the segmented data segment;
B. searching the same-bit cyclic redundancy check code table entry for the first data segment to obtain an r-bit searching result;
C. performing modulo two addition on the search result and r-bit data from the head of the second data segment, and replacing the r-bit data with the obtained result;
D. discarding a first data segment of the data sequence;
E. repeating the steps B to D; when only the last segment of the data sequence remains, searching the corresponding cyclic redundancy check code table entry of the segment of data to obtain a cyclic redundancy check code;
F. and the cyclic redundancy check code is sequentially added after the data sequence and is transmitted along with the data sequence.
Based on the above scheme, the apparatus for transmitting a data sequence including a cyclic redundancy check code according to the present invention, as shown in fig. 6, includes: register 601, table entry generating unit 602, table lookup unit 603, processing unit 604, determining unit 605, and transmitting unit 701. Wherein,
the register 601 is used for sequentially segmenting the stored data sequence;
the table entry generating unit 602 establishes a cyclic redundancy check code table entry with the same bit as the data segment in the register 601, and stores the table entry into the table look-up unit 603;
the table look-up unit 603 searches the first data segment in the register 601 for the cyclic redundancy check code table entry with the same bit, and sends the obtained corresponding r-bit search result to the processing unit 604;
the processing unit 604 performs modulo two addition on the search result and r-bit data from the first bit of the second data segment, and replaces the r-bit data in the register 601 with the obtained result according to the corresponding bit;
the register 601 overflows the first data segment of the data sequence;
the judging unit 605 judges the total number of the remaining data segments in the register 601, until the data sequence in the register 601 only has the last segment, the table look-up unit 603 searches the corresponding cyclic redundancy check code table entry for the segment of data in the register 601, and sends the obtained cyclic redundancy check code to the sending unit 701;
the transmitting unit 701 sequentially adds the cyclic redundancy check codes to the data sequence, and transmits the cyclic redundancy check codes together with the data sequence.
The method for performing cyclic redundancy check on the received data sequence provided by the invention comprises the following steps:
A. sequentially segmenting the data sequence, and establishing a cyclic redundancy check code table entry with the same bit as the segmented data segment;
B. searching the same-bit cyclic redundancy check code table entry for the first data segment to obtain an r-bit searching result;
C. performing modulo two addition on the search result and r-bit data from the head of the second data segment, and replacing the r-bit data with the obtained result;
D. discarding a first data segment of the data sequence;
E. repeating the steps B to D; when only the last segment of the data sequence remains, searching the corresponding cyclic redundancy check code table entry of the segment of data to obtain a cyclic redundancy check code;
F. and performing modulo two addition on the obtained cyclic redundancy check code and the original cyclic redundancy check code, and checking the data sequence according to the result.
Wherein the verifying the data sequence according to the result comprises:
when the obtained result is 0, the data sequence to be processed is considered to be correct;
and when the obtained result is 1, the data sequence to be processed is considered to have errors.
Based on the above scheme, the apparatus for performing CRC check on a received data sequence containing a CRC check code, as shown in fig. 8, includes: register 601, table entry generating unit 602, table lookup unit 603, processing unit 604, judging unit 605, receiving unit 801, and checking unit 802. Wherein,
the register 601 is used for sequentially segmenting the data sequence received from the accepting unit 801;
the table entry generating unit 602 establishes a cyclic redundancy check code table entry with the same bit as the data segment in the register 601, and stores the table entry into the table look-up unit 603;
the table look-up unit 603 searches the first data segment in the register 601 for the cyclic redundancy check code table entry with the same bit, and sends the obtained corresponding r-bit search result to the processing unit 604;
the processing unit 604 performs modulo two addition on the search result and r-bit data from the first bit of the second data segment, and replaces the r-bit data in the register 601 with the obtained result according to the corresponding bit;
the register 601 overflows the first data segment of the data sequence;
the judging unit 605 judges the total number of the remaining data segments in the register 601, until the data sequence in the register 601 only has the last segment, the table look-up unit 603 searches the corresponding cyclic redundancy check code table entry for the segment of data in the register 601, and sends the obtained cyclic redundancy check code to the checking unit 802;
the check unit 802 performs modulo two addition on the obtained cyclic redundancy check code and the original cyclic redundancy check code, checks the data sequence according to the result, and outputs the check result.
The above-described embodiments of the present invention do not limit the scope of the present invention. Any modification, equivalent replacement, and improvement made within the spirit and principle of the present invention should be included in the protection scope of the present invention.
Claims (11)
1. A method for generating cyclic redundancy check codes, comprising:
A. segmenting the data sequence according to the high-low order, and establishing a cyclic redundancy check code table entry with the same bit as the segmented data segment;
B. searching the same-bit cyclic redundancy check code table entry for the first data segment to obtain an r-bit searching result;
C. performing modulo two addition on the search result and r-bit data from the head of the second data segment, and replacing the r-bit data with the obtained result;
D. discarding a first data segment of the data sequence;
E. repeating the steps B to D; when only the last segment of the data sequence remains, searching the corresponding cyclic redundancy check code table entry of the segment of data to obtain a cyclic redundancy check code;
the step A specifically comprises the following steps:
when the data sequence can be equally divided, equally dividing the data sequence into n-bit data segments according to the high-low order, and establishing n-bit cyclic redundancy check code table entries; or
When the data sequence can not be equally divided, dividing the data sequence into a plurality of sections according to the sequence of n bits as a section according to the high-low order, and dividing the rest n1Using the bit data as the last segment, establishing n, n1A cyclic redundancy check code table entry of bits;
in step E, the searching for the corresponding cyclic redundancy check code entry of the segment of data to obtain the cyclic redundancy check code specifically includes:
when the data sequence can be equally divided, searching n-bit cyclic redundancy check code table items of the n-bit data to obtain a cyclic redundancy check code; or
When the data sequence can not be equally divided, dividing the n1Bit data carries out n1And searching the bit cyclic redundancy check code table entry to obtain the cyclic redundancy check code.
2. The method of claim 1, wherein said generating until the last segment of the data sequence remains is further characterized by: until the data sequence length is less than or equal to n bits.
3. The method for generating cyclic redundancy check codes according to claim 1, further comprising, between the step a and the step B: the initial value of the counter is set to 0.
4. The method for generating cyclic redundancy check codes according to claim 3, further comprising between step D and step E: the counter value is incremented by 1.
5. The method of claim 4, wherein the step until the last segment of the data sequence remains is further characterized by: until when the counter value equals the total number of data segments into which the data sequence is divided minus 1.
6. An apparatus for generating a cyclic redundancy check code, comprising:
the register is used for equally dividing the data sequence into n-bit data segments according to the high-low order when the data sequence can be equally divided, or
When the data sequence can not be equally divided, dividing the data sequence into a plurality of sections according to the sequence of n bits as a section according to the high-low order, and dividing the rest n1Bit data as the last segment;
the table item generating unit establishes a cyclic redundancy check code table item with the same bit as the data segment in the register and stores the table item into a table look-up unit;
the table look-up unit searches the first data segment in the register for the cyclic redundancy check code table entry with the same bit, and sends the obtained corresponding r-bit search result to the processing unit;
the processing unit carries out modulo two addition on the search result and r bit data from the first bit of the second data segment, and replaces the r bit data in the register according to the corresponding bit;
the register overflows the first data segment of the data sequence;
the judging unit judges the total number of the remaining data segments in the register, and the table look-up unit searches the corresponding cyclic redundancy check code table entry of the segment of data in the register until the data sequence in the register only has the last segment, so as to obtain the cyclic redundancy check code;
when the data sequence cannot be equally divided:
the table look-up unit is divided into a first table look-up unit and a second table look-up unit;
the table item generating unit establishes the table item with n and n in the register1N, n of the same bit of the bit data segment1After the bit cyclic redundancy check code table entry, and the n are combined1The bit cyclic redundancy check code entries are respectively stored in the first table look-up unit and the second table look-up unit;
when the data sequence has more than one segment, selecting the first table look-up unit to carry out n-bit CRC check code table item look-up on the first data segment in the register; and when the data sequence only has the last data segment, selecting a second table look-up unit to look up the last segment of data, wherein the table look-up result is the final CRC check code.
7. A method for transmitting a data sequence containing a cyclic redundancy check code, comprising:
A. segmenting the data sequence according to the high-low order, and establishing a cyclic redundancy check code table entry with the same bit as the segmented data segment;
B. searching the same-bit cyclic redundancy check code table entry for the first data segment to obtain an r-bit searching result;
C. performing modulo two addition on the search result and r-bit data from the head of the second data segment, and replacing the r-bit data with the obtained result;
D. discarding a first data segment of the data sequence;
E. repeating the steps B to D; when only the last segment of the data sequence remains, searching the corresponding cyclic redundancy check code table entry of the segment of data to obtain a cyclic redundancy check code;
F. the cyclic redundancy check codes are sequentially added behind the data sequence and are transmitted together with the data sequence;
the step A specifically comprises the following steps:
when the data sequence can be equally divided, the data sequence is sequentially equally divided into n-bit data segments, and n-bit cyclic redundancy check code table entries are established; or
When the data sequence can not be equally divided, dividing the data sequence into a plurality of segments according to the sequence of n bits as one segment, and dividing the restn1Using the bit data as the last segment, establishing n, n1A cyclic redundancy check code table entry of bits; in step E, the searching for the corresponding cyclic redundancy check code entry of the segment of data to obtain the cyclic redundancy check code specifically includes:
when the data sequence can be equally divided, searching n-bit cyclic redundancy check code table items of the n-bit data to obtain a cyclic redundancy check code; or
When the data sequence can not be equally divided, dividing the n1Bit data carries out n1And searching the bit cyclic redundancy check code table entry to obtain the cyclic redundancy check code.
8. An apparatus for transmitting a data sequence including a cyclic redundancy check code, comprising:
the register is used for equally dividing the data sequence into n-bit data segments according to the high-low order when the data sequence can be equally divided, or
When the data sequence can not be equally divided, dividing the data sequence into a plurality of sections according to the sequence of n bits as a section according to the high-low order, and dividing the rest n1Bit data as the last segment;
the table item generating unit generates a cyclic redundancy check code table item with the same bit as the data segment in the register and stores the table item into the table look-up unit;
the table look-up unit searches the first data segment in the register for the cyclic redundancy check code table entry with the same bit, and sends the obtained corresponding r-bit search result to the processing unit;
the processing unit carries out modulo two addition on the search result and r bit data from the first bit of the second data segment, and replaces the r bit data in the register according to the corresponding bit;
the register overflows the first data segment of the data sequence;
the judging unit judges the total number of the remaining data segments in the register, and the table look-up unit searches the corresponding cyclic redundancy check code table item of the data segment in the register until the data sequence in the register only has the last segment, and sends the obtained cyclic redundancy check code to the sending unit;
when the data sequence cannot be equally divided:
the table look-up unit is divided into a first table look-up unit and a second table look-up unit;
the table item generating unit establishes the table item with n and n in the register1N, n of the same bit of the bit data segment1After the bit cyclic redundancy check code table entry, and the n are combined1The bit cyclic redundancy check code entries are respectively stored in the first table look-up unit and the second table look-up unit;
when the data sequence has more than one segment, selecting the first table look-up unit to carry out n-bit CRC check code table item look-up on the first data segment in the register; when the data sequence only has the last data segment, selecting a second table look-up unit to look-up the last segment of data, wherein the table look-up result is the final CRC (cyclic redundancy check) code;
the transmitting unit adds the cyclic redundancy check codes to the data sequence in sequence and transmits the cyclic redundancy check codes together with the data sequence.
9. A method for performing a cyclic redundancy check on a received data sequence, comprising:
A. segmenting the data sequence according to the high-low order, and establishing a cyclic redundancy check code table entry with the same bit as the segmented data segment;
B. searching the same-bit cyclic redundancy check code table entry for the first data segment to obtain an r-bit searching result;
C. performing modulo two addition on the search result and r-bit data from the head of the second data segment, and replacing the r-bit data with the obtained result;
D. discarding a first data segment of the data sequence;
E. repeating the steps B to D; when only the last segment of the data sequence remains, searching the corresponding cyclic redundancy check code table entry of the segment of data to obtain a cyclic redundancy check code;
F. performing modulo two addition on the obtained cyclic redundancy check code and the original cyclic redundancy check code, and checking the data sequence according to the result;
the step A specifically comprises the following steps:
when the data sequence can be equally divided, the data sequence is sequentially equally divided into n-bit data segments, and n-bit cyclic redundancy check code table entries are established; or
When the data sequence can not be equally divided, dividing the data sequence into a plurality of segments according to the sequence of n bits as one segment, and dividing the rest n1Using the bit data as the last segment, establishing n, n1A cyclic redundancy check code table entry of bits; in step E, the searching for the corresponding cyclic redundancy check code entry of the segment of data to obtain the cyclic redundancy check code specifically includes:
when the data sequence can be equally divided, searching n-bit cyclic redundancy check code table items of the n-bit data to obtain a cyclic redundancy check code; or
When the data sequence can not be equally divided, dividing the n1Bit data carries out n1And searching the bit cyclic redundancy check code table entry to obtain the cyclic redundancy check code.
10. The method of cyclic redundancy check of claim 9, wherein said checking the data sequence according to its result comprises:
when the obtained result is 0, the data sequence to be processed is considered to be correct;
and when the obtained result is not 0, the data sequence to be processed is considered to be wrong.
11. An apparatus for performing a cyclic redundancy check on a received data sequence including a cyclic redundancy check code, comprising:
the register is used for equally dividing the data sequence into n-bit data segments according to the high-low order when the data sequence can be equally divided, or
When the data sequence can not be equally divided, dividing the data sequence into a plurality of sections according to the sequence of n bits as a section according to the high-low order, and dividing the rest n1Bit data as the last segment;
the table item generating unit generates a cyclic redundancy check code table item with the same bit as the data segment in the register and stores the table item into the table look-up unit;
the table look-up unit searches the first data segment in the register for the cyclic redundancy check code table entry with the same bit, and sends the obtained corresponding r-bit search result to the processing unit;
the processing unit carries out modulo two addition on the search result and r bit data from the first bit of the second data segment, and replaces the r bit data in the register according to the corresponding bit;
the register overflows the first data segment of the data sequence;
the judging unit judges the total number of the remaining data segments in the register, and the table look-up unit searches the corresponding cyclic redundancy check code table items of the data segment in the register until the data sequence in the register only has the last segment, and sends the obtained cyclic redundancy check code to the checking unit; the check unit performs modulo two addition on the obtained cyclic redundancy check code and the original cyclic redundancy check code, checks the data sequence according to the result of the modulo two addition, and outputs the check result;
when the data sequence cannot be equally divided:
the table look-up unit is divided into a first table look-up unit and a second table look-up unit;
the table item generating unit establishes the table item with n and n in the register1N, n of the same bit of the bit data segment1After the bit cyclic redundancy check code table entry, and the n are combined1The bit cyclic redundancy check code entries are respectively stored in the first table look-up unit and the second table look-up unit;
when the data sequence has more than one segment, selecting the first table look-up unit to carry out n-bit CRC check code table item look-up on the first data segment in the register; and when the data sequence only has the last data segment, selecting a second table look-up unit to look up the last segment of data, wherein the table look-up result is the final CRC check code.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2006101654183A CN101207467B (en) | 2006-12-19 | 2006-12-19 | Generation of cyclic redundancy check code as well as method and apparatus for sending and testing data sequence |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2006101654183A CN101207467B (en) | 2006-12-19 | 2006-12-19 | Generation of cyclic redundancy check code as well as method and apparatus for sending and testing data sequence |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN101207467A CN101207467A (en) | 2008-06-25 |
| CN101207467B true CN101207467B (en) | 2011-05-18 |
Family
ID=39567379
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN2006101654183A Active CN101207467B (en) | 2006-12-19 | 2006-12-19 | Generation of cyclic redundancy check code as well as method and apparatus for sending and testing data sequence |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN101207467B (en) |
Families Citing this family (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102612173B (en) * | 2011-01-21 | 2016-08-10 | 芯讯通无线科技（上海）有限公司 | The means of communication between multi mode terminal and communication module thereof |
| CN103516478B (en) * | 2012-06-29 | 2018-03-13 | 华为技术有限公司 | Method for sending information and equipment |
| CN109391349B (en) * | 2017-08-08 | 2020-04-07 | 维沃移动通信有限公司 | Method and apparatus for cyclic redundancy check |
| EP3667962B1 (en) | 2017-08-08 | 2022-10-26 | Vivo Mobile Communication Co., Ltd. | Method and device for cyclic redundancy check |
| CN109474379B (en) * | 2017-09-08 | 2022-05-06 | 华为技术有限公司 | Encoding method and device |
| CN113608917B (en) * | 2021-06-23 | 2023-07-14 | 苏州浪潮智能科技有限公司 | Method and device for calculating CRC value of arbitrary data |
| CN115001623B (en) * | 2022-05-07 | 2024-04-19 | 通号城市轨道交通技术有限公司 | Method and device for checking vehicle-mounted electronic map data |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1431594A (en) * | 2003-01-27 | 2003-07-23 | 西安电子科技大学 | Method for parallel computing code of CRC in multiple channels and multiple bits |
| CN1633030A (en) * | 2003-12-22 | 2005-06-29 | 普天信息技术研究院 | A rapid calculation method for cyclic redundant check |
-
2006
- 2006-12-19 CN CN2006101654183A patent/CN101207467B/en active Active
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1431594A (en) * | 2003-01-27 | 2003-07-23 | 西安电子科技大学 | Method for parallel computing code of CRC in multiple channels and multiple bits |
| CN1633030A (en) * | 2003-12-22 | 2005-06-29 | 普天信息技术研究院 | A rapid calculation method for cyclic redundant check |
Also Published As
| Publication number | Publication date |
|---|---|
| CN101207467A (en) | 2008-06-25 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN101207467B (en) | Generation of cyclic redundancy check code as well as method and apparatus for sending and testing data sequence | |
| US9071275B2 (en) | Method and device for implementing cyclic redundancy check codes | |
| CN107370560B (en) | Method, device and equipment for coding and rate matching of polarization code | |
| CN101867379B (en) | Cyclic redundancy check-assisted convolutional code decoding method | |
| US10866857B2 (en) | Encoding and decoding of permuted cyclic codes | |
| CN101366183A (en) | Method and apparatus for error management | |
| WO2020237377A1 (en) | Methods and systems for bit error determination and correction | |
| CN113110954A (en) | CRC (Cyclic redundancy check) code parallel computing method and device and application thereof | |
| CN1146116C (en) | Shortened fire code error-trapping decoding method and apparatus | |
| US20090094507A1 (en) | Code error detector and error detecting code generator | |
| CN101151806A (en) | Memory efficient interleaving / de-interleaving utilising the periodicity of the mapping function | |
| EP0608848B1 (en) | Cyclic coding and cyclic redundancy code check processor | |
| Babaie et al. | Double bits error correction using CRC method | |
| CN101803204B (en) | Bit string-error correcting method | |
| CN108574490B (en) | Method and device for calculating Cyclic Redundancy Check (CRC) code | |
| CN111431541B (en) | Method and device for obtaining CRC (cyclic redundancy check) code | |
| US20180309463A1 (en) | Hybrid type iterative decoding method and apparatus | |
| JP2008160663A (en) | Division method for information bit string and its device | |
| CN116048868A (en) | Code generation method, device, equipment and storage medium | |
| JP4379329B2 (en) | CRC generator polynomial selection method, CRC encoding method, and CRC encoding circuit | |
| US7225391B1 (en) | Method and apparatus for parallel computation of linear block codes | |
| KR20140031980A (en) | Error-correcting decoder | |
| JP3579039B2 (en) | Error correction circuit using cyclic code | |
| JPH0998093A (en) | Error correction code decoding method | |
| KR102353983B1 (en) | How to arrange an algorithm in Cyclic Redundancy Check (CRC) |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant |