CN112036117B - CRC (cyclic redundancy check) control system suitable for parallel input data with multiple bit widths - Google Patents
CRC (cyclic redundancy check) control system suitable for parallel input data with multiple bit widths Download PDFInfo
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- CN112036117B CN112036117B CN202010889797.0A CN202010889797A CN112036117B CN 112036117 B CN112036117 B CN 112036117B CN 202010889797 A CN202010889797 A CN 202010889797A CN 112036117 B CN112036117 B CN 112036117B
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- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F30/00—Computer-aided design [CAD]
- G06F30/30—Circuit design
- G06F30/39—Circuit design at the physical level
- G06F30/398—Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM]
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- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
- G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
- G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
- G06F11/1004—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's to protect a block of data words, e.g. CRC or checksum
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
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Abstract
The invention discloses a CRC control system suitable for parallel input data with various bit widths, wherein an AHB interface unit realizes analysis of an AHB access protocol; the CRC calculation unit outputs the CRC value after carrying out CRC calculation on the data source; the CRC preset value unit is used for comparing with a CRC calculation result; the comparison unit is used for comparing the check value with a preset value; the counting unit is used for realizing overtime counting and data source counting in the verification process and generating conditions required by the interrupt generating unit; the interrupt generation unit realizes the generation of external interrupt by the control system. By adopting a mechanism for selecting the optimal computational polynomial based on the verification data source, a data parallel verification mechanism, an interrupt control processing mechanism and the like, the quick parallel verification of different polynomials for different data sources is realized, meanwhile, the working reliability of a control system can be improved through the interrupt processing mechanism, and the problem of the data reliability in an embedded system and an SoC system is solved.
Description
Technical Field
The invention belongs to the technical field of embedded systems and integrated circuit designs, and particularly relates to a CRC (cyclic redundancy check) control system suitable for parallel input data with multiple bit widths.
Background
The high-security high-reliability SoC has extremely high requirements on reliability, which means that the high requirements on the reliability of data in a storage system are put on. In general, a storage system is implemented by using common storage devices such as SRAM, FLASH, etc., and in the process of storing data, the devices are affected by uncertain factors transmitted or externally connected by an internal system, so that the stored data are inconsistent with the original data. To solve the above problem, a cyclic redundancy check (Cyclic Redundancy Check, CRC) mechanism is generally introduced in the design to check the data in the storage system to ensure the reliability of the data. Therefore, it is important to design a CRC check control system, particularly a highly versatile control system.
At present, the main stream CRC check control structure adopts a single calculation polynomial, and the characteristics (such as bit width and data quantity) of data and the working reliability of a controller are not fully considered, so that the control structure has poor universality, low check performance and poor working reliability. Therefore, a verification control system for realizing verification of a data source with the shortest time overhead is urgently needed, and meanwhile, a plurality of calculation polynomials can be selected to promote universality. At present, the existing conversion structure fails to consider the problems, the defects of the corresponding technology are reflected on different layers, and the related documents are searched, so that a method for well solving the problems is not available.
Disclosure of Invention
Aiming at the defects in the prior art, the invention provides a CRC check control system suitable for multiple bit width parallel input data, and aiming at the characteristic that the reliability requirement of a large amount of data in a SoC storage system is high, by adopting a mechanism for selecting an optimal calculation polynomial based on a check data source, a data parallel check mechanism, an interrupt control processing mechanism and the like, the quick parallel check of different polynomials for different data sources can be realized, and meanwhile, the working reliability of the control system can be improved through the interrupt processing mechanism, and the problem of the data reliability in an embedded system and the SoC system is solved.
The invention adopts the following technical scheme:
a CRC check control system suitable for multiple bit width parallel input data comprises an AHB interface unit,
one end of the AHB interface unit is connected with the AHB bus, the other end of the AHB interface unit is respectively connected with the input ends of the CRC calculation unit and the CRC preset value unit, the output ends of the CRC calculation unit and the CRC preset value unit are connected with the interrupt generation unit through the comparison unit, the interrupt generation unit is connected with the counting unit, the checked data source is analyzed through the AHB interface unit, the data is input into the CRC calculation unit, calculation is realized through a CRC calculation polynomial, a CRC value is obtained, the comparison unit is used for comparing the calculated value with the preset value of the CRC preset value unit to obtain a result, the interrupt generation unit is used for outputting the result, and finally the CRC check control of the data is realized.
Specifically, the CRC calculation polynomials include 8, 16, 32, and 64-bit wide calculation polynomials.
Further, the 8, 16, 32 and 64 bit wide computational polynomials are specifically:
f_crc8(x)＝x 8 +x 2 +x+1
f_crc16(x)＝x 16 +x 15 +x 2 +x+1
f_crc32(x)＝x 32 +x 26 +x 23 +x 22 +x 16 +x 12 +x 11 +x 10 +x 8 +x 7 +x 5 +x 4 +x 2 +x+1
f_crc64(x)＝x 64 +x 4 +x 3 +x+1
specifically, the AHB interface unit is used for analyzing an AHB access protocol and processing an AHB interface signal;
the CRC calculation unit selects an optimal calculation polynomial from the polynomial selection structure, and outputs a CRC value after CRC calculation is performed on the data source;
the CRC preset value unit is used for writing a correct check result of the original data source in advance by the AHB interface and comparing the correct check result with a CRC calculation result;
the comparison unit is used for comparing the check value with a preset value and outputting a comparison result;
the counting unit is used for realizing overtime counting and data source counting in the verification process and generating the conditions required by the interrupt generating unit;
and the interrupt generating unit is used for judging the interrupt condition and realizing the generation of external interrupt of the control system.
Compared with the prior art, the invention has at least the following beneficial effects:
the CRC control system suitable for the parallel input data with multiple bit widths can realize the rapid parallel check of the data with different bit widths, and the universality of the check system is improved by adopting a mechanism for selecting the optimal calculation polynomial based on a check data source. According to the bit width characteristics of the data sources, the corresponding calculation polynomial can be flexibly selected, so that the verification system can be used for verification of various data sources, and the verification efficiency is effectively improved by adopting a data parallel verification mechanism. The verification of large-batch data can be realized quickly, and the time cost is greatly reduced; and an interrupt control processing mechanism is adopted, so that the safety and reliability of the operation of a control system are ensured. The interrupt processing mechanism can timely process and report abnormal conditions in the checking system, effectively avoid the occurrence of the 'dead halt' condition of the control system, and greatly improve the working reliability of the control system.
Furthermore, the adopted CRC calculation polynomials comprise 8, 16, 32 and 64-bit data bit width calculation polynomials, and the corresponding calculation polynomials can be flexibly selected according to the bit width characteristics of the data sources, so that the verification system can be used for verification of various data sources, and the universality of the verification system is improved.
Furthermore, the calculation polynomials of the bit widths of 8, 16, 32 and 64 bits of data are provided, and a mathematical algorithm of the calculation polynomials is specifically provided, so that the quick parallel check of the data with different bit widths is realized.
Further, the AHB interface unit is used for analyzing an AHB access protocol and processing AHB interface signals; the CRC calculation unit selects an optimal calculation polynomial from the polynomial selection structure, and outputs a CRC value after CRC calculation is performed on the data source; the CRC preset value unit is used for writing a correct check result of the original data source in advance by the AHB interface and comparing the correct check result with a CRC calculation result; the comparison unit is used for comparing the check value with a preset value and outputting a comparison result; the counting unit is used for realizing overtime counting and data source counting in the verification process and generating the conditions required by the interrupt generating unit; and the interrupt generating unit is used for judging the interrupt condition and realizing the generation of external interrupt of the control system. The organic interconnection of the units works in a coordinated manner, so that the quick parallel check of different polynomials for different data sources is realized, and meanwhile, the working reliability of a control system can be improved through an interrupt processing mechanism.
In conclusion, the invention has flexible and simple structure and high working efficiency, can be suitable for checking various data with different bit widths, is easy to transplant and expand, and has strong universality and high reliability.
The technical scheme of the invention is further described in detail through the drawings and the embodiments.
Drawings
FIG. 1 is a CRC check control system of the present invention;
fig. 2 is a CRC calculation polynomial shift register implementation structure.
Wherein: an AHB interface unit; a CRC calculation unit; CRC preset value unit; 400. a comparison unit; 500. a counting unit; 600. an interrupt generation unit.
Detailed Description
The invention provides a CRC (cyclic redundancy check) control system suitable for multiple bit width parallel input data, which adopts a mechanism for selecting an optimal computational polynomial based on a check data source, a data parallel check mechanism and an interrupt control processing mechanism, realizes the rapid parallel check of different polynomials for different data sources, and improves the data reliability in an embedded system and an SoC (system on chip).
Referring to fig. 1, the present invention relates to a CRC check control system suitable for multiple bit width parallel input data, which can implement data check in a SoC memory system; comprises an AHB interface unit 100, a CRC calculation unit 200, a CRC preset value unit 300, a comparison unit 400, a counting unit 500 and an interrupt generation unit 600.
One end of the AHB interface unit 100 is connected with an AHB bus, the other end is respectively connected with input ends of the CRC calculation unit 200 and the CRC preset value unit 300, output ends of the CRC calculation unit 200 and the CRC preset value unit 300 are connected with the interrupt generation unit 600 through the comparison unit 400, the interrupt generation unit 600 is connected with the counting unit 500, a checked data source is analyzed through the AHB interface unit 100, then the data is input into the CRC calculation unit 200, calculation is realized through an optimal calculation polynomial, a CRC value is obtained, the calculated value and the preset value of the CRC preset value unit 300 are compared through the comparison unit 400, a comparison result is generated, the result is output through the interrupt generation unit 600, and finally the CRC check control of the data is realized.
The AHB interface unit 100 is configured to analyze an AHB access protocol and process an AHB interface signal;
a CRC calculation unit 200, which selects the best calculation polynomial from the polynomial selection structure, and outputs the CRC value after performing CRC calculation on the data source;
a CRC preset value unit 300, which is written in the correct check result of the original data source in advance by the AHB interface and is used for comparing with the result of CRC calculation;
the comparison unit 400 is used for comparing the check value with a preset value and outputting a comparison result;
the counting unit 500 is used for realizing overtime counting and data source counting in the verification process and generating the conditions required by the interrupt generating unit;
8. The 16, 32 and 64 bits corresponding CRC calculation polynomials realize four calculation polynomials with different bit widths, and according to the characteristics of checked data, the corresponding optimal calculation polynomials are selected for CRC check to generate CRC values, specifically:
f_crc8(x)＝x 8 +x 2 +x+1
f_crc16(x)＝x 16 +x 15 +x 2 +x+1
f_crc32(x)＝x 32 +x 26 +x 23 +x 22 +x 16 +x 12 +x 11 +x 10 +x 8 +x 7 +x 5 +x 4 +x 2 +x+1
f_crc64(x)＝x 64 +x 4 +x 3 +x+1
referring to fig. 2, the CRC calculation polynomial is implemented by a shift register structure, and four calculation polynomials with different bit widths are implemented by a multi-stage shift register structure, so as to achieve the purpose of quickly implementing CRC calculation by hardware.
CRC8 shift register structure, interconnection is realized by 8 registers and 3 exclusive OR gates. In the CRC8 shift register structure, corresponding to a CRC8 calculation polynomial, the 7 th bit, the 1 st bit and the 0 th bit are subjected to exclusive OR operation.
The CRC16 shift register structure is interconnected by 16 registers and 4 exclusive OR gates. In the CRC16 shift register structure, the 15 th bit, the 14 th bit, the 1 st bit and the 0 th bit are exclusive-ored corresponding to a CRC16 calculation polynomial.
The CRC32 shift register structure is interconnected by 32 registers and 14 exclusive OR gates. In the CRC32 shift register structure, corresponding to a CRC32 calculation polynomial, the 31 st bit, the 25 th bit, the 22 nd bit, the 21 st bit, the 15 th bit, the 11 th bit, the 10 th bit, the 9 th bit, the 7 th bit, the 6 th bit, the 4 th bit, the 3 rd bit, the 1 st bit and the 0 th bit are subjected to exclusive OR operation.
The CRC64 shift register structure is interconnected by 64 registers and 4 exclusive OR gates. In the CRC64 shift register structure, the 63 rd bit, the 3 rd bit, the 2 nd bit and the 0 th bit are exclusive-ored corresponding to the CRC64 calculation polynomial.
For the purpose of making the objects, technical solutions and advantages of the embodiments of the present invention more apparent, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention, and it is apparent that the described embodiments are some embodiments of the present invention, but not all embodiments of the present invention. The components of the embodiments of the present invention generally described and illustrated in the figures herein may be arranged and designed in a wide variety of different configurations. Thus, the following detailed description of the embodiments of the invention, as presented in the figures, is not intended to limit the scope of the invention, as claimed, but is merely representative of selected embodiments of the invention. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.
The invention realizes the analysis of the AHB access protocol through the AHB interface unit 100; the CRC calculation unit 200 realizes the selection of a CRC calculation polynomial and performs CRC check on the original data to generate a CRC check value; the CRC preset unit 300 stores a correct check result to be compared; the comparison unit 400 is used for comparing the check value with a preset value and outputting a comparison result; the counting unit 500 is used for performing timeout counting on the verification process and counting on the data source, and generating the condition required by the interrupt generating unit; the interrupt generation unit 600 implements generation of control system interrupts.
The invention is successfully applied to a high-performance SoC chip based on ARM Cortex-R4 processor cores. The method realizes the verification and calculation of the memory space data such as FLASH, SRAM and the like in the SoC chip, can select the optimal characteristic polynomial to carry out CRC according to the characteristics of the memory space data, has high whole calculation efficiency, and ensures the reliability and the safety of the data in the chip.
According to the CRC control structure in FIG. 1, the CRC control system applicable to multiple bit width parallel input data can be obtained by adopting the polynomial shift register implementation structure in FIG. 2.
In summary, the CRC control system suitable for multiple bit width parallel input data according to the present invention can realize data source verification with the shortest time overhead, and can select multiple computational polynomials to improve versatility. The system has simple structure and easy realization, and can be transplanted into an integrated circuit system with the requirement on data verification.
The above is only for illustrating the technical idea of the present invention, and the protection scope of the present invention is not limited by this, and any modification made on the basis of the technical scheme according to the technical idea of the present invention falls within the protection scope of the claims of the present invention.
Claims (3)
1. A CRC check control system suitable for multiple bit width parallel input data, characterized by comprising an AHB interface unit (100),
one end of the AHB interface unit (100) is connected with an AHB bus, the other end of the AHB interface unit is respectively connected with input ends of the CRC calculation unit (200) and the CRC preset value unit (300), output ends of the CRC calculation unit (200) and the CRC preset value unit (300) are connected with the interrupt generation unit (600) through the comparison unit (400), the interrupt generation unit (600) is connected with the counting unit (500), a checked data source is analyzed through the AHB interface unit (100), the data is input into the CRC calculation unit (200), calculation is realized through a CRC calculation polynomial, a CRC value is obtained, a result is obtained through comparison of the calculated value and the preset value of the CRC preset value unit (300), the result is output through the interrupt generation unit (600), and finally CRC check control of the data is realized;
an AHB interface unit (100) for analyzing an AHB access protocol and processing an AHB interface signal;
a CRC calculation unit (200) for selecting an optimal calculation polynomial from the polynomial selection structure, performing CRC calculation on the data source, and outputting a CRC value;
a CRC preset value unit (300) which is written in the correct check result of the original data source in advance by the AHB interface and is used for comparing with the result of CRC calculation;
the comparison unit (400) is used for comparing the check value with a preset value and outputting a comparison result;
the counting unit (500) is used for realizing overtime counting and data source counting in the verification process and generating the conditions required by the interrupt generating unit;
and the interrupt generating unit (600) judges the interrupt condition and realizes the generation of external interrupt of the control system.
2. The CRC check control system for multiple bit wide parallel input data as claimed in claim 1, wherein the CRC calculation polynomials include 8, 16, 32, and 64 bit wide calculation polynomials.
3. The CRC check control system for multiple bit wide parallel input data according to claim 2, characterized in that the 8, 16, 32 and 64 bit wide computational polynomials are specifically:
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