CN108318028A - A kind of navigation system core processing circuit design method - Google Patents
A kind of navigation system core processing circuit design method Download PDFInfo
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- CN108318028A CN108318028A CN201711389031.0A CN201711389031A CN108318028A CN 108318028 A CN108318028 A CN 108318028A CN 201711389031 A CN201711389031 A CN 201711389031A CN 108318028 A CN108318028 A CN 108318028A
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01C—MEASURING DISTANCES, LEVELS OR BEARINGS; SURVEYING; NAVIGATION; GYROSCOPIC INSTRUMENTS; PHOTOGRAMMETRY OR VIDEOGRAMMETRY
- G01C21/00—Navigation; Navigational instruments not provided for in groups G01C1/00 - G01C19/00
- G01C21/10—Navigation; Navigational instruments not provided for in groups G01C1/00 - G01C19/00 by using measurements of speed or acceleration
- G01C21/12—Navigation; Navigational instruments not provided for in groups G01C1/00 - G01C19/00 by using measurements of speed or acceleration executed aboard the object being navigated; Dead reckoning
- G01C21/16—Navigation; Navigational instruments not provided for in groups G01C1/00 - G01C19/00 by using measurements of speed or acceleration executed aboard the object being navigated; Dead reckoning by integrating acceleration or speed, i.e. inertial navigation
Abstract
The invention belongs to airborne and missile-borne inertial navigation data processing technology fields, are related to a kind of navigation system core processing circuit design method；The present invention discloses a kind of design method of the inertial navigation system core processing circuit based on multi-core processor, including：1. the core processing circuit based on domestic multi-core processor FT Q6713J/500 multi-core processor inertial navigation systems；2. high-precision temperature sensor Acquisition Circuit design；3. the High Speed Data Acquisition Circuit of high real-time high robust designs；4. the design method of high speed 1553B bus circuits；5. the health control of inertial navigation system designs.By designing above, multi-functional, highly integrated inertial navigation system core processing circuit is realized.
Description
Technical field
The invention belongs to airborne and missile-borne inertial navigation data processing technology fields, are related to a kind of navigation system core processing
Circuit design method.
Background technology
Inertial navigation technology has the advantage that independence is strong, short-term accuracy is high, real-time, but the mistake of its inertia component
The poor cumulative effect long period stability of inertial navigation, it is difficult to complete the navigation task of the higher long endurance of precision.With used
Property technology high-speed development, the navigation sensor of more and more types is introduced in inertial navigation system, to the data of navigation system
Processing platform data processing and resolving ability, sensor fusion faculty, health monitoring and managerial ability also proposed higher want
It asks, therefore develops with Fusion ability, real-time is good, miniaturization, inexpensive, while meeting high-precision
It spends, the computing platform of the integrated navigation system of high dynamic and high reliability, is an important side of current inertial technology development
To.
A kind of patent " navigation calculation device based on heterogeneous polynuclear framework " (Shen of Huazhong Photoelectric Technology Inst.'s application
Please number：CN201610935841.0, publication number：CN106547237A a kind of heterogeneous polynuclear based on ARM+DSP is disclosed in)
The resolver of framework, due to the use of the framework of heterogeneous polynuclear, however it remains the power consumption of system is larger, data between heterogeneous polynuclear
The relatively low disadvantage of efficiency of transmission.
A kind of patent " the inertia based on multi-core DSP/satellite deep combination letter of Beijing Automation Control Equipment Research Institute's application
Breath processing hardware platform " (application number CN201410336170.7, publication number CN105319569A) designs hardware using multi-core DSP
Platform completes different resolvings and deep combination function using 4 cores, but this it is hard-wired have a single function, fail integrated total
Line transmits, the health monitoring function of sensor acquisition and data transmission and navigation system.
Invention content
The object of the invention is to realize that one kind having Fusion ability, meets high-precision, high dynamic and height
A kind of core processing circuit that the integrated navigation of reliability requires, it is proposed that navigation based on FT-Q6713J/500 core processors
System core circuit design method.
Technical solution of the present invention：A kind of navigation system core processing circuit design method, which is characterized in that packet
Include following steps：
The first step is the core circuit design based on multinuclear FT-Q6713J/500 processor chips；
Second step is that the temperature collection circuit of multi-channel high-accuracy designs；
Third step is the data transmission circuit of high real-time high robust；
4th step is the health monitoring circuit design of inertial navigation system；
5th step is the design of high speed 1553B bus circuits；
6th step is the health monitoring circuit design of inertial navigation system.
The core circuit design of the first step is using multinuclear FT6713-500 processor chips, while using being based on
The internal bootstrap mode of EMIF buses.
The bootstrap approach is in multinuclear FT6713-500 processor chips bootstrap process, and Core0 is by being resident
Line programing function generates object code and completes programming；The guiding of main core Core0 is completed after system electrification first, then passes through other cores
Global address with the completion machine code of Core0 from Flash to the carrying of the on-chip memory of other each Core, last triggering
The entry address of each core, the reset for completing each core enter entrance.
The second step temperature collection circuit is designed as being based on special A/D chip ADS1148, ADS1148 of high precision measuring temperature
Internal there are two identical constant-current source IDAC, and the parameter of two current sources is identical, does not introduce measurement error；Design
The middle connection using three-wire system RTD generates reference voltage using a kind of structure of rate, improves the precision of system；It is directed to temperature simultaneously
The characteristic of sensor nonlinear measures temperature using the method that least square polynomial fit, dichotomy are tabled look-up non-linear
Error is corrected and has been compensated, and the precision that system temperature measures is improved.
The third step data transmission circuit is designed as in inertial navigation system, is needed to have and is collected sensor
Data are real-time, are reliably transmitted and resolve, collected using the transmission of full duplex dual redundant High Speed Serial all the way in design
Gyro and plus table pulse information；Traffic rate bit rate is not less than 2Mbps；Communication interface circuit should have redundancy, fault-tolerant, error detection and
Can self test capability to ensure the reliability of transmission data, while communication process is not take up cpu resource；
The communications protocol of the High Speed Serial transmission acquisition is that each cycle is configurable per channel transceiving data length in design,
Ranging from 0-2N Byte are configured, the ranging from 1-25 of wherein N, N default to 15, and under default length, each cycle is sent per channel
It is a group that valid data, which are 15 words, and each word is defined as a frame in a group, every group and must be synchronized before sending per frame data,
There are check bit, the communication data of High Speed Serial to use Manchester's code mode, agreement group synchronization signal, frame synchronization letter per frame
Number, the graceful code format of verification bit width and data, when being sent per frame data a high position in preceding, low level rear, per frame data format, number
It is II type biphase level code of Manchester according to code, logic 1 is bipolar coding signal 1/0, logical zero position bipolar coding signal 0/1, mistake
Zero saltus step is happened at midpoint when each.
The High Speed Serial transmission acquisition reliability refers in the case where meeting 0.5ms communication cycles, per a group data
In by increasing the means such as frame copy, check code and Reliability codes improve communication reliability；To ensure the Shandong of communications protocol
Stick realizes following functions when designing sending and receiving logic：
A) on sending logical design, A, channel B are mutual indepedent, can be staggered on data transmission period, and staggering time is adjustable,
Range：0~63.75us, resolution ratio 0.25us；Avoid external disturbance synchronization cause A, in channel B signal distortion,
But it should ensure that 0.5ms communication cycle requirements.
B) in receiving circuit, setting monitoring circuit, monitoring receives time out fault and timing error, and can complete mistake
The accidentally set of mark, error count and the reset for receiving logic.
C) transceiver logic circuit considers testability in design, tries and provides test result in power-on self-test or can guarantee
The test of function is completed under the control of outer logic circuit.
D) two channel reception logics of A, B should all design buffering area, and it is correct to receive the newest a group of buffering area reception storage
The design of data, buffering area avoids external read operation and internal write operation resource competing problem by using ping-pong operation, ensures
Outer logic circuit can read the last correct data received at any time.
If e) for having reception mistake in a group data of reception, and correct data cannot be restored, then cluster data are abandoned,
There is direct or indirect record to abandoning behavior and abandoning number simultaneously.
The design of the 4th step high speed 1553B bus circuits；
High speed 1553B modules realize protocol conversion, HT- using high speed 1553B protocol chips HT-61843GB-2
61843GB-2 includes independent two channel Communication Control logics, has the flexible data buffer zones RT, and message package monitoring may be selected,
Support MT/RT patterns simultaneously.
The health monitoring circuit design of the 5th step inertial navigation system.
Inertial navigation system is by designing heartbeat monitor, state recognition and power supply and driving current detection circuit, to real
The quick detection of existing failure, and then ensure the operation health of navigation system core circuit, health detection circuit design includes：
A) heartbeat discrete magnitude observation circuit:Discrete magnitude input and output include 4 road reseting input signals, and 1 tunnel resets enabled defeated
Enter signal, the programming of 1 tunnel enables input signal, 4 road DSP heartbeats output signals and 4 road DSP discrete output signals, is required to optocoupler
Isolation.Signal isolation uses HCPL-6651 or HCPL-0631 according to number of channels, design.
B) power supply and secondary power supply detection circuit
After voltage acquisition front end is by amplifier FX147 conditionings, into A/D Acquisition Circuits.
Compared with the prior art, the present invention has the following advantages：
First, different function core processing in navigation system is realized using high-performance multi-core processor, improves system collection
Cheng Du reduces power consumption, while greatly facilitating the realization of the data fusion of different sensors.
Second, the Acquisition Circuit of multi-channel high-accuracy can more in real time, the temperature in more accurate response sensor cavity,
To provide accurately input source for accurate temperature compensation algorithm.
Third is designed by the data transmission circuit of high real-time high robust, ensures timely to receive in navigation system
To reliably sensing data, lay a good foundation for the correctness of navigation calculation.
4th, it is designed by high speed 1553B bus circuits, meets big data quantity in rocket and guided missile dispatch control system
The demand of transmission.
5th, by designing heartbeat inspecting circuit, power sense circuit realizes the health monitoring of navigation system, improves system
Safety and reliability.
Description of the drawings
Fig. 1 is the system architecture diagram of the present invention.
Fig. 2 is platinum resistor temperature measuring RTD circuit theory schematic diagrams
Fig. 3 is High Speed Serial data format
Fig. 4 is II type biphase level code of Manchester
Fig. 5 is high speed string data coding requirement
Fig. 6 is high speed 1553B circuit function schematic diagrams
Fig. 7 is heartbeat discrete magnitude detection circuit
Specific implementation mode
A kind of navigation system core processing circuit design method, includes the following steps：
Specific implementation details are as follows：As shown in Figure 1
(1) the core circuit design method based on multinuclear FT-Q6713J/500 processor chips.
Traditional navigation system core processing circuit is generally made of two parts, and a part is that monokaryon DSP realizes inertia solution
It calculates, gyro and acceleration acquisition, another part realize RS422 by separate processor, the interfaces such as RS429,1553B and bus
It acquires and transmits, realize that coupling, this isomery framework not only cause to lead by twoport or asynchronous serial bus between two parts
System processor type of navigating is various, and exploitation is complicated, and between processor data transmission efficiency it is low be unfavorable for different sensors it
Between depth coupling.Using multinuclear FT6713-500 processor chips, BootLoader technology is to apply difficult point, and this method uses
Internal bootstrap mode based on EMIF buses, which do not need the participation of other processors, are a kind of independent load modes, together
When for external bootstrap approach, save I/O and memory resource.It booted in multinuclear FT6713-500 processor chips
Cheng Zhong, Core0 generate object code by resident online programming function and complete programming.Main core is completed after system electrification first
The guiding of Core0, then by the global addresses of other cores with the completion machine code of Core0 from Flash to the piece of other each Core
The carrying of upper memory, the entry address of each core of last triggering, the reset for completing each core enter entrance.It, which is powered on, loaded
Journey is as shown in Figure 1.
(2) the temperature collection circuit design method of multi-channel high-accuracy.
Laser gyro in inertial navigation system, the sensors such as accelerometer are temperature sensitive sensor, collection result
It is both needed to be compensated according to temperature change, therefore sensor accuracy and temperature acquisition precision are closely related, temperature acquisition work is
An important factor for influence system reliable and stable work.For this reason, it may be necessary to design temperature measuring circuit that is accurate, reliable and stablizing.
Temperature collection circuit design is based on inside high precision measuring temperature special A/D chip ADS1148, ADS1148 in the design
There are two identical constant-current source IDAC, it is ensured that the parameter of two current sources is identical, avoids introducing measurement error.
Reference voltage is generated using a kind of structure of rate using the connection of three-wire system RTD (platinum resistance) in the design, is improved
The precision of system.
It is directed to the nonlinear characteristic of temperature sensor, the side tabled look-up using least square polynomial fit, dichotomy simultaneously
The nonlinearity erron that method measures temperature is corrected and has been compensated, and the precision of system temperature measurement is further improved.
(3) the data transmission circuit design of high real-time high robust
In inertial navigation system, needs to have when that sensor is collected into total factually, is reliably transmitted reconciliation
It calculates.Collected gyro is transmitted using full duplex dual redundant High Speed Serial all the way in design and adds table pulse information.Traffic rate
Bit rate is not less than 2Mbps；Communication interface circuit should have redundancy, fault-tolerant, error detection and can self test capability to ensure transmission data
Reliability, while communication process is not take up cpu resource；
Configurable per channel transceiving data length (0~2N Byte, 15) N=1~25, N are defaulted to each cycle in design.
Under default length (other length and so on), it is 15 words (being defined as a group) that each cycle, which sends valid data per channel,
Each word is defined as a frame in a group, and every group and every frame data must synchronize before sending, have check bit, data format to see per frame
Fig. 5；
In the case where meeting 0.5ms communication cycles, passes through in every a group data and increase frame copy, check code and reliability
The means such as coding improve communication reliability；
The communication data of High Speed Serial uses Manchester's code mode, agreement group synchronization signal, frame synchronizing signal, verification
Bit width and the graceful code format of data as shown in figure 4, when being sent per frame data a high position in preceding, low level rear, per frame data format
As shown in Figure 7.
Numeric data code be II type biphase level code of Manchester, logic 1 be bipolar coding signal 1/0 (i.e. a positive pulse after
With a negative pulse).Logical zero position bipolar coding signal 0/1 (i.e. a negative pulse is followed by a positive pulse).Zero passage saltus step
Midpoint when being happened at each.
To ensure the robustness of communications protocol, following functions are realized when designing sending and receiving logic：
A) on sending logical design, A, channel B are mutual indepedent, can be staggered on data transmission period, and staggering time is adjustable,
Range：0~63.75us, resolution ratio 0.25us；Avoid external disturbance synchronization cause A, in channel B signal distortion,
But it should ensure that 0.5ms communication cycle requirements.
B) in receiving circuit, setting monitoring circuit, monitoring receives time out fault and timing error, and can complete mistake
The accidentally set of mark, error count and the reset for receiving logic.
C) transceiver logic circuit considers testability in design, tries and provides test result in power-on self-test or can guarantee
The test of function is completed under the control of outer logic circuit.
D) two channel reception logics of A, B should all design buffering area, and it is correct to receive the newest a group of buffering area reception storage
The design of data, buffering area avoids external read operation and internal write operation resource competing problem by using ping-pong operation, ensures
Outer logic circuit can read the last correct data received at any time.
If e) for having reception mistake in a group data of reception, and correct data cannot be restored, then cluster data are abandoned,
There is direct or indirect record to abandoning behavior and abandoning number simultaneously.
(4) design method of high speed 1553B bus circuits；
With the continuous improvement of guided missile functional performance complexity, the amount of information exchange between missile equipment increasingly increases, right
The requirement of 1553B bus system message transmission rates is higher and higher.Currently, domestic common 1553B bus required standards transmission
Rate is 1Mbps, can no longer meet the basic need of every data exchange during modern Aviation, space flight and surface car system are applied
It asks.
High speed 1553B modules realize protocol conversion, HT- using high speed 1553B protocol chips HT-61843GB-2
61843GB-2 includes independent two channel Communication Control logics, has the flexible data buffer zones RT, and message package monitoring may be selected,
Support MT/RT patterns simultaneously, whole principle is as indicated at 3.
(5) the health monitoring circuit design of inertial navigation system.
Inertial navigation system is usually likened to the eyes of aircraft, and safety and reliability has aircraft performance
Extremely important effect, by designing heartbeat monitor, state recognition and power supply and driving current detection circuit, to realize event
The quick detection of barrier, and then ensure the operation health of navigation system core circuit.
Health detection circuit design includes：
A. heartbeat discrete magnitude observation circuit
Discrete magnitude input and output include 4 road reseting input signals, and 1 tunnel, which resets, enables input signal, the enabled input of 1 tunnel programming
Signal, 4 road DSP heartbeats output signals and 4 road DSP discrete output signals, are required to light-coupled isolation.Signal isolation is according to port number
Amount, design use HCPL-6651 or HCPL-0631.
Power supply and secondary power supply detection circuit
Due to the use of multiple sensors in navigation system, the supply voltage of different sensors is different, while core electricity
There is also the requirements of multiple voltage supply for the various integrated circuits used in road, therefore to external core processing circuit externally fed electricity
The monitoring of pressure and two times transfer voltage is particularly important.
After voltage acquisition front end is by amplifier FX147 conditionings, into A/D Acquisition Circuits.Circuit theory is shown in 8.
The present invention has been successfully applied in certain model laser-inertial navigation system, according to leading for the method for the invention design
The boat system core solves the function of real-time acquisition and depth integration of the navigation system to multisensor, and realize high safety and
The requirement of high reliability, works well.
Claims (9)
1. a kind of navigation system core processing circuit design method, which is characterized in that include the following steps：
The first step is the core circuit design based on multinuclear FT-Q6713J/500 processor chips；
Second step is that the temperature collection circuit of multi-channel high-accuracy designs；
Third step is the data transmission circuit of high real-time high robust；
4th step is the health monitoring circuit design of inertial navigation system；
5th step is the design of high speed 1553B bus circuits；
6th step is the health monitoring circuit design of inertial navigation system.
2. navigation system core processing circuit design method as described in claim 1, which is characterized in that the core of the first step
Electrocardio road is designed as using multinuclear FT6713-500 processor chips, while using the internal bootstrap mode based on EMIF buses.
3. navigation system core processing circuit design method as claimed in claim 2, which is characterized in that the bootstrap approach is
In multinuclear FT6713-500 processor chips bootstrap process, Core0 generates object code simultaneously by resident online programming function
Complete programming；Complete the guiding of main core Core0 after system electrification first, then complete with Core0 by the global addresses of other cores
It is completed each from Flash to the carrying of the on-chip memory of other each Core, the entry address of each core of last triggering at machine code
The reset of a core enters entrance.
4. navigation system core processing circuit design method as described in claim 1, which is characterized in that the second step temperature
Acquisition Circuit is designed as based on there are two identical constant currents inside special A/D chip ADS1148, ADS1148 of high precision measuring temperature
The parameter of source IDAC, two current sources are identical, do not introduce measurement error；It is adopted using the connection of three-wire system RTD in design
Reference voltage is generated with a kind of structure of rate, improves the precision of system；It is directed to the nonlinear characteristic of temperature sensor simultaneously, uses
The nonlinearity erron that the method that least square polynomial fit, dichotomy are tabled look-up measures temperature is corrected and has been compensated, and is carried
The precision that high system temperature measures.
5. navigation system core processing circuit design method as described in claim 1, which is characterized in that the third step data
Transmission circuit is designed as in inertial navigation system, needs to have sensor collecting data in real time, reliably pass
Defeated and resolving transmits collected gyro using full duplex dual redundant High Speed Serial all the way in design and adds table pulse information；It is logical
Believe that rate bit rate is not less than 2Mbps；Communication interface circuit should have redundancy, fault-tolerant, error detection and can self test capability to ensure to transmit
The reliability of data, while communication process is not take up cpu resource.
6. navigation system core processing circuit design method as claimed in claim 5, which is characterized in that the High Speed Serial passes
The communications protocol of defeated acquisition is that each cycle is configurable per channel transceiving data length in design, configures ranging from 0-2N Byte,
The ranging from 1-25 of middle N, N default to 15, and under default length, it is one that the every channel transmission valid data of each cycle, which are 15 words,
Group, each word is defined as a frame in a group, and every group and every frame data must synchronize before sending, there is check bit, high speed string per frame
The communication data of mouth uses Manchester's code mode, arranges group synchronization signal, frame synchronizing signal, verification bit width and data
Graceful code format, for a high position in preceding, low level in rear, every frame data format, numeric data code is that II type of Manchester is double when being sent per frame data
Phase level code, logic 1 are bipolar coding signal 1/0, logical zero position bipolar coding signal 0/1, when zero passage saltus step is happened at each
Midpoint.
7. navigation system core processing circuit design method as claimed in claim 5, which is characterized in that the High Speed Serial passes
Defeated acquisition reliability refers to passing through in every a group data in the case where meeting 0.5ms communication cycles and increasing frame copy, check code
And the means such as Reliability codes improve communication reliability；It is real when designing sending and receiving logic to ensure the robustness of communications protocol
Existing following functions：
A) on sending logical design, A, channel B are mutual indepedent, can be staggered on data transmission period, and staggering time is adjustable, model
It encloses：0~63.75us, resolution ratio 0.25us；Avoid external disturbance synchronization cause A, in channel B signal distortion, but answer
Ensure the requirement of 0.5ms communication cycles.
B) in receiving circuit, setting monitoring circuit, monitoring receives time out fault and timing error, and can complete wrong mark
Set, error count and the reset for receiving logic of will.
C) transceiver logic circuit considers testability in design, tries and provides test result in power-on self-test or can guarantee outside
The test of function is completed under the control of portion's logic circuit.
D) two channel reception logics of A, B should all design buffering area, receive buffering area and receive the newest a group correct data of storage,
The design of buffering area avoids external read operation and internal write operation resource competing problem by using ping-pong operation, ensures external patrol
The last correct data received can be read at any time by collecting circuit.
If e) for having reception mistake in a group data of reception, and correct data cannot be restored, then cluster data are abandoned, simultaneously
There is direct or indirect record to abandoning behavior and abandoning number.
8. navigation system core processing circuit design method as described in claim 1, which is characterized in that the 4th step high speed
The design of 1553B bus circuits；
High speed 1553B modules realize protocol conversion using high speed 1553B protocol chips HT-61843GB-2, in HT-61843GB-2
Containing independent two channel Communication Control logics, there is the flexible data buffer zones RT, message package monitoring may be selected, support MT/ simultaneously
RT patterns.
9. navigation system core processing circuit design method as described in claim 1, which is characterized in that the 5th step inertia
The health monitoring circuit design of navigation system.
Inertial navigation system is by designing heartbeat monitor, state recognition and power supply and driving current detection circuit, to realize event
The quick detection of barrier, and then ensure the operation health of navigation system core circuit, health detection circuit design includes：
A) heartbeat discrete magnitude observation circuit:Discrete magnitude input and output include 4 road reseting input signals, and 1 tunnel resets enabled input letter
Number, the programming of 1 tunnel enables input signal, 4 road DSP heartbeats output signals and 4 road DSP discrete output signals, is required to light-coupled isolation.
Signal isolation uses HCPL-6651 or HCPL-0631 according to number of channels, design.
B) power supply and secondary power supply detection circuit
After voltage acquisition front end is by amplifier FX147 conditionings, into A/D Acquisition Circuits.
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| CN110262331A (en) * | 2019-06-12 | 2019-09-20 | 北京航天控制仪器研究所 | It is a kind of adapt to moving base calibration multi-mode gyro add square and aim at interface circuit |
| CN110989427A (en) * | 2019-11-19 | 2020-04-10 | 中国航空工业集团公司西安航空计算技术研究所 | Fault detection and health management method for multiprocessor computer |
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| CN110989427A (en) * | 2019-11-19 | 2020-04-10 | 中国航空工业集团公司西安航空计算技术研究所 | Fault detection and health management method for multiprocessor computer |
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| CN114020070B (en) * | 2021-10-15 | 2023-03-31 | 北京航天控制仪器研究所 | Temperature control system for compatible two-type inertial platform |
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