CN111078612A - FPGA-based biss-c protocol decoding system - Google Patents
FPGA-based biss-c protocol decoding system Download PDFInfo
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- CN111078612A CN111078612A CN201911090254.6A CN201911090254A CN111078612A CN 111078612 A CN111078612 A CN 111078612A CN 201911090254 A CN201911090254 A CN 201911090254A CN 111078612 A CN111078612 A CN 111078612A
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
- G06F13/4282—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus
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- G01C—MEASURING DISTANCES, LEVELS OR BEARINGS; SURVEYING; NAVIGATION; GYROSCOPIC INSTRUMENTS; PHOTOGRAMMETRY OR VIDEOGRAMMETRY
- G01C25/00—Manufacturing, calibrating, cleaning, or repairing instruments or devices referred to in the other groups of this subclass
- G01C25/005—Manufacturing, calibrating, cleaning, or repairing instruments or devices referred to in the other groups of this subclass initial alignment, calibration or starting-up of inertial devices
Abstract
The utility model discloses a Field Programmable Gate Array (FPGA) -based biss-c protocol decoding system, which belongs to the technical field of inertial navigation systems. The system comprises: the BISS-C encoder is used for providing a position request and clock information for the absolute encoder, acquiring data at a position synchronous with a clock signal after receiving the clock signal, and providing the data to the data acquisition module; the data acquisition module is used for receiving slo position data of the rotary table and navigation data of the inertial system; the coding module is used for coding according to the position data and the navigation data received by the data acquisition module to obtain coded data; and the decoding module is used for decoding the coded data received from the coding module to obtain the decoded data. The system has important significance for improving the test quality of the inertial navigation system.
Description
Technical Field
The invention relates to the technical field of inertial navigation system calibration, in particular to a FPGA-based biss-c protocol decoding system.
Background
The attitude accuracy of the high-precision inertial navigation system is a key index for measuring the long-term navigation performance of the high-precision inertial navigation system. Typically, before using high precision inertial navigation, its precision must be evaluated. The attitude precision evaluation provides not only attitude precision indexes of the high-precision inertial navigation system, but also provides a basis for precision analysis of the weapon platform. Therefore, the simulation test system is established, the carrier motion is simulated, and the simulation test system is combined with the vehicle test, so that the simulation test system has important significance for improving the test quality of the inertial navigation system. The precision evaluation equipment commonly used at home and abroad is a high-precision rotary table. Absolute angular encoders are commonly used to measure the azimuth, pitch and roll angles of a turntable. The absolute angle encoder adopts a serial interface protocol to exchange data with a data receiving system. The data protocol biss-c is the open digital interface protocol introduced by ic-haus in 2002. The bis-c interface protocol provides a two-way fast communication standard for the sensors and actuators. It can be implemented in simple hardware. The method is suitable for real-time data acquisition. Compared with other interfaces, the method has leading advantages in the aspects of openness, high speed, networking mode, line delay compensation and the like. The decoding of the bis-c interface protocol may be implemented using hardware decoding, software decoding, or hybrid decoding. Compared with software decoding, hardware decoding can provide higher communication speed and save the cost of external logic circuits.
However, in the conventional precision evaluation test, the angle information of the turntable is sent to the user through the upper computer software of the turntable, and the time delay is difficult to estimate accurately. This results in difficulty in time synchronization between the turntable output attitude reference data and the inertial navigation system attitude measurement information.
Disclosure of Invention
In view of the above, the invention provides a decoding system of a bios-c protocol based on an FPGA, which realizes a bios-c data acquisition system based on real-time, synchronous and high-speed hardware and software of the FPGA, and has an important meaning for improving the test quality of an inertial navigation system, thereby being more practical.
In order to achieve the purpose, the technical scheme of the FPGA-based biss-c protocol decoding system provided by the invention is as follows:
the decoding system of the biss-c protocol based on the FPGA provided by the invention comprises:
a BISS-C encoder for providing a position request and clock information to the absolute encoder;
after receiving the clock signal, acquiring data at a position synchronous with the clock signal, and providing the data to the data acquisition module;
the data acquisition module is used for receiving slo position data of the rotary table and navigation data of the inertial navigation system;
the coding module is used for coding according to the position data and the navigation data received by the data acquisition module to obtain coded data;
the decoding module is used for decoding the coded data received from the coding module to obtain decoded data;
and the upper computer is used for displaying the decoded data.
The FPGA-based biss-c protocol decoding system provided by the invention can be further realized by adopting the following technical measures.
Preferably, the data acquisition module includes an FPGA minimum system circuit and a corresponding peripheral circuit, and specifically includes:
RS422 interface: the system comprises a transmitter and a receiver, wherein the transmitter is used for transmitting an ma clock and receiving slo position data and navigation data from an inertial navigation system;
an RS232 interface: used for communicating with the rotary table and the upper computer.
Preferably, the decoding system of the biss-c protocol based on the FPGA further comprises:
and the optical coupler is used for realizing data interaction of the data acquisition system in an isolated manner, wherein the optical coupler is arranged between the interface chip and the FPGA core module.
Preferably, each voltage of the FPGA is provided with a respective patch capacitor.
Preferably, the operation mode of the clock includes:
when the clock does not work, the clock signal and the position signal are set to be high level;
when the clock starts to work, the encoder sets the signal low to indicate "acknowledge" on the second rising edge;
after waiting for n1 clocks, there will be an adjacent high "start" and a low "0" as symbols;
the next 29 bits are position information, followed by "error" and "warning" to check whether the decoding is normal, which are zero, indicating an error in the decoding;
then, six bits of cyclic redundancy check bits are used; when the time is out, the clock is set to be high, and the encoder signal is set to be low;
after waiting n2 clocks, the encoder signal sets it high again and waits for the next set of data to be released;
where the number of clocks for n1 and n2 is not fixed, typically 2-5 clocks.
As a preference, the first and second liquid crystal compositions are,
the cyclic redundancy check formula g (x) ═ x6+ x + 1.
Preferably, each acquisition requires 150 clock cycles, and if n1 or n2 has more than 50 clocks, the clocks will be directly interrupted, acquisition is incorrect, and the next data acquisition is waited.
Preferably, the operation mode of the decoding module includes:
after initial power-on or reset, the decoding module firstly detects whether the data sent by the encoder is at a high level;
when the idle state is detected, the clock ma is transmitted. At the moment, the states of 'confirmation', 'start' and '0' appear in sequence according to the BISS-C frame, if the states are not detected, the state of 'overtime' is directly entered, and the next time of receiving data is waited;
if the detection is passed, receiving a 29-bit position signal, a 2-bit detection signal and a 6-bit check code after the '0' bit;
after receiving, the master device stops sending the clock, waits for the timeout to end, and then enters the next period;
the cyclic redundancy module is responsible for verifying whether the data is correct, wherein the decoding module sends 31 bits of the received 29-bit position signal and 2-bit detection signal to the cyclic redundancy module.
Preferably, the checking method of the cyclic redundancy module comprises the following steps:
preparing a frame of data to be checked, 29-bit position data, 2-bit state bits and 6-bit cyclic redundancy check codes;
replacing the last 6 bits of the cyclic redundancy check code with '000000' to obtain a replaced check code;
dividing the replaced check code by a generator polynomial '1000011';
obtaining 37-bit data;
dividing to obtain a remainder;
and then the cyclic redundancy check code is obtained in a reverse direction.
The FPGA-based biss-c protocol decoding system provided by the invention is used for designing a data acquisition system by utilizing the FPGA. In the bis-c protocol, the data acquisition system can correctly provide position acquisition requests and clock information ma to the encoder and acquire position data slo from the encoder. After frequency division, rs232 is used for transmitting position data, and angle position information is correctly displayed on the upper computer. The maximum data interaction period between the master system and the slave system is 40 mus, the maximum ma clock frequency is 10mhz, and the maximum data delay is 42.5 ns. Experiments prove that the system runs well, and angle data are displayed correctly, so that the method has important significance for improving the test quality of the inertial navigation system.
Drawings
Various other advantages and benefits will become apparent to those of ordinary skill in the art upon reading the following detailed description of the preferred embodiments. The drawings are only for purposes of illustrating the preferred embodiments and are not to be construed as limiting the invention. Also, like reference numerals are used to refer to like parts throughout the drawings.
In the drawings:
FIG. 1 is a schematic diagram of a decoding system for a bios-c protocol based on an FPGA according to an embodiment of the present invention;
FIG. 2 is a schematic diagram of the electrical structure of the food connection of the decoding system based on the FPGA bis-c protocol according to the embodiment of the present invention;
FIG. 3 is a schematic diagram of an embodiment of the present invention, illustrating an operation mode of a clock applied in a decoding system based on a bios-c protocol of an FPGA;
fig. 4 is a flowchart illustrating steps of a method for checking a cyclic redundancy module applied in a decoding system based on a bios-c protocol of an FPGA according to an embodiment of the present invention.
Detailed Description
The data protocol biss-c is the open digital interface protocol introduced by ic-haus in 2002. The bis-c interface protocol provides a two-way fast communication standard for sensors and actuators. It can be implemented in simple hardware. The method is suitable for real-time data acquisition. Compared with other interfaces, the method has the advantages of openness, high speed, networking mode, line delay compensation and the like. The decoding of the bis-c interface protocol may be implemented using hardware decoding, software decoding, or hybrid decoding. Compared with software decoding, hardware decoding can provide higher communication speed and save the cost of external logic circuits.
The bis-c interface protocol is an open full-duplex synchronous serial communication protocol and consists of a point-to-point networking mode and a bus mode. In point-to-point mode, the master interface is connected only to the slave interface. The master interface provides the clock to the slave interface through the rs422 equal differential signal; the slave interface uses the slo signal line to synchronously transmit sensor data from the slave interface back to the master interface. Thus, in a point-to-point mode, the master interface may receive data from the slave interface and communicate with the slave interface in both directions.
Based on the above, the invention provides a BISS-c protocol decoding system based on FPGA for solving the problems in the prior art, which realizes the BISS-c data acquisition system based on the real-time, synchronous and high-speed hardware and software of FPGA, and has important significance for improving the test quality of the inertial navigation system.
To further illustrate the technical means and effects of the present invention for achieving the predetermined objects, the following detailed description of the embodiments, structures, features and effects of the decoding system of the field programmable gate array based biss-c protocol according to the present invention will be made with reference to the accompanying drawings and preferred embodiments. In the following description, different "one embodiment" or "an embodiment" refers to not necessarily the same embodiment. Furthermore, the features, structures, or characteristics of one or more embodiments may be combined in any suitable manner.
The term "and/or" herein is merely an association describing an associated object, meaning that three relationships may exist, e.g., a and/or B, with the specific understanding that: both a and B may be included, a may be present alone, B may be present alone, and any of the three may be provided.
The decoding system of the biss-c protocol based on the FPGA provided by the invention comprises:
a BISS-C encoder for providing a position request and clock information to the absolute encoder; after receiving the clock signal, acquiring data at a position synchronous with the clock signal and providing the data to a data acquisition module;
the data acquisition module is used for receiving slo position data of the rotary table and navigation data of the inertial system;
the coding module is used for coding according to the position data and the navigation data received by the data acquisition module to obtain coded data;
the decoding module is used for decoding the encoded data received from the encoding module to obtain decoded data;
and the upper computer is used for displaying the decoded data.
The FPGA-based biss-c protocol decoding system provided by the invention is used for designing a data acquisition system by utilizing the FPGA. In the bis-c protocol, the data acquisition system can correctly provide position acquisition requests and clock information ma to the encoder and acquire position data slo from the encoder. After frequency division, rs232 is used for transmitting position data, and angle position information is correctly displayed on the upper computer. The maximum data interaction period between the master system and the slave system is 40 mus, the maximum ma clock frequency is 10mhz, and the maximum data delay is 42.5 ns. Experiments prove that the system runs well, and angle data are displayed correctly, so that the method has important significance for improving the test quality of the inertial navigation system.
Wherein, the data acquisition module includes minimum system circuit of FPGA and corresponding peripheral circuit, and it specifically includes:
RS422 interface: the system comprises a transmitter and a receiver, wherein the transmitter is used for transmitting an ma clock and receiving slo position data and navigation data from an inertial navigation system;
an RS232 interface: used for communicating with the rotary table and the upper computer.
The decoding system of the biss-c protocol based on the FPGA further comprises:
and the optical coupler is used for realizing data interaction of the data acquisition system in an isolated manner, wherein the optical coupler is arranged between the interface chip and the FPGA core module.
Wherein each voltage of the FPGA is provided with a corresponding patch capacitor.
The working mode of the clock comprises the following steps:
when the clock does not work, the clock signal and the position signal are set to be high level;
when the clock starts to work, the encoder sets the signal low to indicate "acknowledge" on the second rising edge;
after waiting for n1 clocks, there will be an adjacent high "start" and a low "0" as symbols;
the next 29 bits are position information, followed by "error" and "warning" to check whether the decoding is normal, which are zero, indicating an error in the decoding;
then, six bits of cyclic redundancy check bits are used; when the time is out, the clock is set to be high, and the encoder signal is set to be low;
after waiting n2 clocks, the encoder signal sets it high again and waits for the next set of data to be released;
where the number of clocks for n1 and n2 is not fixed, typically 2-5 clocks.
Wherein the content of the first and second substances,
cyclic redundancy check formula g (x) x6+ x + 1.
Wherein, each acquisition needs 150 clock cycles, if n1 or n2 has more than 50 clocks, the clocks are directly interrupted, the acquisition is wrong, and the next data acquisition is waited.
The working mode of the decoding module comprises the following steps:
after initial power-on or reset, the decoding module firstly detects whether the data sent by the encoder is at a high level;
when the idle state is detected, the clock ma is transmitted. At the moment, the states of 'confirmation', 'start' and '0' appear in sequence according to the BISS-C frame, if the states are not detected, the state of 'overtime' is directly entered, and the next time of receiving data is waited;
if the detection is passed, receiving a 29-bit position signal, a 2-bit detection signal and a 6-bit check code after the '0' bit;
after receiving, the master device stops sending the clock, waits for the timeout to end, and then enters the next period;
the cyclic redundancy module is responsible for verifying whether the data is correct, wherein the decoding module sends 31 bits of the received 29-bit position signal and 2-bit detection signal to the cyclic redundancy module.
The checking method of the cyclic redundancy module comprises the following steps:
preparing a frame of data to be checked, 29-bit position data, 2-bit state bits and 6-bit cyclic redundancy check codes;
replacing the last 6 bits of the cyclic redundancy check code with '000000' to obtain a replaced check code;
the replaced check code is divided by a generator polynomial "1000011";
obtaining 37-bit data;
dividing to obtain a remainder;
and then the cyclic redundancy check code is obtained in a reverse direction.
The experimental verification process is as follows:
in the experiment, the clock signal ma used 1.25mhz, and the encoder responded to the position data on the rising edge of these active clocks. The upper channel 1 is the clock signal ma and the lower channel 2 is the slo data signal. It can be seen that the slo data signal conforms to the biss-c protocol as well as the clock signal. The data segment has 39 valid data, shown as "1010111011001000001110111100101". According to the biss protocol, an error bit "1" indicates that the transmitted location information has been checked by a built-in security check algorithm; a warning bit of "1" indicates that the grating scale and read window are clean, indicating that the encoder is working well at this time. As can be seen from the above, the crc is "000111", and the calculated crc parity bits are the same, indicating that the collected data is valid and correct. The host can also read the data correctly. The method comprises the following steps: 1) subtracting the fixed mechanical zero position on the rotary table from the pulse number of the absolute encoder; 2) divided by 2^29-1 and multiplied by 360. This shows that the whole FPGA-based biss-c protocol interface circuit achieves the purposes of communication and decoding.
The embodiment designs a data acquisition system by using the FPGA. In the bis-c protocol, the data acquisition system can correctly provide position acquisition requests and clock information ma to the encoder and acquire position data slo from the encoder. After frequency division, rs232 is used for transmitting position data, and angle position information is correctly displayed on the upper computer. The maximum data interaction period between the master system and the slave system is 40 mu s, the maximum ma clock frequency is 10mhz, and the maximum data delay is 42.5 ns. Experiments prove that the system runs well, and angle data are displayed correctly.
While preferred embodiments of the present invention have been described, additional variations and modifications in those embodiments may occur to those skilled in the art once they learn of the basic inventive concepts. Therefore, it is intended that the appended claims be interpreted as including preferred embodiments and all such alterations and modifications as fall within the scope of the invention.
It will be apparent to those skilled in the art that various changes and modifications may be made in the present invention without departing from the spirit and scope of the invention. Thus, if such modifications and variations of the present invention fall within the scope of the claims of the present invention and their equivalents, the present invention is also intended to include such modifications and variations.
Claims (9)
1. A FPGA-based bis-c protocol decoding system is characterized by comprising:
a BISS-C encoder for providing a position request and clock information to the absolute encoder; after receiving the clock signal, acquiring data at a position synchronous with the clock signal, and providing the data to the data acquisition module;
the data acquisition module is used for receiving slo position data of the rotary table and navigation data of the inertial system;
the coding module is used for coding according to the position data and the navigation data received by the data acquisition module to obtain coded data;
the decoding module is used for decoding the coded data received from the coding module to obtain decoded data;
and the upper computer is used for displaying the decoded data.
2. The FPGA-based bis-c protocol decoding system of claim 1, wherein said data acquisition module comprises an FPGA minimal system circuit and corresponding peripheral circuits, which specifically comprises:
RS422 interface: the system comprises a transmitter and a receiver, wherein the transmitter is used for transmitting an ma clock and receiving slo position data and navigation data from an inertial navigation system;
an RS232 interface: used for communicating with the rotary table and the upper computer.
3. The FPGA-based bss-c protocol decoding system according to claim 1, further comprising:
and the optical coupler is used for realizing data interaction of the data acquisition system in an isolated manner, wherein the optical coupler is arranged between the interface chip and the FPGA core module.
4. The FPGA-based bis-c protocol decoding system of claim 1, wherein each voltage of said FPGA is provided with a corresponding patch capacitor.
5. The FPGA-based bis-c protocol decoding system of claim 1, wherein said clock operates in a manner comprising:
when the clock does not work, the clock signal and the position signal are set to be high level;
when the clock starts to work, the encoder sets the signal low to indicate "acknowledge" on the second rising edge;
after waiting for n1 clocks, there will be an adjacent high "start" and a low "0" as symbols;
the next 29 bits are position information, followed by "error" and "warning" to check whether the decoding is normal, which are zero, indicating an error in the decoding;
then, six bits of cyclic redundancy check bits are used; when the time is out, the clock is set to be high, and the encoder signal is set to be low;
after waiting n2 clocks, the encoder signal sets it high again and waits for the next set of data to be released;
where the number of clocks for n1 and n2 is not fixed, typically 2-5 clocks.
6. The FPGA-based biss-c protocol decoding system as recited in claim 5,
the cyclic redundancy check formula g (x) ═ x6+ x + 1.
7. The FPGA-based bss-c protocol decoding system of claim 5, wherein each acquisition requires 150 clock cycles, and if n1 or n2 has more than 50 clocks, the clocks are directly interrupted, the acquisition is wrong, and the next data acquisition is waited.
8. The FPGA-based bis-c protocol decoding system of claim 1, wherein said decoding module operates in a manner comprising:
after initial power-on or reset, the decoding module firstly detects whether the data sent by the encoder is at a high level;
when the idle state is detected, the clock ma is transmitted. At the moment, the states of 'confirmation', 'start' and '0' appear in sequence according to the BISS-C frame, if the states are not detected, the state of 'overtime' is directly entered, and the next time of receiving data is waited;
if the detection is passed, receiving a 29-bit position signal, a 2-bit detection signal and a 6-bit check code after the '0' bit;
after receiving, the master device stops sending the clock, waits for the timeout to end, and then enters the next period;
the cyclic redundancy module is responsible for verifying whether the data is correct, wherein the decoding module sends 31 bits of the received 29-bit position signal and 2-bit detection signal to the cyclic redundancy module.
9. The FPGA-based bis-c protocol decoding system of claim 8, wherein said cyclic redundancy module checking method comprises the steps of:
preparing a frame of data to be checked, 29-bit position data, 2-bit state bits and 6-bit cyclic redundancy check codes;
replacing the last 6 bits of the cyclic redundancy check code with '000000' to obtain a replaced check code;
dividing the replaced check code by a generator polynomial '1000011';
obtaining 37-bit data;
dividing to obtain a remainder;
and then the cyclic redundancy check code is obtained in a reverse direction.
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| CN112729311A (en) * | 2020-12-25 | 2021-04-30 | 湖南航天机电设备与特种材料研究所 | Sampling method and sampling system of inertial navigation system |
| CN113535614A (en) * | 2021-09-13 | 2021-10-22 | 之江实验室 | Communication system for decoding BISS-C protocol |
| CN114020660A (en) * | 2021-12-20 | 2022-02-08 | 河北威赛特科技有限公司 | Decoding method and device based on BISS-C protocol and terminal equipment |
| CN115017095A (en) * | 2022-08-05 | 2022-09-06 | 微传智能科技（常州）有限公司 | Current output type AK protocol wheel speed chip communication system and method |
| CN115145857A (en) * | 2022-09-05 | 2022-10-04 | 中国船舶重工集团公司第七0七研究所 | Interface protocol converter conversion method and FPGA system for executing method |
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Application publication date: 20200428 |