CN113498625A - Clock synchronization method and device, chip system, unmanned aerial vehicle and terminal - Google Patents

Clock synchronization method and device, chip system, unmanned aerial vehicle and terminal Download PDF

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CN113498625A
CN113498625A CN202080015468.1A CN202080015468A CN113498625A CN 113498625 A CN113498625 A CN 113498625A CN 202080015468 A CN202080015468 A CN 202080015468A CN 113498625 A CN113498625 A CN 113498625A
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subsystem
time
data set
utc
index
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王钧玉
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SZ DJI Technology Co Ltd
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SZ DJI Technology Co Ltd
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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04W—WIRELESS COMMUNICATION NETWORKS
    • H04W56/00—Synchronisation arrangements
    • H04W56/001—Synchronization between nodes
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04W—WIRELESS COMMUNICATION NETWORKS
    • H04W56/00—Synchronisation arrangements
    • H04W56/003—Arrangements to increase tolerance to errors in transmission or reception timing
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04W—WIRELESS COMMUNICATION NETWORKS
    • H04W84/00—Network topologies
    • H04W84/02—Hierarchically pre-organised networks, e.g. paging networks, cellular networks, WLAN [Wireless Local Area Network] or WLL [Wireless Local Loop]
    • H04W84/04—Large scale networks; Deep hierarchical networks
    • H04W84/06—Airborne or Satellite Networks

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  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
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  • Electric Clocks (AREA)

Abstract

The utility model provides a clock synchronization method and device, a chip system, an unmanned aerial vehicle and a terminal, wherein a first subsystem in the chip system receives UTC time sent by a second subsystem in the chip system and local time of the second subsystem; clock synchronizing the local time of the first subsystem and the UTC time based on a time difference between the local time of the first subsystem and the local time of the second subsystem; and the time delay of the second subsystem for acquiring the UTC time is less than the time delay of the first subsystem for acquiring the UTC time.

Description

Clock synchronization method and device, chip system, unmanned aerial vehicle and terminal
Technical Field
The present disclosure relates to the technical field of chip systems, and in particular, to a clock synchronization method and apparatus, a chip system, an unmanned aerial vehicle, and a terminal.
Background
When a subsystem in a chip system works, Coordinated Universal Time (UTC) needs to be acquired. When obtaining the UTC time, the subsystem obtains a Pulse Per Second (PPS) signal from the satellite receiving system, and obtains the UTC time corresponding to the PPS signal from the interrupt program. However, some subsystems have a large interrupt latency, resulting in less accuracy in obtaining UTC time.
Disclosure of Invention
The disclosure provides a clock synchronization method and device, a chip system, an unmanned aerial vehicle and a terminal, which can improve the accuracy of UTC time acquired by the subsystem in the chip system.
In a first aspect, an embodiment of the present disclosure provides a clock synchronization method applied to a first subsystem in a chip system, where the method includes: receiving UTC time sent by a second subsystem in the chip system and local time of the second subsystem; clock synchronizing the local time of the first subsystem and the UTC time based on a time difference between the local time of the first subsystem and the local time of the second subsystem; and the time delay of the second subsystem for acquiring the UTC time is less than the time delay of the first subsystem for acquiring the UTC time.
In a second aspect, an embodiment of the present disclosure provides a clock synchronization method applied to a second subsystem in a chip system, where the method includes: receiving UTC time transmitted by a satellite receiving system and the local time of the second subsystem; sending the UTC time to a first subsystem in the chip system, so that the first subsystem performs clock synchronization on the local time of the first subsystem and the UTC time based on a time difference between the local time of the first subsystem and the local time of the second subsystem; and the time delay of the second subsystem for acquiring the UTC time is less than the time delay of the first subsystem for acquiring the UTC time.
In a third aspect, an embodiment of the present disclosure provides a clock synchronization apparatus, including a first processor and a first communication interface, where the first communication interface is configured to receive a UTC time sent by a second subsystem in a chip system and a local time of the second subsystem; the first processor is configured to clock synchronize the local time of the first subsystem and the UTC time based on a time difference between the local time of the first subsystem and the local time of the second subsystem; and the time delay of the second subsystem for acquiring the UTC time is less than the time delay of the first subsystem for acquiring the UTC time.
In a fourth aspect, an embodiment of the present disclosure provides a clock synchronization apparatus, including a second processor and a second communication interface, where the second communication interface is configured to receive UTC time sent by a satellite receiving system; the second processor is used for sending the UTC time and the local time of the second subsystem to a first subsystem in the chip system, so that the first subsystem performs clock synchronization on the local time of the first subsystem and the UTC time based on a time difference between the local time of the first subsystem and the local time of the second subsystem; and the time delay of the second subsystem for acquiring the UTC time is less than the time delay of the first subsystem for acquiring the UTC time.
In a fifth aspect, an embodiment of the present disclosure provides a chip system, including: a first subsystem and a second subsystem; the second subsystem is used for receiving the UTC time sent by the satellite receiving system and sending the UTC time and the local time of the second subsystem to the first subsystem in the chip system; the first subsystem is used for carrying out clock synchronization on the local time of the first subsystem and the UTC time based on the time difference between the local time of the first subsystem and the local time of the second subsystem; and the time delay of the second subsystem for acquiring the UTC time is less than the time delay of the first subsystem for acquiring the UTC time.
In a sixth aspect, an embodiment of the present disclosure provides an unmanned aerial vehicle, including: the chip system according to any one of the embodiments of the present disclosure; and the satellite receiving system is used for sending the UTC time to a second subsystem in the chip system.
In a seventh aspect, an embodiment of the present disclosure provides a terminal, including: the chip system according to any one of the embodiments of the present disclosure; and the communication system is used for controlling the unmanned aerial vehicle to fly based on the synchronized local time of the first subsystem.
In an eighth aspect, an embodiment of the present disclosure provides a computer-readable storage medium, which includes instructions that, when executed on a computer, cause the computer to perform the clock synchronization method according to the first aspect.
In the embodiment of the disclosure, the UTC time is acquired by the second subsystem, and because the time delay for acquiring the UTC time by the second subsystem is small, the accuracy of the UTC time acquired by the second subsystem is high; and then, clock synchronization is carried out on the local time of the first subsystem and the UTC time based on the time difference between the local times of the first subsystem and the second subsystem, so that the first subsystem is not required to acquire the UTC time from the interrupt program, and the accuracy of acquiring the UTC time by the first subsystem is improved.
It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the disclosure.
Drawings
In order to more clearly illustrate the technical solutions in the embodiments of the present disclosure, the drawings needed to be used in the description of the embodiments are briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present disclosure, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without inventive labor.
Fig. 1 is a schematic diagram of a conventional clock synchronization method.
Fig. 2 is a flow chart of a clock synchronization method of an embodiment of the present disclosure.
Fig. 3 is a schematic diagram comparing the clock synchronization method of the embodiment of the present disclosure with the conventional clock synchronization method.
Fig. 4A and 4B are schematic diagrams of a caching process of a data set according to an embodiment of the disclosure.
Fig. 5 is a flow chart of a clock synchronization method of further embodiments of the present disclosure.
Fig. 6 is a timing diagram of a clock synchronization process of an embodiment of the disclosure.
Fig. 7 is a schematic diagram of a clock synchronization apparatus of an embodiment of the present disclosure.
Fig. 8 is a block diagram of a chip system of an embodiment of the disclosure.
Fig. 9 is a schematic diagram of a drone of an embodiment of the present disclosure.
Fig. 10 is a schematic diagram of a terminal of an embodiment of the disclosure.
Detailed Description
Reference will now be made in detail to the exemplary embodiments, examples of which are illustrated in the accompanying drawings. When the following description refers to the accompanying drawings, like numbers in different drawings represent the same or similar elements unless otherwise indicated. The implementations described in the exemplary embodiments below are not intended to represent all implementations consistent with the present disclosure. Rather, they are merely examples of apparatus and methods consistent with certain aspects of the present disclosure, as detailed in the appended claims.
The terminology used in the present disclosure is for the purpose of describing particular embodiments only and is not intended to be limiting of the disclosure. As used in this disclosure and the appended claims, the singular forms "a," "an," and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It should also be understood that the term "and/or" as used herein refers to and encompasses any and all possible combinations of one or more of the associated listed items.
It is to be understood that although the terms first, second, third, etc. may be used herein to describe various information, such information should not be limited to these terms. These terms are only used to distinguish one type of information from another. For example, first information may also be referred to as second information, and similarly, second information may also be referred to as first information, without departing from the scope of the present disclosure. The word "if" as used herein may be interpreted as "at … …" or "when … …" or "in response to a determination", depending on the context.
Global Navigation Satellite Systems (GNSS) have been widely used globally, and can provide users with all-weather real-time position, speed, and time information. When the GNSS is used for time-feeding, a pulse signal PPS signal is generated outwards, the period is 1 second, and meanwhile UTC time at the rising edge time of the PPS is sent out through a communication link.
When a subsystem in a chip system works, the local time of the subsystem needs to be clock-synchronized (also called clock alignment) with the UTC time, that is, the local time of the subsystem corresponds to the UTC time. The chip system can receive the PPS signal sent by the satellite receiving system, and then read the UTC time corresponding to the PPS signal from the interrupt program. As shown in fig. 1, assuming that the time delay from the time when the satellite receiving system transmits the UTC time to the time when the subsystem receives the UTC time is t1, and the time delay from the time when the subsystem reads the UTC time from the interrupt routine is t2, the time delay for reading the UTC time in the whole process is t1+ t 2. The delay for some subsystems in the system-on-chip to acquire UTC time is large (e.g., the communication link delay is large, or the delay for reading the interrupt handling response of the UTC from the interrupt routine is large), resulting in a low accuracy for acquiring UTC time and thus a low accuracy for clock synchronization.
Based on this, the embodiment of the present disclosure provides a clock synchronization method, which is applied to a first subsystem in a chip system, as shown in fig. 2, the method includes:
201: receiving UTC time sent by a second subsystem in the chip system and local time of the second subsystem;
202: clock synchronizing the local time of the first subsystem and the UTC time based on a time difference between the local time of the first subsystem and the local time of the second subsystem; and the time delay of the second subsystem for acquiring the UTC time is less than the time delay of the first subsystem for acquiring the UTC time.
The first subsystem and the second subsystem in the embodiment of the present disclosure may be any subsystem, for example, a Linux System, a Real Time Operating System (RTOS), a Disk Operating System (DOS), a Windows System, a hong meng System, or another Operating System, which is not limited in this disclosure, and only needs that the Time delay of the second subsystem to acquire the UTC Time is less than the Time delay of the first subsystem to acquire the UTC Time. The first subsystem and the second subsystem can be connected in a hardware mode. For example, the first subsystem and the second subsystem may be connected by wires or other hardware circuits. Due to the adoption of a hardware connection mode, the communication time delay between the first subsystem and the second subsystem can be ignored, and the accuracy of obtaining the UTC time by the first subsystem is further improved.
The clock synchronization in the embodiment of the present disclosure may be performed by performing clock synchronization between the UTC time of the satellite receiving system transmitting part or all of the PPS signals and the local time of the first subsystem. The satellite receiving system and the second subsystem can also be connected in a hardware mode. The communication link between the satellite receiving system and the second subsystem may be a Serial port, a Controller Area Network (CAN) Bus, a 1553B Bus, a Universal Serial Bus (USB), or other communication links.
In some embodiments, the first subsystem is a Linux system and the second subsystem is an RTOS system. A Micro Control Unit (MCU) or a Central Processing Unit (CPU) in the RTOS system may be connected to the satellite receiving system through a communication link, and a PPS signal sent by the satellite receiving system is introduced to an external interrupt of the CPU or the MCU, so that the CPU or the MCU may receive the PPS signal and UTC at the time of receiving the PPS signal.
According to the embodiment of the invention, a clock synchronization system is formed by using common modules such as a satellite receiving system and a CPU/MCU (central processing unit/micro control unit), the implementation is simple, the cost is low, the advantage that the interruption processing time of an RTOS (real time operating system) is short can be fully utilized, the clock difference of the RTOS is given to a Linux system in a sharing mode, so that the accuracy of the UTC time acquired by the Linux system is improved, the error between the local time on a subsystem and the UTC time is within 2us, and the requirements of fields such as surveying and mapping on high-precision time can be met. Fig. 3 is a schematic diagram illustrating a comparison between the clock synchronization method according to the embodiment of the present disclosure and the conventional clock synchronization method. Assuming that the transmission delay between the satellite receiving system and the first subsystem and the transmission delay between the satellite receiving system and the second subsystem are both t1, the interrupt response time t3 for the second subsystem to obtain the UTC time from the interrupt program is much shorter than the interrupt response time t2 for the first subsystem to obtain the UTC time from the interrupt program, so that the delay for the first subsystem to obtain the UTC time can be shortened to t 4-t 2-t 3.
In some embodiments, the local time of the first subsystem may be clock synchronized with a time corresponding to a sum of the UTC time and the time difference. Assuming that the UTC time received by the first subsystem from the second subsystem is UTC _ time, and the time difference is delta, the UTC time corresponding to the local time of the first subsystem is UTC _ time _ now-UTC _ time + delta.
The local time of a subsystem may be determined based on the count value of a counter in the subsystem. Since the manner of determining the local time of the first subsystem is the same as the manner of determining the local time of the second subsystem, the manner of determining the local time will be described herein by taking the first subsystem as an example only.
A first count value of a counter of the first subsystem may be obtained, and a local time of the first subsystem may be determined based on the first count value. The counter of the first subsystem may count at regular time intervals, for example, once every time a transition edge (rising or falling) of the target signal is detected. The local time may be determined based on the first count value and the counted time interval. For example, assume that the local time when the first count value is k is tkIf the first count value is k + p, the local time is tk+ p t0, where t0 denotes the time interval of counting, k and p both being positive integers.
Similarly, a second count value of the counter of the second subsystem may be obtained, and the local time of the second subsystem may be determined based on the second count value. For a specific process, reference may be made to a manner of determining the local time of the first subsystem, which is not described herein again.
Further, there may be a difference between the clock frequency generated by the crystal oscillator used to generate the local clock of the subsystem and the standard clock frequency that is expected to be generated, e.g., the clock frequency that the second subsystem is expected to generate may be 60.00Hz, but the actual generated clock frequency is 59.99 Hz. This situation may further lead to errors in clock synchronization. In order to solve the above problem, when determining the time difference, a frequency difference between the clock frequency of the first subsystem and the clock frequency of the second subsystem may be obtained, and the time difference may be corrected based on the frequency difference.
In some embodiments, to facilitate data interaction, a first subsystem may receive a data set from a second subsystem, which may include the UTC time and a local time of the second subsystem. Further, the data set may further include index and/or check information of the UTC time. The data set may be denoted as { index, counter, utc _ time, crc } in some embodiments, and the order of the data items in the data set may also be in other embodiments, which is not limited by this disclosure. The index indicates an index, and since the satellite receiving system transmits one PPS signal to the second subsystem every second, the number of PPS signals received by the second subsystem may be used as the index. For example, when the second subsystem receives the mth PPS signal, the index of the corresponding data set is denoted as m. counter represents a second count value of the second subsystem, UTC _ time represents UTC time of the second subsystem, and CRC represents a Cyclic Redundancy Check (CRC). Of course, other types of check information besides the CRC check code may be used here, and will not be described here again.
The first subsystem, upon receiving the data set, may cache the data set based on an index in the data set. In some embodiments, the received data sets may be sequentially cached at addresses in the cache. Before the cache is not full, caching a data set under a free address in the cache every time the data set is received; in the case of a full cache, each time a data set is received, the data set may be cached at the target address for caching the data set that includes the smallest index. For example, in the case where the cache is full, assuming that the data set at address 1 in the cache includes an index of 1, the data set at address 2 includes an index of 2, and so on, the data set at address 1 includes the smallest index, so that address 1 is determined as the target address, and the received data set is cached at address 1 to cover the original data set at address 1.
When clock synchronization is required, the first subsystem may read the data set from the cache and read the required information therefrom. In particular, the data set including the largest index may be read from the cache. For example, assuming that the data set at address 1 in the cache includes an index of 1, the data set at address 2 includes an index of 2, and so on, the data set at address 5 in the cache includes an index of 5, and the index is the largest index, the data set may be read from address 5.
For convenience of operation, the start index start _ index and the end index end _ index of each data set in the buffer may be recorded. Where start _ index is used to record the index value of the smallest index in the data set, end _ index is used to record the index value of the largest index in the data set, and start _ index and end _ index may be 32-bit unsigned integers. The start _ index and end _ index may be buffered and read directly from the buffer when needed. The start _ index and end _ index may be updated every time a data set is cached. For example, in the case that the cache is not full, every time one data set is cached, the end _ index may be updated, that is, the value of the end _ index is added by 1. In case the cache is full, both start _ index and end _ index can be updated for each data set cached. Assuming that the current start _ index and end _ index are s and e, respectively, in case of receiving the next data set, the data set may be overwritten to the address where the data set including the index s is located, the end _ index may be updated to e +1, and the start _ index may be updated to s + 1. Wherein s and e are both positive integers.
As shown in fig. 4A and 4B, it is assumed that 3600 data sets can be cached at most in the cache. And sequentially caching the data sets under the addresses in the cache according to the size of the index under the condition that the cache is not full. When the cache is just full, as shown in fig. 4A, the start _ index and end _ index at this time are 0 and 3600, respectively. Assuming that a data set is received again, as shown in fig. 4B, the address where the data set with index 0 is located is covered, so that start _ index and end _ index are 1 and 3601, respectively.
Further, before clock synchronization, integrity check may also be performed on the data set based on the check information. Optionally, when the data set includes one item of data, the first check information corresponding to the item of data may be recorded as 1; when a certain item of data in the data set is missing, the first check information corresponding to the item of data may be recorded as 0. For example, for a data set { index, counter, utc _ time, crc }, in the case that an index is included in the data set, the first check information corresponding to an index data item is marked as 1, otherwise, it is marked as 0. So that the first check information of each data item can be and-operated to obtain the check information crc. If crc is 1, it means the data set is complete, otherwise it means the data set is incomplete. In the event that the data set is incomplete, the data set may be discarded.
As shown in fig. 5, an embodiment of the present disclosure further provides a clock synchronization method applied to a second subsystem in a chip system, where the method includes:
501: receiving UTC time transmitted by a satellite receiving system;
502: sending the UTC time and the local time of the second subsystem to a first subsystem in the chip system, so that the first subsystem performs clock synchronization on the local time of the first subsystem and the UTC time based on a time difference between the local time of the first subsystem and the local time of the second subsystem; and the time delay of the second subsystem for acquiring the UTC time is less than the time delay of the first subsystem for acquiring the UTC time.
In some embodiments, the second subsystem may further send the clock frequency of the second subsystem to the first subsystem, so that the first subsystem corrects the time difference based on a frequency difference between the clock frequency of the first subsystem and the clock frequency of the second subsystem.
In some embodiments, the second subsystem may transmit a data set including the UTC time and a local time of the second subsystem to the first subsystem.
In some embodiments, the data set further includes an index of the UTC time, and the index is used for the first subsystem to cache the data set and read a corresponding data set from the cache.
In some embodiments, the data set further includes verification information for the first subsystem to verify integrity of the data set.
In some embodiments, the first subsystem and the second subsystem are connected by hardware. In some embodiments, the second subsystem is connected to the satellite receiving system by hardware.
In some embodiments, the first subsystem is a Linux system and the second subsystem is an RTOS system.
For details of the technology of this embodiment, reference is made to the foregoing embodiment of the clock synchronization method applied to the first subsystem, and details are not described herein again.
The following describes the technical solution of the present disclosure by taking a specific embodiment as an example and referring to fig. 6. The Chip System of the embodiments of the present disclosure may be a multi-core Chip System, each core in the multi-core Chip System may be a subsystem, and the Chip System may be a System on Chip (SoC). The scheme of the embodiment of the present disclosure is described by taking a two-core chip system as an example, where the first subsystem is an a-core and the second subsystem is a B-core. The embodiment of the disclosure comprises a satellite receiving system and a multi-core chip system, wherein the satellite receiving system is connected with the SoC through a communication link, and meanwhile, the PPS of the satellite receiving system introduces the external interrupt of the SoC. The SoC responds to the satellite reception system outputting a pulse of seconds in the form of an interrupt, while receiving UTC time at the time of the rising edge of the PPS signal over the communication link. The B core processes the PPS signal while both the a and B cores are receiving UTC time.
At 601, the satellite receiving system transmits the PPS signal and the UTC time to the B-core. The UTC time and PPS signals may be transmitted synchronously over different links.
In 602 and 603, the B-core may read the UTC time at which the PPS signal is received from the interrupt program after receiving the PPS signal, and may also read a second count value counter of the counter from the interrupt program. Then, the index of the PPS signal (i.e., the number of currently received PPS signals), the second count value, the UTC time, and the check information crc are packed to generate a data set, and the data set is transmitted to the a core.
In 604 through 606, the a-core may first cache the data set. When the application on the a-core needs to obtain the current time, the a-core may read the data set from the cache, and read the first count value of the counter of the a-core, so as to calculate a time interval delta between the local time of the a-core and the local time of the B-core according to the first count value and the second count value, and further calculate the current UTC time, that is, UTC _ time _ now is UTC _ time + delta.
Through practical tests, the clock synchronization scheme described by the invention can ensure that the error between the local time and the UTC time is within +/-2 microseconds, and achieves a higher precision level. The clock synchronization scheme disclosed by the invention avoids the defect of long interrupt response time of subsystems such as Linux and the like, fully utilizes the advantage of fast interrupt response of systems such as RTOS and the like, and achieves the purposes of local timing and accumulated error elimination, thereby improving the clock synchronization precision.
The embodiment of the present disclosure further provides a clock synchronization apparatus, including a first processor and a first communication interface, where the first communication interface is configured to receive a UTC time sent by a second subsystem in a chip system and a local time of the second subsystem; the first processor is configured to clock synchronize the local time of the first subsystem and the UTC time based on a time difference between the local time of the first subsystem and the local time of the second subsystem; and the time delay of the second subsystem for acquiring the UTC time is less than the time delay of the first subsystem for acquiring the UTC time.
In some embodiments, the first processor is configured to: and performing clock synchronization on the local time of the first subsystem and the time corresponding to the sum of the UTC time and the time difference.
In some embodiments, the first processor is further configured to: acquiring a frequency difference between the clock frequency of the first subsystem and the clock frequency of the second subsystem; and correcting the time difference based on the frequency difference.
In some embodiments, the first processor is further configured to: acquiring a first count value of a counter of the first subsystem; determining a local time of the first subsystem based on the first count value.
In some embodiments, the first communication interface is to: and receiving a data set sent by the second subsystem, wherein the data set comprises the UTC time and the local time of the second subsystem.
In some embodiments, the data set further comprises an index of the UTC time, the first processor is further configured to: caching the data set based on the index; and reading the corresponding data set from the cache based on the index. It should be noted that the cached data set is not necessarily read immediately, and the first processor may read the data set from the cache when needed, for example, when an application in the first subsystem needs to acquire time.
In some embodiments, the first processor is configured to: and reading the data set comprising the maximum index from the cache.
In some embodiments, the first processor is configured to: and in the case that the cache space is full, caching the data set under a target address, wherein the target address is used for caching the data set comprising the minimum index.
In some embodiments, the data set further includes verification information; the first processor is further configured to: and checking the integrity of the data set based on the checking information.
In some embodiments, the first subsystem and the second subsystem are connected by hardware.
In some embodiments, the first subsystem is a Linux system and the second subsystem is an RTOS system.
The embodiment of the present disclosure further provides a clock synchronization apparatus, which includes a second processor and a second communication interface, where the second communication interface is configured to receive UTC time sent by a satellite receiving system; the second processor is used for sending the UTC time and the local time of the second subsystem to a first subsystem in the chip system, so that the first subsystem performs clock synchronization on the local time of the first subsystem and the UTC time based on a time difference between the local time of the first subsystem and the local time of the second subsystem; and the time delay of the second subsystem for acquiring the UTC time is less than the time delay of the first subsystem for acquiring the UTC time.
In some embodiments, the second processor is further configured to: and sending the clock frequency of the second subsystem to the first subsystem, so that the first subsystem corrects the time difference based on the frequency difference between the clock frequency of the first subsystem and the clock frequency of the second subsystem.
In some embodiments, the second processor is configured to: transmitting a data set including the UTC time and a local time of the second subsystem to the first subsystem.
In some embodiments, the data set further includes an index of the UTC time, and the index is used for the first subsystem to cache the data set and read a corresponding data set from the cache.
In some embodiments, the data set further includes verification information for the first subsystem to verify integrity of the data set.
In some embodiments, the first subsystem and the second subsystem are connected by hardware; and/or the second subsystem is connected with the satellite receiving system in a hardware mode.
In some embodiments, the first subsystem is a Linux system and the second subsystem is an RTOS system.
In some embodiments, the second processor is further configured to: acquiring a second count value of a counter of the second subsystem; determining a local time of the second subsystem based on the second count value.
Fig. 7 is a schematic diagram illustrating a hardware structure of a more specific clock synchronization apparatus provided in an embodiment of the present specification, where the apparatus may include: a processor 701, a memory 702, an input/output interface 703, a communication interface 704, and a bus 705. Wherein the processor 701, the memory 702, the input/output interface 703 and the communication interface 704 are communicatively connected to each other within the device via a bus 705. When the clock synchronization apparatus is used to execute the method applied to the first subsystem, the processor 701 is a first processor, and the communication interface 704 is a first communication interface. When the clock synchronization apparatus is used to execute the method applied to the second subsystem, the processor 701 is a second processor, and the communication interface 704 is a second communication interface.
The processor 701 may be implemented by a general-purpose CPU (Central Processing Unit), a microprocessor, an Application Specific Integrated Circuit (ASIC), or one or more Integrated circuits, and is configured to execute related programs to implement the technical solutions provided in the embodiments of the present specification.
The Memory 702 may be implemented in the form of a ROM (Read Only Memory), a RAM (Random Access Memory), a static storage device, a dynamic storage device, or the like. The memory 702 may store an operating system and other application programs, and when the technical solution provided by the embodiments of the present specification is implemented by software or firmware, the relevant program codes are stored in the memory 702 and called to be executed by the processor 701.
The input/output interface 703 is used for connecting an input/output module to realize information input and output. The i/o module may be configured as a component in a device (not shown) or may be external to the device to provide a corresponding function. The input devices may include a keyboard, a mouse, a touch screen, a microphone, various sensors, etc., and the output devices may include a display, a speaker, a vibrator, an indicator light, etc.
The communication interface 704 is used for connecting a communication module (not shown in the figure) to realize communication interaction between the device and other devices. The communication module can realize communication in a wired mode (such as USB, network cable and the like) and also can realize communication in a wireless mode (such as mobile network, WIFI, Bluetooth and the like).
Bus 705 includes a pathway for communicating information between various components of the device, such as processor 701, memory 702, input/output interface 703, and communication interface 704.
It should be noted that although the above-mentioned device only shows the processor 701, the memory 702, the input/output interface 703, the communication interface 704 and the bus 705, in a specific implementation, the device may also include other components necessary for normal operation. In addition, those skilled in the art will appreciate that the above-described apparatus may also include only those components necessary to implement the embodiments of the present description, and not necessarily all of the components shown in the figures.
As shown in fig. 8, the embodiment of the present disclosure further provides a chip system 800, which includes a first subsystem 801 and a second subsystem 802; the second subsystem 802 is configured to receive the UTC time sent by the satellite receiving system, and send the UTC time and the local time of the second subsystem 802 to the first subsystem 801 in the chip system; the first subsystem 801 is configured to clock-synchronize the local time of the first subsystem 801 and the UTC time based on a time difference between the local time of the first subsystem 801 and the local time of the second subsystem 802; wherein, the time delay of the second subsystem 802 for acquiring the UTC time is less than the time delay of the first subsystem 801 for acquiring the UTC time.
In some embodiments, the first subsystem 801 is configured to: and performing clock synchronization on the local time of the first subsystem and the time corresponding to the sum of the UTC time and the time difference.
In some embodiments, the first subsystem 801 is further configured to: acquiring a frequency difference between the clock frequency of the first subsystem 801 and the clock frequency of the second subsystem 802; and correcting the time difference based on the frequency difference.
In some embodiments, the first subsystem 801 is further configured to: acquiring a first count value of a counter of the first subsystem 801; the local time of the first subsystem 801 is determined based on the first count value.
In some embodiments, the second subsystem 802 is further configured to: acquiring a second count value of the counter of the second subsystem 802; a local time of the second subsystem 802 is determined based on the second count value.
In some embodiments, the second subsystem 802 is configured to: a data set comprising the UTC time and the local time of the second subsystem 802 is sent to the first subsystem 801.
In some embodiments, the data set further includes an index of the UTC time, and the first subsystem 801 is further configured to: caching the data set based on the index; and reading the corresponding data set from the cache based on the index.
In some embodiments, the first subsystem 801 is configured to: and reading the data set comprising the maximum index from the cache.
In some embodiments, the first subsystem 801 is configured to: and in the case that the cache space is full, caching the data set under a target address, wherein the target address is used for caching the data set comprising the minimum index.
In some embodiments, the data set further includes verification information; the first subsystem 801 is configured to: and checking the integrity of the data set based on the checking information.
In some embodiments, the first subsystem 801 is connected to the second subsystem 802 by hardware; and/or the second subsystem 802 is connected to the satellite receiving system by hardware.
In some embodiments, the first subsystem 801 is a Linux system and the second subsystem 802 is an RTOS system.
In this embodiment, the specific embodiment of the first subsystem 801 is described in detail in the above embodiment of the method applied to the first subsystem, and the specific embodiment of the second subsystem 802 is described in detail in the above embodiment of the method applied to the second subsystem, which is not described herein again.
As shown in fig. 9, an unmanned aerial vehicle 900 according to an embodiment of the present disclosure further includes the chip system 800 according to any of the foregoing embodiments, and a satellite receiving system 901, configured to send the UTC time to a second subsystem in the chip system.
Further, the unmanned aerial vehicle 900 further comprises a body 902 and a power system 903, the chip system 800, the satellite receiving system 901 and the power system 903 are all arranged in the body 902, and the power system 903 is used for providing power for the unmanned aerial vehicle. The chip system 800 may be included in a flight control system of the drone 900 for controlling the drone 900 to fly.
As shown in fig. 10, an embodiment of the present disclosure further provides a terminal 1000, which includes the chip system 800 described in any of the above embodiments, and a communication system 1001, and is configured to control a state of the drone based on the synchronized local time of the first subsystem 801. The terminal can be a mobile phone, a tablet personal computer and other equipment, and can also be an unmanned aerial vehicle dedicated remote controller and other equipment. The chip system 800 can be installed in the terminal 1000, and the terminal 1000 can send a control instruction to the drone through the communication system 1001 based on a clock synchronization result of the chip system 800 to control the drone to fly (e.g., take off, return, or perform a specific task).
The embodiments of the present disclosure also provide a computer-readable storage medium, which includes instructions that, when executed on a computer, cause the computer to perform the method of any of the preceding embodiments.
Computer-readable media, including both non-transitory and non-transitory, removable and non-removable media, may implement information storage by any method or technology. The information may be computer readable instructions, data structures, modules of a program, or other data. Examples of computer storage media include, but are not limited to, phase change memory (PRAM), Static Random Access Memory (SRAM), Dynamic Random Access Memory (DRAM), other types of Random Access Memory (RAM), Read Only Memory (ROM), Electrically Erasable Programmable Read Only Memory (EEPROM), flash memory or other memory technology, compact disc read only memory (CD-ROM), Digital Versatile Discs (DVD) or other optical storage, magnetic cassettes, magnetic tape magnetic disk storage or other magnetic storage devices, or any other non-transmission medium that can be used to store information that can be accessed by a computing device. As defined herein, a computer readable medium does not include a transitory computer readable medium such as a modulated data signal and a carrier wave.
From the above description of the embodiments, it is clear to those skilled in the art that the embodiments of the present disclosure can be implemented by software plus necessary general hardware platform. Based on such understanding, the technical solutions of the embodiments of the present specification may be essentially or partially implemented in the form of a software product, which may be stored in a storage medium, such as a ROM/RAM, a magnetic disk, an optical disk, etc., and includes several instructions for enabling a computer device (which may be a personal computer, a server, or a network device, etc.) to execute the methods described in the embodiments or some parts of the embodiments of the present specification.
The systems, devices, modules or units illustrated in the above embodiments may be implemented by a computer chip or an entity, or by a product with certain functions. A typical implementation device is a computer, which may take the form of a personal computer, laptop computer, cellular telephone, camera phone, smart phone, personal digital assistant, media player, navigation device, email messaging device, game console, tablet computer, wearable device, or a combination of any of these devices.
Various technical features in the above embodiments may be arbitrarily combined as long as there is no conflict or contradiction in the combination between the features, but the combination is limited by the space and is not described one by one, and therefore, any combination of various technical features in the above embodiments also belongs to the scope of the present disclosure.
Other embodiments of the present disclosure will be apparent to those skilled in the art from consideration of the specification and practice of the disclosure disclosed herein. This disclosure is intended to cover any variations, uses, or adaptations of the disclosure following, in general, the principles of the disclosure and including such departures from the present disclosure as come within known or customary practice within the art to which the disclosure pertains. It is intended that the specification and examples be considered as exemplary only, with a true scope and spirit of the disclosure being indicated by the following claims.
It will be understood that the present disclosure is not limited to the precise arrangements described above and shown in the drawings and that various modifications and changes may be made without departing from the scope thereof. The scope of the present disclosure is limited only by the appended claims.
The above description is only exemplary of the present disclosure and should not be taken as limiting the disclosure, as any modification, equivalent replacement, or improvement made within the spirit and principle of the present disclosure should be included in the scope of the present disclosure.

Claims (53)

1. A clock synchronization method applied to a first subsystem in a chip system, the method comprising:
receiving UTC time sent by a second subsystem in the chip system and local time of the second subsystem;
clock synchronizing the local time of the first subsystem and the UTC time based on a time difference between the local time of the first subsystem and the local time of the second subsystem;
and the time delay of the second subsystem for acquiring the UTC time is less than the time delay of the first subsystem for acquiring the UTC time.
2. The method of claim 1, wherein clock synchronizing the local time of the first subsystem and the UTC time based on a time difference between the local time of the first subsystem and the local time of the second subsystem comprises:
and performing clock synchronization on the local time of the first subsystem and the time corresponding to the sum of the UTC time and the time difference.
3. The method of claim 1, further comprising:
acquiring a frequency difference between the clock frequency of the first subsystem and the clock frequency of the second subsystem;
and correcting the time difference based on the frequency difference.
4. The method of claim 1, further comprising:
acquiring a first count value of a counter of the first subsystem;
determining a local time of the first subsystem based on the first count value.
5. The method of claim 1, wherein the receiving the UTC time transmitted by the second subsystem in the system-on-chip and the local time of the second subsystem comprises:
and receiving a data set sent by the second subsystem, wherein the data set comprises the UTC time and the local time of the second subsystem.
6. The method of claim 5, wherein the dataset further comprises an index of the UTC time, the method further comprising:
caching the data set based on the index; and
based on the index, a corresponding data set is read from the cache.
7. The method of claim 6, wherein reading the corresponding set of data from the cache based on the index comprises:
and reading the data set comprising the maximum index from the cache.
8. The method of claim 6, wherein caching the data set based on the index comprises:
and in the case that the cache space is full, caching the data set under a target address, wherein the target address is used for caching the data set comprising the minimum index.
9. The method of claim 6, wherein the data set further comprises verification information; the method further comprises the following steps:
and checking the integrity of the data set based on the checking information.
10. The method of claim 1, wherein the first subsystem is connected to the second subsystem via hardware.
11. The method of claim 1, wherein the first subsystem is a Linux system and the second subsystem is an RTOS system.
12. A clock synchronization method applied to a second subsystem in a chip system, the method comprising:
receiving UTC time transmitted by a satellite receiving system;
sending the UTC time and the local time of the second subsystem to a first subsystem in the chip system, so that the first subsystem performs clock synchronization on the local time of the first subsystem and the UTC time based on a time difference between the local time of the first subsystem and the local time of the second subsystem;
and the time delay of the second subsystem for acquiring the UTC time is less than the time delay of the first subsystem for acquiring the UTC time.
13. The method of claim 12, further comprising:
and sending the clock frequency of the second subsystem to the first subsystem, so that the first subsystem corrects the time difference based on the frequency difference between the clock frequency of the first subsystem and the clock frequency of the second subsystem.
14. The method of claim 12, wherein sending the UTC time and the local time of the second subsystem to a first subsystem in the system-on-chip comprises:
transmitting a data set including the UTC time and a local time of the second subsystem to the first subsystem.
15. The method of claim 14, wherein the data set further comprises an index of the UTC time, and wherein the index is used for the first subsystem to cache the data set and to read the corresponding data set from the cache.
16. The method of claim 14, wherein the data set further comprises verification information, and the verification information is used for verifying the integrity of the data set by the first subsystem.
17. The method of claim 12, wherein the first subsystem is connected to the second subsystem by hardware; and/or
The second subsystem is connected with the satellite receiving system in a hardware mode.
18. The method of claim 12, wherein the first subsystem is a Linux system and the second subsystem is an RTOS system.
19. The method of claim 12, further comprising:
acquiring a second count value of a counter of the second subsystem;
determining a local time of the second subsystem based on the second count value.
20. A clock synchronization apparatus comprising a first processor and a first communication interface,
the first communication interface is used for receiving UTC time sent by a second subsystem in the chip system and local time of the second subsystem;
the first processor is configured to clock synchronize the local time of the first subsystem and the UTC time based on a time difference between the local time of the first subsystem and the local time of the second subsystem;
and the time delay of the second subsystem for acquiring the UTC time is less than the time delay of the first subsystem for acquiring the UTC time.
21. The apparatus of claim 20, wherein the first processor is configured to:
and performing clock synchronization on the local time of the first subsystem and the time corresponding to the sum of the UTC time and the time difference.
22. The apparatus of claim 20, wherein the first processor is further configured to:
acquiring a frequency difference between the clock frequency of the first subsystem and the clock frequency of the second subsystem;
and correcting the time difference based on the frequency difference.
23. The apparatus of claim 20, wherein the first processor is further configured to:
acquiring a first count value of a counter of the first subsystem;
determining a local time of the first subsystem based on the first count value.
24. The apparatus of claim 20, wherein the first communication interface is configured to:
and receiving a data set sent by the second subsystem, wherein the data set comprises the UTC time and the local time of the second subsystem.
25. The apparatus of claim 24, wherein the data set further comprises an index of the UTC time, and wherein the first processor is further configured to:
caching the data set based on the index; and
based on the index, a corresponding data set is read from the cache.
26. The apparatus of claim 25, wherein the first processor is configured to:
and reading the data set comprising the maximum index from the cache.
27. The apparatus of claim 25, wherein the first processor is configured to:
and in the case that the cache space is full, caching the data set under a target address, wherein the target address is used for caching the data set comprising the minimum index.
28. The apparatus of claim 25, wherein the data set further comprises verification information; the first processor is further configured to:
and checking the integrity of the data set based on the checking information.
29. The apparatus of claim 20, wherein the first subsystem and the second subsystem are connected by hardware.
30. The apparatus of claim 20, wherein the first subsystem is a Linux system and the second subsystem is an RTOS system.
31. A clock synchronization apparatus comprising a second processor and a second communication interface,
the second communication interface is used for receiving UTC time transmitted by a satellite receiving system;
the second processor is used for sending the UTC time and the local time of the second subsystem to a first subsystem in the chip system, so that the first subsystem performs clock synchronization on the local time of the first subsystem and the UTC time based on a time difference between the local time of the first subsystem and the local time of the second subsystem;
and the time delay of the second subsystem for acquiring the UTC time is less than the time delay of the first subsystem for acquiring the UTC time.
32. The apparatus of claim 31, wherein the second processor is further configured to:
and sending the clock frequency of the second subsystem to the first subsystem, so that the first subsystem corrects the time difference based on the frequency difference between the clock frequency of the first subsystem and the clock frequency of the second subsystem.
33. The apparatus of claim 31, wherein the second processor is configured to:
transmitting a data set including the UTC time and a local time of the second subsystem to the first subsystem.
34. The apparatus of claim 33, wherein the data set further comprises an index of the UTC time, wherein the index is used for the first subsystem to cache the data set, and wherein the corresponding data set is read from the cache.
35. The apparatus of claim 33, wherein the data set further comprises verification information, and wherein the verification information is used by the first subsystem to verify the integrity of the data set.
36. The apparatus of claim 31, wherein the first subsystem is connected to the second subsystem by hardware; and/or
The second subsystem is connected with the satellite receiving system in a hardware mode.
37. The apparatus of claim 31, wherein the first subsystem is a Linux system and the second subsystem is an RTOS system.
38. The apparatus of claim 31, wherein the second processor is further configured to:
acquiring a second count value of a counter of the second subsystem;
determining a local time of the second subsystem based on the second count value.
39. A chip system, comprising:
a first subsystem and a second subsystem;
the second subsystem is used for receiving the UTC time sent by the satellite receiving system and sending the UTC time and the local time of the second subsystem to the first subsystem in the chip system;
the first subsystem is used for carrying out clock synchronization on the local time of the first subsystem and the UTC time based on the time difference between the local time of the first subsystem and the local time of the second subsystem;
and the time delay of the second subsystem for acquiring the UTC time is less than the time delay of the first subsystem for acquiring the UTC time.
40. The chip system of claim 39, wherein the first subsystem is configured to:
and performing clock synchronization on the local time of the first subsystem and the time corresponding to the sum of the UTC time and the time difference.
41. The chip system of claim 39, wherein the first subsystem is further configured to:
acquiring a frequency difference between the clock frequency of the first subsystem and the clock frequency of the second subsystem;
and correcting the time difference based on the frequency difference.
42. The chip system of claim 39, wherein the first subsystem is further configured to:
acquiring a first count value of a counter of the first subsystem;
determining a local time of the first subsystem based on the first count value.
43. The chip system of claim 39, wherein the second subsystem is further configured to:
acquiring a second count value of a counter of the second subsystem;
determining a local time of the second subsystem based on the second count value.
44. The chip system of claim 39, wherein the second subsystem is configured to:
transmitting a data set including the UTC time and a local time of the second subsystem to the first subsystem.
45. The chip system of claim 44, wherein the dataset further comprises an index of the UTC time, and wherein the first subsystem is further configured to:
caching the data set based on the index; and
based on the index, a corresponding data set is read from the cache.
46. The chip system of claim 45, wherein the first subsystem is configured to:
and reading the data set comprising the maximum index from the cache.
47. The chip system of claim 45, wherein the first subsystem is configured to:
and in the case that the cache space is full, caching the data set under a target address, wherein the target address is used for caching the data set comprising the minimum index.
48. The system on a chip of claim 45, wherein the data set further comprises verification information; the first subsystem is to:
and checking the integrity of the data set based on the checking information.
49. The chip system according to claim 39, wherein the first subsystem is connected to the second subsystem by hardware; and/or
The second subsystem is connected with the satellite receiving system in a hardware mode.
50. The chip system according to claim 39, wherein the first subsystem is a Linux system and the second subsystem is an RTOS system.
51. An unmanned aerial vehicle, comprising:
the chip system of any one of claims 39 to 50; and
and the satellite receiving system is used for sending the UTC time to a second subsystem in the chip system.
52. A terminal, comprising:
the chip system of any one of claims 39 to 50; and
and the communication system is used for controlling the unmanned aerial vehicle to fly based on the synchronized local time of the first subsystem.
53. A computer-readable storage medium comprising instructions which, when executed on a computer, cause the computer to perform the method of any one of claims 1 to 19.
CN202080015468.1A 2020-10-13 2020-10-13 Clock synchronization method and device, chip system, unmanned aerial vehicle and terminal Pending CN113498625A (en)

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