CN105389286A - BISS C protocol data acquisition and display apparatus - Google Patents
BISS C protocol data acquisition and display apparatus Download PDFInfo
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- CN105389286A CN105389286A CN201510715943.7A CN201510715943A CN105389286A CN 105389286 A CN105389286 A CN 105389286A CN 201510715943 A CN201510715943 A CN 201510715943A CN 105389286 A CN105389286 A CN 105389286A
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
- G06F13/4282—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus
- G06F13/4295—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus using an embedded synchronisation
Abstract
The present invention relates to a BISS C protocol data acquisition and display apparatus. The apparatus comprises an encoder data reception and display panel, a power source and a display screen; the power source is capable of supplying power for the encoder data reception and display panel; the display screen is used for displaying data output by the encoder data reception and display panel; and the encoder data reception and display panel comprises a DSP (Digital Signal Processor) plus a DPGA (Field Programmable Gate Array), an external FLASH, an interface chip, a communication chip and the like. The apparatus provided by the present invention adopts a "DSP+FPGA" hardware combination mode and performs data exchange with an absolute-type encoder of BISS C mode data; the FPGA implements whole logic and time sequence control and configures each interrupt of the DSP, and the DSP implements exchange and processing of data, so that logic units have jobs divided clearly, the control program is simplified, and the speed and accuracy of data exchange are improved.
Description
Technical field
The present invention relates to Data Transport Protocol technical field, particularly a kind of BISSC protocol data gathers and display device.
Background technology
BISSC is a kind of special Data Transport Protocol, is the data layout that a kind of absolute type encoder and external system carry out exchanges data.BISSC pattern is a kind of Fast synchronization serial line interface for scrambler collection position data, and it is a kind of MS master-slave interface.Main interface control position obtains sequential and data rate, and scrambler is from interface, connects between interface by two to unidirectional differential lines is coupling.Be called main interface based on the scrambler collection of BISSC pattern and display system, certain model absolute type encoder is from interface.Two pairs of data that MS master-slave interface exchanges are called MA and SLO, and it is the station acquisition request and the time sequence information that transfer to scrambler from main interface that station acquisition request and time sequence information are transferred to scrambler MA from main interface by MA; Position data is the position data synchronous with MA from encoder transmission to main interface from encoder transmission to the main interface SLO synchronous with MA by SLO.Transmission data layout as shown in Figure 1.
BISSC pattern typically asks end-around carry to be: when idle, and main interface makes MA line keep high level; It is ready by making SLO line keep high level display for scrambler; Main interface asks station acquisition by starting to transmit time clock on MA; Scrambler is set to low level by the SLO line of the second rising edge by MA and makes response; Complete Ack week after date, scrambler transfers data to the main interface with clock synchronous, as shown in fig. 1; When all data all transmit complete, main interface stops clock, and MA line is set to high level; If scrambler not yet prepares to carry out next RQ cycle, SLO line can be set to low level and namely enter time out period by it; When scrambler prepares to carry out next RQ cycle, it points out main interface by mode SLO line being set to high level, and it is ready.
In Fig. 1, in SLO data segment, ACK is the time period that encoder count head calculates absolute position.Start and " 0 " position are the beginning flag of data transmission, and each data are 1 bit data that clock is corresponding, and initial Start position is always high level, and " 0 " position is always low level.Position data is the binary format absolute position data of 26 or 32, for disk light beam encoder, often becomes a full member and has 2
nindividual pulse, umber of pulse is overflowed and is rapped around to 0 position afterwards.Error is fault bit, Low level effective, and " 1 " represents that result is correct, and " 0 " represents inner and detects unsuccessfully.Warn is warning position, and Low level effective, " 0 " represents that reply grating scale or reading window clean.CRC is 6 position data check bit, and the CRC polynomial expression of position, mistake and alarm data is: x
6+ x
1+ x
0, start bit and 0 ignore from CRC calculates.Timeout is time-out information.Main interface by stopping clock or mode MA being set to high level, can reset grating encoder at any time in request cyclic process in addition.
The technology major part of current existence directly adopts FPGA or DSP to receive BISSC data, not to its process and display; Also how scrambler is not carried out to the method for set, in addition also not to the analytic process that the encoder data collected verifies.
Summary of the invention
The present invention will solve technical matters of the prior art, provides the collection of a kind of BISSC protocol data and display device.
In order to solve the problems of the technologies described above, technical scheme of the present invention is specific as follows:
A kind of BISSC protocol data gathers and display device, comprising:
Encoder data receives and display board, power supply and display screen; Described power supply can receive encoder data and display board is powered; Described display screen is used for showing the data that encoder data receives and display board exports;
Described encoder data receives and display board comprises: DSP and FPGA, exterior storage FLASH, interface chip, clock chip, communication chip, power supply chip;
DSP carries out both-way communication by its GPIO and FPGA, and be responsible for exporting data to scrambler and calculate and process, data layout as required serially communication chip sends data;
FPGA is by the bidirectional data exchange with DSP, station acquisition request and time sequence information MA is provided to scrambler, the station acquisition data SLO that scrambler exports with BISS agreement is supplied to DSP, FPGA carries out sequential and logic control simultaneously, need according to sequential the Read-write Catrol carrying out serial port chip, the reseting controling signal of peripheral chip is provided.
In technique scheme, described DSP comprises:
Azimuth encoder, pitching scrambler, liquid crystal display controls and data output display module, and outside FLASH controls and programming module, and outside programming application configuration module.
In technique scheme, described DSP can:
First initialization is carried out, then master routine starts, DSP according to interruption the fastest with 40 μ s for the cycle carries out exchanges data and process, station acquisition request MA is sent by GPIO, and station acquisition data SLO is received between MA high period, register stores SLO data, and find a frame data starting position juxtaposition zone bit according to BISS agreement, then the binary data received is carried out calculating and changing, export with the form of " degree/point/second ", and will " degree/point/second " information displaying in the relevant position of liquid crystal display.
In technique scheme, described FPGA comprises:
GPIO and MA/SLO counterlogic module, sequential and Logic control module, serial port chip Read-write Catrol module, and integral reset signal control module.
In technique scheme, described FPGA can:
Definition input/output signal, then according to the output of external reset chip MAX706 for whole system provides reset signal, FPGA and DSP carries out two-way exchanges data afterwards, the fastest with 40 μ s for the cycle, the station acquisition request sent by DSP and time sequence information MA are supplied to scrambler, the station acquisition data SLO that scrambler exports by BISS agreement is supplied to DSP, and FPGA provides the logic control signal of all peripheral chips in addition, and provides look-at-me for DSP.
In technique scheme, described peripheral chip comprises: asynchronous serial communication chip, outside FLAH chip, reset chip.
In technique scheme, described scrambler is absolute type disk light beam encoder.
The present invention has following beneficial effect:
The present invention adopts the hardware combinations mode of " DSP+FPGA ", exchanges data is carried out with the absolute type encoder of BISSC mode data, FPGA realize arranging logic and sequential control and configure DSP each interrupt, DSP realizes exchange and the process of data, the GPIO of DSP is adopted to put the request of collection and timing control signal MA to encoder output bit, the position data that same employing GPIO capturing and coding device exports, the array mode of this employing " DSP+FPGA ", logical block is not only made to divide the work clear and definite, and simplify control program, improve speed and the degree of accuracy of exchanges data.
The present invention is while carrying out exchanges data with scrambler, add Presentation Function, the position data received is processed, intuitively positional value is presented in LCDs with the form of " degree/point/second " afterwards, the operator's present orientation value of readout equipment and pitching value intuitively can be made.
The present invention has and puts several function, device can carry out communication with master control system, what receive that it transmits puts number order, modified value is received in certain fixing position, and existed in outside FLASH, encoder data numerical value and modified value are subtracted each other, 0 position of equipment can be obtained, carry out position reading as benchmark.
The present invention is to after the data receiver of scrambler, according to the content of BISSC agreement, data are verified, by verification, the state of scrambler and the correctness of data can be determined, improve accuracy and the stability of data acquisition, simultaneously can the problem of Timeliness coverage scrambler, and solve as soon as possible, reduce the error rate of data receiver.
BISSC protocol data of the present invention collection and display device are applied in engineering practice, and data acquisition is stable, intuitive display.Facts have proved: based on the encoder data collection of BISSC pattern and display system can be correct carry out exchanges data with scrambler, and the orientation values of display-object and pitching value in real time, working stability, has stronger practical engineering value.
Accompanying drawing explanation
Below in conjunction with the drawings and specific embodiments, the present invention is described in further detail.
Fig. 1 is BISSC mode data form schematic diagram.
Fig. 2 is BISSC pattern disk light beam encoder data receiver display system one-piece construction figure.
Fig. 3 is that encoder data receives and display board hardware structure diagram.
Fig. 4 is FPGA program circuit schematic diagram.
Fig. 5 is DSP main program flow schematic diagram.
Fig. 6 is that BISS protocol data receives and display test structure schematic diagram.
Fig. 7 is that SignalTap gathers BISS protocol data schematic diagram.
Fig. 8 is liquid crystal display display orientation, pitching value schematic diagram.
Fig. 9 is absolute type encoder data acquisition and the display device schematic diagram of BISSC pattern.
Embodiment
Below in conjunction with accompanying drawing, the present invention is described in detail.
Absolute type shaft angle encoder is the angle measurement element be usually used at present in electro-optical tracking device, for measuring orientation values and the pitching value of tracking target.Absolute type shaft angle encoder adopts serial line interface and data receiving system to exchange data, and data layout adopts BISSC pattern.
BISSC protocol data of the present invention gathers and display device, adopt the mode of " DSP+FPGA ", exchanges data is carried out with absolute type shaft angle encoder, compile the angle code value that it exports, data are verified, to go forward side by side row relax, orientation values will be collected and pitching value employing liquid crystal display shows with the form of " degree/point/second ", obtain the angle information of target intuitively, this device can be widely used in photoelectric tracking measuring equipment, and real-time and axis angle measurement scrambler carries out exchanges data.
According to the content of BISSC agreement, on the hardware configuration basis of " DSP+FPGA ", Verilog language is adopted to programme to FPGA, C language is adopted to programme to DSP, carry out exchanges data with scrambler and School Affairs process is carried out to data, with " degree/point/second " form, the orientation values of target and pitching value being presented on liquid crystal display.System comprises disk light beam encoder, data receiver and display board and a touch liquid crystal display, and disk light beam encoder data receiver and display board are as main equipment, and absolute type disk light beam encoder is as from equipment, and liquid crystal display is as display interface.
As shown in Figure 2, encoder data reception and display system are as main equipment, disk light beam encoder is as from equipment, main equipment is for power from equipment, and station acquisition request and time sequence information MA are provided, after receiving MA signal from device coding device, provide the station acquisition data SLO with MA clock signal synchronization to main equipment.In addition, main equipment is also by serial communication interface, and programming realization exports the control of liquid crystal display and data, real-time on liquid crystal display with the orientation values of the form display-object of " degree/point/second " and pitching value.
Encoder data based on BISSC pattern receives and display board is stuck in hardware design and adopts FPGA+DSP to be main body, extends out the structure of the chips such as FLASH, serial line interface and Signal form translate, realizes the reception of encoder data, coding and Presentation Function.
As shown in Figure 3, DSP is as the core devices of disk light beam encoder data receiver and display system, both-way communication is carried out by its GPIO and FPGA, be responsible for exporting data to scrambler to calculate and process, data layout as required serially communication chip sends data, and then is presented on liquid crystal display with the form of " degree/point/second " by the angle value collected.FPGA is as the core devices of logic control, by the bidirectional data exchange with DSP, station acquisition request and time sequence information MA is provided to scrambler, the station acquisition data SLO that scrambler exports with BISS agreement is supplied to DSP, FPGA carries out sequential and the logic control of whole system simultaneously, need according to sequential the Read-write Catrol carrying out serial port chip, the reseting controling signal of other peripheral chip is provided.The outside FLASH of DSP is program storage chip.Outside serial port chip TL16C554 carries out exchanges data by interface chip and liquid crystal display, and carries out the exchange of serial data with other system.
Encoder data based on BISSC agreement receives and display system Software for Design divides two parts, and a part is FPGA program design, and a part is DSP program design.FPGA mainly realizes the functions such as logic control, reset and interrupt processing.DSP mainly realizes reception and the function such as process and liquid crystal display of encoder data.Fig. 4 and Fig. 5 provides FPGA program circuit schematic diagram and DSP main program flow schematic diagram respectively.
As shown in Figure 4, first FPGA program defines input/output signal, then according to the output of external reset chip MAX706 for whole system provides reset signal, FPGA and DSP carries out two-way exchanges data afterwards, the fastest with 40 μ s for the cycle, the station acquisition request sent by DSP and time sequence information MA are supplied to scrambler, the station acquisition data SLO that scrambler exports by BISS agreement is supplied to DSP, FPGA provides the logic control signal of all peripheral chips in addition, and provides look-at-me for DSP.
As shown in Figure 5, DSP program starts first to carry out initialization, then master routine starts, DSP according to interruption the fastest with 40 μ s for the cycle carries out exchanges data and process, station acquisition request MA is sent by GPIO, and station acquisition data SLO is received between MA high period, register stores SLO data, and find a frame data starting position juxtaposition zone bit according to BISS agreement, then the binary data received is carried out calculating and changing, export with the form of " degree/point/second ", and will " degree/point/second " information displaying in the relevant position of liquid crystal display.
Further, the present invention receives the encoder data based on BISSC agreement and display system is tested, and adopts absolute type disk light beam encoder to gather orientation values and the pitching value of turntable, and with form angles of display value on liquid crystal display of " degree/point/second ".Fig. 6 provides test structure block diagram.
In test, scrambler be installed on can do orientation and pitching rotary motion turntable on, data receiver and display board clamping are received it and are exported data, and show with the form of " degree/point/second ".Encoder data receive and between display board and disk light beam encoder the fastest with 40 μ s for the cycle carries out exchanges data, in test, MA adopts the clock frequency of 2M, and scrambler replys position data SLO between efficient clock high period.Fig. 7 provides the clock MA and data SLO that adopt SignalTap instrument to gather, according to BISS agreement to data analysis.
Analyze from Fig. 7, data segment has 36 valid data, for the scrambler of 26, Biss agreement according to Fig. 1: data bit=1 " Start "+1 " 0 "+26 " Position "+1 " Error "+1 " Warn "+6 " CRC "=36 bit data, reading 36 bit data according to Fig. 7 is
“1|0|
10000101001001101100000110|1|1|
100101”。According to BISS agreement:
1. front two " 10 " is start bit " Start " position and " 0 " thereafter, as the frame head of data
2. valid data position " Position " be "
10000101001001101100000110"
3. two " 11 " are " Error " position and " Warn " position thereafter
4. last six "
100101" be " CRC (6-bit) " check bit
According to BISS agreement, fault bit " 1 " represents that the positional information of transmission is verified by the built-in security checking algorithm of read head; Warning position is also Low level effective, and " 1 " represents that grating scale and reading window clean.Can illustrate that scrambler duty is now good like this.The CRC polynomial expression of position, mistake and alarm data is: x
6+ x
1+ x
0, start bit and " 0 " position are ignored from CRC calculates.By the position of known SLO reading above, mistake and alarm data x="
1000010100100110110000011011 ", " x is carried out to it
6+ x
1+ x
0" polynomial computation, it is " 100101 " that the result obtained gets low six, identical with the CRC check position that image data obtains, and illustrates that the data gathered are effective, correct like this.
Encoder data receives in addition and display system carries out exchanges data with the frequency of 50Hz and liquid crystal display, and with the form display orientation value of " spend/point/second " and pitching value, Fig. 8 provides liquid crystal display schematic diagram.
As shown in Figure 8, after encoder data receives and the station acquisition data SLO received carries out processing and calculate by display board, send to liquid crystal display systems by serial port chip, liquid crystal display shows angle value intuitively with the form of " degree/point/second ", and Refresh Data rate is 50Hz.
As shown in Figure 9, the absolute type encoder data acquisition of BISSC pattern and display device mainly comprise the content of three parts, absolute type encoder data acquisition and the display circuit board of BISSC pattern, the externally fed power supply of circuit board and the LCDs for angles of display value respectively.The absolute type encoder data acquisition of BISSC pattern and display circuit board and absolute type disk light beam encoder carry out exchanges data, and circuit board sends drive singal according to BISSC agreement to disk light beam encoder, and control position obtains sequential and data rate; Receive the position measurement that disk light beam encoder is passed back according to BISSC agreement simultaneously, it is processed and computing, and the data after process are supplied to other subsystem, according to " degree/point/second " form, the angle value collected is presented on liquid crystal display simultaneously.LCDs is the display device of information, the order of sending according to circuit board, demonstrates the angle value that scrambler collects on a corresponding position with " degree/point/second " form.Externally fed module is the power module that 220V turns 5V, is 5V voltage by 220V voltage transitions, is supplied to absolute type encoder data acquisition and the display circuit board of BISSC pattern.
Obviously, above-described embodiment is only for clearly example being described, and the restriction not to embodiment.For those of ordinary skill in the field, can also make other changes in different forms on the basis of the above description.Here exhaustive without the need to also giving all embodiments.And thus the apparent change of extending out or variation be still among the protection domain of the invention.
Claims (7)
1. BISSC protocol data gathers and a display device, it is characterized in that, comprising:
Encoder data receives and display board, power supply and display screen; Described power supply can receive encoder data and display board is powered; Described display screen is used for showing the data that encoder data receives and display board exports;
Described encoder data receives and display board comprises: DSP and FPGA, outside FLASH, interface chip, crystal oscillator, power supply chip;
DSP carries out both-way communication by its GPIO and FPGA, and be responsible for exporting data to scrambler and calculate and process, data layout as required serially communication chip sends data;
FPGA is by the bidirectional data exchange with DSP, station acquisition request and time sequence information MA is provided to scrambler, the station acquisition data SLO that scrambler exports with BISS agreement is supplied to DSP, FPGA carries out sequential and logic control simultaneously, need according to sequential the Read-write Catrol carrying out serial port chip, the reseting controling signal of peripheral chip is provided.
2. BISSC protocol data according to claim 1 gathers and display device, and it is characterized in that, described DSP comprises:
Azimuth encoder data processing module, pitching encoder data processing module, liquid crystal display controls and data output display module, and outside FLASH controls and programming module, and outside programming application configuration module.
3. BISSC protocol data according to claim 2 gathers and display device, it is characterized in that, described DSP can:
First initialization is carried out, then master routine starts, DSP according to interruption the fastest with 40 μ s for the cycle carries out exchanges data and process, station acquisition request MA is sent by GPIO, and station acquisition data SLO is received between MA high period, register stores SLO data, and find a frame data starting position juxtaposition zone bit according to BISS agreement, then the binary data received is carried out calculating and changing, export with the form of " degree/point/second ", and will " degree/point/second " information displaying in the relevant position of liquid crystal display.
4. BISSC protocol data according to claim 1 gathers and display device, and it is characterized in that, described FPGA comprises:
GPIO and MA/SLO counterlogic module, sequential and Logic control module, serial port chip Read-write Catrol module, and integral reset signal control module.
5. BISSC protocol data according to claim 4 gathers and display device, it is characterized in that, described FPGA can:
Definition input/output signal, then according to the output of external reset chip MAX706 for whole system provides reset signal, FPGA and DSP carries out two-way exchanges data afterwards, the fastest with 40 μ s for the cycle, the station acquisition request sent by DSP and time sequence information MA are supplied to scrambler, the station acquisition data SLO that scrambler exports by BISS agreement is supplied to DSP, and FPGA provides the logic control signal of all peripheral chips in addition, and provides look-at-me for DSP.
6. the BISSC protocol data according to any one in claim 1-5 gathers and display device, and it is characterized in that, described peripheral chip comprises: asynchronous serial communication chip.
7. the BISSC protocol data according to any one in claim 1-5 gathers and display device, and it is characterized in that, described scrambler is absolute type disk light beam encoder.
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| CN110940352A (en) * | 2019-11-08 | 2020-03-31 | 中国计量科学研究院 | Automatic calibration system of micro-electro-mechanical system inertia measurement unit and calibration verification method thereof |
| CN110940352B (en) * | 2019-11-08 | 2022-03-08 | 中国计量科学研究院 | Automatic calibration system of micro-electro-mechanical system inertia measurement unit and calibration verification method thereof |
| CN110943011A (en) * | 2019-11-21 | 2020-03-31 | 深圳市德沃先进自动化有限公司 | Quality monitoring controller for bonding equipment and integrated control method thereof |
| CN111413862A (en) * | 2020-03-31 | 2020-07-14 | 涵涡智航科技(玉溪)有限公司 | Unmanned aerial vehicle rocker redundancy control system and control method thereof |
| CN112762969A (en) * | 2020-12-16 | 2021-05-07 | 北京无线电测量研究所 | Circular grating four-reading-head data acquisition processing system and method |
| CN112947163A (en) * | 2021-02-01 | 2021-06-11 | 贵州航天林泉电机有限公司 | DSP-based BISS-C protocol sensor data analysis and extraction method |
| CN112947163B (en) * | 2021-02-01 | 2022-08-05 | 贵州航天林泉电机有限公司 | DSP-based BISS-C protocol sensor data analysis and extraction method |
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