CN109286448B - Standard frequency signal generating system and method based on USB - Google Patents
Standard frequency signal generating system and method based on USB Download PDFInfo
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- CN109286448B CN109286448B CN201811139134.6A CN201811139134A CN109286448B CN 109286448 B CN109286448 B CN 109286448B CN 201811139134 A CN201811139134 A CN 201811139134A CN 109286448 B CN109286448 B CN 109286448B
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Abstract
A standard frequency signal generating system based on a USB is characterized by comprising a board card, a single chip microcomputer unit, an FPGA control unit, a high-precision crystal oscillator unit, an output driver unit, an input driver unit, a differential-to-single-ended signal circuit unit and an external connector unit; the working method comprises signal input, frequency multiplication processing, real-time display, single-end frequency marking signal output and stop output; the system and the method have the advantages of simple structure, convenience in use and carrying and simplicity in operation.
Description
Technical Field
The invention relates to the field of USB power supply and communication and the technical field of signal testing, in particular to a system and a method for generating a standard frequency signal based on a USB.
Background
The USB (Universal Serial Bus) was created to meet the plug and play requirement and support hot plug. The USB protocol versions include USB1.0, USB1.1, USB2.0, USB3.0 and the like. The USB equipment has two power supply modes, one of which is self-powered equipment, and the equipment obtains working voltage from an external power supply; the second is a bus power supply device: the equipment takes electricity from 5V VBUS. USB1.0 and USB1.1 support a low-speed mode of 1.5Mb/s and a full-speed mode of 12 Mb/bs. High speed mode of 480Mb/s is supported above USB 2.0. USB3.0 finally becomes the standard interface of most Mac and PC, brings great improvement on speed, and the transmission rate of 5Gbps exceeds the interface of the previous generation by more than 10 times.
In the hardware design verification process, a standard frequency signal acquisition test and a test for judging whether an output standard frequency signal is correct are required. The standard frequency test is to test whether the parameters such as the frequency, the duty ratio and the like of the standard frequency signal output by the hardware board card meet the requirements. In the test process, the application of the standard frequency signal is ubiquitous, so that a portable device is urgently needed, and the work of signal acquisition and output can be completed by only one USB interface at any time and any place.
Disclosure of Invention
The invention aims to provide a standard frequency signal generation method based on a USB, which can solve the problems in the prior art and is a system and a method with simple structure, convenient use and carrying and simple operation.
The technical scheme of the invention is as follows: a standard frequency signal generating system based on a USB is characterized by comprising a board card, a single chip microcomputer unit, an FPGA control unit, a high-precision crystal oscillator unit, an output driver unit, an input driver unit, a differential-to-single-ended signal circuit unit and an external connector unit; the single chip microcomputer unit, the FPGA control unit, the high-precision crystal oscillator unit, the output driver unit, the input driver unit, the differential-to-single-ended signal circuit unit and the external connector unit are integrally mounted on the board card; the single chip microcomputer unit is provided with a USB interface and is in bidirectional connection with the PC; the USB interface is led out from the board card, is convenient for communicating with a PC, and the PC provides power for the board card; the input end of the FPGA control unit is connected with the high-precision crystal oscillator unit and is also in bidirectional connection with the single chip microcomputer unit, the output driver unit, the input driver unit and the differential-to-single-ended signal circuit unit; the pair of external connector units receive single-ended input signals and are connected with the input driver unit, and the output signals are accessed to the FPGA control unit; the external connector unit receives a differential input signal, and is connected to the FPGA control unit after passing through the differential-to-single-ended signal circuit unit; the FPGA control unit carries out frequency multiplication processing on the high-precision crystal resonator, receives a PC instruction and outputs a standard frequency signal, and the standard frequency signal is output outwards through the output driver unit and the external connector unit.
The size of the board card is 7.0cm multiplied by 5.0cm, a USB interface of the single chip microcomputer unit is led out from the outside, and the communication with the PC is realized while the power is supplied to the board card.
The single chip microcomputer unit is a PIC24FJ128GB210 chip with a USB interface; the single chip microcomputer unit is connected with an external USB interface through a USB interface (interface signals A _ USB _ P + and A _ USB _ P +), and the host computer is communicated with the local board through a USB communication protocol. The single chip microcomputer unit is connected with the FPGA through an EPMP (PSP) parallel communication interface to realize the parallel communication of the EPMP and the PSP. The working clock of the singlechip is provided by a crystal oscillator of 12 MHz. The slave single chip microcomputer signals comprise RS-232 serial port debugging signals, single chip microcomputer programming interface signals (interface signals for downloading programs and debugging), USB interface signals and parallel communication interface signals.
The input driver unit is an SN74LVC1G14 driving chip, is connected with the FPGA control unit and the output end of the external connector unit, and is used for acquiring an external single-ended input signal; two paths of single-ended signal input are preset on the board card, and the specific connection relationship is that two paths of single-ended input signals (SIG _ IN1 and SIG _ IN2) are introduced into an external connector DB9, and after one-stage driving capability is added to a chip driven by an SN74LVC1G14, FPGA (access signal names SIG1_ FPGA and SIG2_ FPGA) are accessed for collection and use.
The differential-to-single-ended signal circuit unit is formed by connecting an SP485EEN chip or an HCPL0631 chip FPGA with the input end of an external connector and is used for acquiring external differential input signals. A pair of differential signals (DIFF _ SIG1+, DIFF _ SIG 1-) are introduced into the board card IN advance, the FPGA is used for collecting input signals after the difference is converted into the single end through the SP485EEN chip, and the FPGA (access signal names DIFF _ IN1 and DIFF _ IN2) is used for collecting input signals after the difference is converted into the single end through the other pair of differential signals (DIFF _ SIG2+, DIFF _ SIG 2-) is converted into the single end through the HCPL-0631-. The preset two differential-to-single-ended chips and a plurality of differential-to-single-ended functional chips can be selected according to application in specific engineering projects.
The output driving unit circuit is used for driving signals (with signal names of SOUT1_ FPGA and SOUT2_ FPGA) output by the FPGA to be output to the external connector DB9 after being driven by the SN74LVC1G125DBVR chip. Two paths of signals SIG _ OUT1 and SIG _ OUT2 are preset and output to the external connector as output signals.
The pair of external connectors are DB9 connectors. The method provides an input and output interface of a standard frequency signal, wherein 2 paths of single-end input signals (SIG _ IN1 and SIG _ IN2), 2 paths of differential input signals (DIFF _ SIG1+/-, DIFF _ SIG2 +/-), 2 paths of single-end output signals (SIG _ OUT1 and SIG _ OUT 2) and GND signals are corresponding to a single-end signal grounding point are preset.
The FPGA control unit is an EP3C5E144I7N control chip and is connected with the high-precision crystal oscillator unit; the FPGA control unit outputs a single-ended signal, the single-ended signal is sent to the external connector through the output driver unit, and the input signal of the input driver is subjected to frequency scaling signal acquisition.
A frequency marking signal generating method based on USB is characterized by comprising the following steps:
(1) an external single-ended input signal and an external differential input signal are respectively input to the FPGA control unit through the input driver unit and the differential-to-single-ended signal input circuit unit;
(2) the FPGA control unit carries out frequency multiplication processing on the high-precision crystal resonator, utilizes a self-contained PLL structure in the FPGA control unit to carry out frequency multiplication on a counting clock of the FPGA control unit to 100MHz, namely, the FPGA control unit collects input signals with the precision of 10ns and carries out counting operation with the unit of 10ns, and the FPGA control unit uploads a high-level counting value and a low-level counting value of the collected signals. The specific implementation of the standard frequency signal test is that an external input signal is input to the FPGA control unit in a single-ended pulse form after passing through an input driver or a differential-to-single-ended circuit, the FPGA control unit counts input pulses by taking 100MHz as a reference clock, wherein the FPGA control unit counts the time from the adjacent rising edge to the falling edge of the input pulse signal (namely, a high-level count value), and counts the time from the adjacent falling edge to the rising edge of the input pulse signal (namely, a low-level count value). The output standard frequency signal is output by the FPGA control unit after receiving the instruction of the PC to output the appointed high and low level (and different duty ratios). If a communication protocol is agreed between the PC and the singlechip, a specified instruction is received (namely the FPGA control unit acquires that the data on the address 1 is 0x1000, namely a 1KHz signal with 50% of duty ratio is output; acquires that the data on the address 1 is 0x1001, namely a 1KHz signal with 20% of duty ratio is output; and the communication protocol with duty ratio and frequency can be set according to requirements).
(3) The single chip microcomputer unit collects the counting value of the signal collected in the step (2), and displays the duty ratio, the frequency or the period value on an upper PC in real time; the specific calculation is completed by the single chip microcomputer, and comprises calculation according to a duty ratio, namely the duty ratio = a high level count value/(a high level count value + a low level count value); frequency = 1/(high level count value + low level count value); cycle = high level count value + low level count value.
(4) The upper PC can confirm the output and stop the output of the single-end standard frequency signal according to the output instruction of the standard frequency signal.
The counting operation in the step (2) in units of 10ns includes counting a high level and counting a low level for each period.
And (4) in the step (3), the duty ratio, the frequency or the period value is displayed on the upper PC by scrolling at intervals of 1s, and the latest 5 times of counting values, the maximum counting value and the minimum counting value are displayed.
The single-ended frequency marking signal in the step (4) is 1KHz, and can also be set by rewriting corresponding program values of the FPGA according to the test requirement.
The invention has the advantages that: a high-precision crystal resonator is adopted, and then the acquisition precision can reach 10ns through PLL inside the FPGA; the singlechip is connected with the PC through a USB interface on hardware, and 5V electricity is taken from the USB interface to supply power to the board card; simple structure, convenient use and carrying and simple operation.
Drawings
FIG. 1 is a block diagram illustrating an overall structure of a USB-based standard frequency signal generating system according to the present invention.
Fig. 2 is a schematic diagram illustrating a specific connection principle of a single chip unit in a USB-based standard frequency signal generating system according to the present invention.
FIG. 3 is a schematic diagram of a chip unit in a standard frequency signal generating system based on USB according to the present invention.
FIG. 4 is a schematic diagram illustrating a specific connection principle of an input driver unit in a USB-based standard frequency signal generating system according to the present invention.
Fig. 5 is a schematic diagram illustrating a specific connection principle of a circuit unit for converting a differential signal to a single-ended signal in a USB-based standard frequency signal generating system according to the present invention.
Fig. 6 is a schematic diagram illustrating a specific connection principle of an output driving unit circuit in a USB-based standard frequency signal generating system according to the present invention.
Fig. 7 is a schematic diagram illustrating a specific connection principle of an external connector in a USB-based standard frequency signal generating system according to the present invention.
Fig. 8 is a schematic diagram illustrating a specific connection principle of an FPGA control unit in a USB-based standard frequency signal generating system according to the present invention.
Fig. 9 is a schematic diagram illustrating a signal configuration connection principle of an FPGA control unit in a USB-based standard frequency signal generating system according to the present invention.
Detailed Description
Example (b): a standard frequency signal generating system based on a USB is characterized by comprising a board card, a single chip microcomputer unit, an FPGA control unit, a high-precision crystal oscillator unit, an output driver unit, an input driver unit, a differential-to-single-ended signal circuit unit and an external connector unit; the single chip microcomputer unit, the FPGA control unit, the high-precision crystal oscillator unit, the output driver unit, the input driver unit, the differential-to-single-ended signal circuit unit and the external connector unit are integrally mounted on the board card; the single chip microcomputer unit is provided with a USB interface and is in bidirectional connection with the PC; the USB interface is led out from the board card, is convenient for communicating with a PC, and the PC provides power for the board card; the input end of the FPGA control unit is connected with the high-precision crystal oscillator unit and is also in bidirectional connection with the single chip microcomputer unit, the output driver unit, the input driver unit and the differential-to-single-ended signal circuit unit; the pair of external connector units receive single-ended input signals and are connected with the input driver unit, and the output signals are accessed to the FPGA control unit; the external connector unit receives a differential input signal, and is connected to the FPGA control unit after passing through the differential-to-single-ended signal circuit unit; the FPGA control unit carries out frequency multiplication processing on the high-precision crystal resonator, receives a PC instruction and outputs a standard frequency signal, and the standard frequency signal is output outwards through the output driver unit and the external connector unit.
The size of the board card is 7.0cm multiplied by 5.0cm, a USB interface of the single chip microcomputer unit is led out from the outside, and the communication with the PC is realized while the power is supplied to the board card.
The single chip microcomputer unit is a PIC24FJ128GB210 chip with a USB interface, the internal structure block diagram of the chip is shown in fig. 2 and fig. 3, the specific connection relation on the circuit is shown in fig. 2, the single chip microcomputer unit is connected with an external USB interface through the USB interface (interface signals A _ USB _ P +, A _ USB _ P +), and the host computer is communicated with the local board through a USB communication protocol. The singlechip microcomputer unit is connected with the FPGA control unit through an EPMP (PSP) parallel communication interface to realize the parallel communication of the EPMP and the PSP. The working clock of the singlechip is provided by a crystal oscillator of 12 MHz. The slave single chip microcomputer signals comprise RS-232 serial port debugging signals, single chip microcomputer programming interface signals (interface signals for downloading programs and debugging), USB interface signals and parallel communication interface signals.
The input driver unit is formed by connecting an SN74LVC1G14 driving chip with an FPGA control unit and an output end of an external connector and is used for collecting external single-ended input signals. The specific circuit is shown IN fig. 4, the board card presets two single-ended signal inputs, and the specific connection relationship is that two single-ended input signals (SIG _ IN1 and SIG _ IN2) are introduced into the external connector DB9, and are connected to the FPGA control unit (connected to signal names SIG1_ FPGA and SIG2_ FPGA) for acquisition after the SN74LVC1G14 drives the chip to increase the first-stage driving capability.
The differential-to-single-ended signal circuit unit is an SP485EEN chip or an HCPL0631 chip FPGA control unit and is connected with the input end of an external connector and used for collecting external differential input signals. The specific circuit is as shown IN fig. 5, a pair of differential signals (DIFF _ SIG1+, DIFF _ SIG 1-) are introduced into the board card IN advance, the FPGA control unit acquires input signals after the differential to single conversion is realized through an SP485EEN chip, and the FPGA control unit (access signal names DIFF _ IN1 and DIFF _ IN2) acquires input signals after the differential to single conversion is realized through an HCPL-0631-000E chip. The preset two differential-to-single-ended chips and a plurality of differential-to-single-ended functional chips can be selected according to application in specific engineering projects.
The output driving unit circuit is used for outputting signals (with signal names of SOUT1_ FPGA and SOUT2_ FPGA) output by the FPGA control unit to the external connector DB9 after being driven by the SN74LVC1G125DBVR chip. The specific circuit connection is as shown in fig. 6, and two paths of signals SIG _ OUT1 and SIG _ OUT2 are preset and output to the external connector as output signals.
The pair of external connectors are DB9 connectors. The specific circuit of the input/output interface for providing the frequency scaling signal is shown IN fig. 7, wherein 2 single-ended input signals (SIG _ IN1 and SIG _ IN2), 2 differential input signals (DIFF _ SIG1+/-, DIFF _ SIG2 +/-), and 2 single-ended output signals (SIG _ OUT1 and SIG _ OUT 2) are preset, and the GND signal is a corresponding single-ended ground signal.
The FPGA control unit is an EP3C5E144I7N control chip and is connected with the high-precision crystal oscillator unit; the FPGA control unit outputs a single-ended signal, the single-ended signal is sent to the external connector through the output driver unit, and the input signal of the input driver is subjected to frequency scaling signal acquisition. The specific circuit connection is as shown in fig. 8, signals in the figure are schematic diagrams of connection with a parallel bus of a single chip unit, connection with an input/output driver and a differential-to-single-ended unit, and connection with a high-precision crystal resonator, and signals in fig. 9 are connection of configuration signals of an FPGA control unit.
A frequency marking signal generating method based on USB is characterized by comprising the following steps:
(1) an external single-ended input signal and an external differential input signal are respectively input to the FPGA control unit through the input driver unit and the differential-to-single-ended signal input circuit unit;
(2) the FPGA control unit carries out frequency multiplication processing on the high-precision crystal resonator, a PLL structure in the FPGA control unit is utilized to carry out frequency multiplication on the FPGA control unit to 100MHz by using a counting clock, namely, an input signal is acquired with the precision of 10ns, counting operation is carried out by taking 10ns as a unit, and the FPGA uploads a high-level count value and a low-level count value of the acquired signal. The specific implementation of the standard frequency signal test is that an external signal is input to the FPGA control unit in a single-ended pulse form after passing through an input driver or a differential-to-single-ended circuit, the FPGA control unit counts input pulses by using 100MHz as a reference clock, wherein the FPGA counts the time from a rising edge to a falling edge adjacent to the input pulse signal (i.e., a high-level count value), and counts the time from a falling edge to a rising edge adjacent to the input pulse signal (i.e., a low-level count value). The output standard frequency signal is output by the FPGA control unit after receiving the instruction of the PC to output the appointed high and low level (and different duty ratios). If a communication protocol is agreed between the PC and the singlechip, a specified instruction is received (namely the FPGA acquires that the data on the address 1 is 0x1000, namely a 1KHz signal with 50% of duty ratio is output; acquires that the data on the address 1 is 0x1001, namely a 1KHz signal with 20% of duty ratio is output; and the communication protocol can set the duty ratio and the frequency according to requirements).
(3) The single chip microcomputer unit collects the counting value of the signal collected in the step (2), and displays the duty ratio, the frequency or the period value on an upper PC in real time; the specific calculation is completed by the single chip microcomputer, and comprises calculation according to a duty ratio, namely the duty ratio = a high level count value/(a high level count value + a low level count value); frequency = 1/(high level count value + low level count value); cycle = high level count value + low level count value.
(4) The upper PC can confirm the output and stop the output of the single-end standard frequency signal according to the output instruction of the standard frequency signal.
The counting operation in the step (2) in units of 10ns includes counting a high level and counting a low level for each period.
And (4) in the step (3), the duty ratio, the frequency or the period value is displayed on the upper PC by scrolling at intervals of 1s, and the latest 5 times of counting values, the maximum counting value and the minimum counting value are displayed.
The single-ended frequency marking signal in the step (4) is 1KHz, and can also be set by rewriting corresponding program values of the FPGA control unit according to the test requirement.
The present invention will be described in further detail with reference to the following examples and the accompanying drawings.
The invention designs a method for realizing portable USB equipment with a standard frequency signal generator and a test module, which comprises the following steps: a processor with a USB interface is adopted, a single chip microcomputer PIC24FJ128GB210 is taken as an example, one end of the USB interface can adopt a square-head USB interface connector, a general USB emulator adopts a square-head USB interface to be connected with an emulator, one end of a butt joint computer is a flat-port USB interface connector and is connected to a PC through a general USB cable, and the equipment is powered through the USB interface and simultaneously realizes communication with the PC.
A PMP interface of the single chip is connected to an FPGA control unit (taking EP3C5E144I7N as an example), the FPGA control unit is simultaneously connected with a high-precision crystal oscillator, and external input differential or single-ended signals can be connected to the FPGA control unit through a corresponding processing circuit, so that the acquisition of frequency and duty ratio and the output of designated frequency are realized; the external single-ended input signal is input from the connector, is driven by an input driver chip (taking SN74LVC1G14 as an example) and then is connected to the FPGA control unit, and the external differential input signal is input from the connector, is connected to the FPGA control unit after passing through a differential-to-single-ended chip (taking SP485EEN and HCPL0631 as examples), so that the signal input is completed. The frequency scaling signal generator outputs a single-ended signal from the FPGA, and then outputs the signal to the connector via an output driver (taking 1G125 as an example). The DB9 connector may be chosen to be inexpensive for the external connector. The standard frequency signal to be tested can be an RS-422 serial port communication signal.
The PIC24FJ128GB210 is a single chip microcomputer chip with a USB interface, and has the advantages of simple software programming and hardware circuit design and strong operability. Basic communication can be accomplished through a USB interface.
The FPGA control unit can select EP3C5E144I7N, the chip is packaged into a surface-mounted chip, welding is simple, PLL resources are arranged in the FPGA, frequency doubling can be achieved, and testing accuracy is improved. The FPGA control unit can output a standard frequency signal with specified duty ratio and frequency according to actual needs, and can also collect the duty ratio and the frequency of the input standard frequency signal.
The SN74LVC1G14 and SN74LVC1G125 chips can increase the driving capability of signals, provide certain output current for output signals, provide certain driving capability for the FPGA control unit to process input signals, and provide certain driving capability for the output of frequency marking signals.
The SP485EEN chip is a differential-to-single-ended chip, and the chip can meet the function of collecting differential standard frequency signals entering an FPGA.
Description of the supply circuit: the power supply chip APL5916 realizes the conversion of 5V to 3.3V, the conversion of 5V to 2.5V and the conversion of 5V to 1.2V, and supplies power for IO, PLL and nuclear power for the FPGA. And 3.3V is also provided for supplying power to the singlechip. The 5V power is taken from the USB interface. The power-on reset circuit can be realized by TPS3823, and the circuit starts to work after power-on is firstly reset uniformly for each device by a low level of 200 ms.
Detailed working principle: an external signal is accessed into an FPGA control unit after passing through a processing circuit (a differential-to-single end and an input driver), a 50MH high-precision crystal oscillator (with the precision as high as 1 ppm) is connected on the FPGA control unit, then the frequency of the external signal is doubled to 100MHz by a PLL (phase locked loop) arranged in the FPGA control unit, the input signal is collected with the precision of 10ns, a counting value with 10ns as a unit is obtained, wherein the counting value comprises a high-level counting value and a low-level counting value of each period, the high-level counting value and the low-level counting value are collected by a single chip microcomputer through a PMP (pulse width modulation) bus, the high-level counting value and the low-level counting value are displayed on a PC (personal computer) interface, the specific duty ratio and the frequency (or period value) are displayed on a rolling screen at intervals of 1s on the interface after the counting value is. The PC interface has a standard frequency signal output instruction, after clicking to start outputting, a single-ended standard frequency signal (1 KHz) is output, and after pressing a stop button, the output is stopped (note: the standard frequency signal can be set according to specific needs, and the FPGA control unit code can be specifically changed to realize the purpose). The connection of the singlechip and the PC is connected on hardware through a USB interface, and 5V electricity is taken out from the USB interface to supply power for the board card. The software writes a special singlechip drive program, and realizes control and display through a PC interface.
The above embodiments are merely specific application examples of the portable USB device with the standard frequency signal generator and the test module, and do not limit the claims of the present application. All modifications and insubstantial improvements over what is claimed herein are intended to be covered by the claims.
Nothing in this specification is said to apply to the prior art.
Claims (10)
1. A standard frequency signal generating system based on a USB is characterized by comprising a board card, a single chip microcomputer unit, an FPGA control unit, a high-precision crystal oscillator unit, an output driver unit, an input driver unit, a differential-to-single-ended signal circuit unit and an external connector unit; the single chip microcomputer unit, the FPGA control unit, the high-precision crystal oscillator unit, the output driver unit, the input driver unit, the differential-to-single-ended signal circuit unit and the external connector unit are integrally mounted on the board card; the single chip microcomputer unit is provided with a USB interface and is in bidirectional connection with the PC; the USB interface is led out from the board card, is convenient for communicating with a PC, and the PC provides power for the board card; the input end of the FPGA control unit is connected with the high-precision crystal oscillator unit, and meanwhile, the FPGA control unit is also in bidirectional connection with the single chip microcomputer unit, the output driver unit, the input driver unit and the differential-to-single-ended signal circuit unit; the pair of external connector units receive single-ended input signals and are connected with the input driver unit, and the output signals are accessed to the FPGA control unit; the external connector unit receives a differential input signal, and is connected to the FPGA control unit after passing through the differential-to-single-ended signal circuit unit; the FPGA control unit carries out frequency multiplication processing on the high-precision crystal resonator, receives a PC instruction and outputs a standard frequency signal, and the standard frequency signal is output outwards through the output driver unit and the external connector unit.
2. The system for generating a standard frequency signal based on the USB as claimed in claim 1, wherein the size of the board card is 7.0cm × 5.0cm, a USB interface of the single chip microcomputer unit is led out from the outside, and the communication with the PC is realized while the power is supplied to the board card.
3. The system for generating a frequency-scaled signal based on USB according to claim 1, wherein the single chip microcomputer unit is a PIC24FJ128GB210 chip with a USB interface; the single chip microcomputer unit is connected with an external USB interface through a USB interface, and the communication between the PC and the USB communication protocol of the standard frequency signal generation and test system based on the USB is realized.
4. The system according to claim 1, wherein the input driver unit is an SN74LVC1G14 driver chip connected to the FPGA control unit and the output of the external connector unit for collecting external single-ended input signals.
5. The system according to claim 1, wherein the differential-to-single-ended signal circuit unit is an SP485EEN chip or an HCPL0631 chip.
6. A USB based standard frequency signal generating system as claimed in claim 1 wherein said external connector is a DB9 connector for providing input and output interfaces for standard frequency signals; and 2 paths of single-end input signals, 2 paths of differential input signals, 2 paths of single-end output signals and GND signals serving as grounding points of corresponding single-end signals are preset in the external connector.
7. The system of claim 1, wherein the FPGA control unit is an EP3C5E144I7N control chip connected to the high-precision crystal oscillator unit; the FPGA control unit outputs a single-ended signal, the single-ended signal is sent to the external connector through the output driver unit, and the input signal of the input driver is subjected to frequency scaling signal acquisition.
8. A frequency marking signal generating method based on USB is characterized by comprising the following steps:
(1) an external single-ended input signal and an external differential input signal are respectively input to the FPGA control unit through the input driver unit and the differential-to-single-ended signal input circuit unit;
(2) the FPGA control unit performs frequency multiplication on the high-precision crystal resonator, utilizes a self-contained PLL structure in the FPGA control unit to multiply the frequency of the counting clock of the FPGA control unit to 100MHz, namely, the FPGA control unit acquires input signals with the precision of 10ns and performs counting operation by taking 10ns as a unit, and uploads a high-level count value and a low-level count value of the acquired signals; an external input signal is input into the FPGA control unit in a single-ended pulse form after passing through an input driver or a differential-to-single-ended circuit, the FPGA control unit counts input pulses by taking 100MHz as a reference clock, wherein the FPGA control unit counts the time from the adjacent rising edge to the falling edge of the input pulse signal, namely a high-level count value, and counts the time from the adjacent falling edge to the rising edge of the input pulse signal, namely a low-level count value; the FPGA control unit receives the instruction of the PC to output specified high and low levels, namely levels with different duty ratios;
(3) the single chip microcomputer unit collects the counting value of the signal collected in the step (2), and displays the duty ratio, the frequency or the period value on an upper PC in real time; the specific calculation is completed by the single chip microcomputer, and comprises the following steps of calculating according to the duty ratio, namely:
duty = high level count value/(high level count value + low level count value);
frequency = 1/(high level count value + low level count value);
cycle = high level count value + low level count value;
(4) the upper PC can confirm the output and stop the output of the single-end standard frequency signal according to the output instruction of the standard frequency signal.
9. The method according to claim 8, wherein the counting operation in the step (2) in units of 10ns comprises counting high and low levels every period.
10. The method according to claim 8, wherein the displaying of the duty ratio, frequency or period value on the upper PC in step (3) is a scrolling display with 1s interval, and the latest 5 counts and the maximum and minimum counts are displayed; and (4) setting the single-ended frequency marking signal in the step (4) to be 1KHz by rewriting a corresponding program value of the FPGA control unit according to the test requirement.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201811139134.6A CN109286448B (en) | 2018-09-28 | 2018-09-28 | Standard frequency signal generating system and method based on USB |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201811139134.6A CN109286448B (en) | 2018-09-28 | 2018-09-28 | Standard frequency signal generating system and method based on USB |
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| Publication Number | Publication Date |
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| CN109286448A CN109286448A (en) | 2019-01-29 |
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Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0645689B1 (en) * | 1993-09-29 | 2000-04-05 | Seiko Epson Corporation | Clock supply system |
| CN202488467U (en) * | 2012-01-17 | 2012-10-10 | 吴青萍 | Ultrashort wave frequency spectrum monitoring receiver |
| CN103077258A (en) * | 2012-12-30 | 2013-05-01 | 陕西海泰电子有限责任公司 | Synchronous data acquisition card (DAC) with high speed |
| CN104158540A (en) * | 2014-08-27 | 2014-11-19 | 河北大学 | Three-phase digital phase-locked loop and phase lock method |
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Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0645689B1 (en) * | 1993-09-29 | 2000-04-05 | Seiko Epson Corporation | Clock supply system |
| CN202488467U (en) * | 2012-01-17 | 2012-10-10 | 吴青萍 | Ultrashort wave frequency spectrum monitoring receiver |
| CN103077258A (en) * | 2012-12-30 | 2013-05-01 | 陕西海泰电子有限责任公司 | Synchronous data acquisition card (DAC) with high speed |
| CN104158540A (en) * | 2014-08-27 | 2014-11-19 | 河北大学 | Three-phase digital phase-locked loop and phase lock method |
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