CN104158540A - Three-phase digital phase-locked loop and phase lock method - Google Patents
Three-phase digital phase-locked loop and phase lock method Download PDFInfo
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- CN104158540A CN104158540A CN201410426553.3A CN201410426553A CN104158540A CN 104158540 A CN104158540 A CN 104158540A CN 201410426553 A CN201410426553 A CN 201410426553A CN 104158540 A CN104158540 A CN 104158540A
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Abstract
The invention provides a three-phase digital phase-locked loop and a phase lock method. The three-phase digital phase-locked loop comprises a Clark conversion unit, a Park conversion unit, a second-order generalized integrator, a subtracter, a PI (Proportional Integral) controller, a local synchronizing signal generation unit and a trigonometric table storage. According to the three-phase digital phase-locked loop and the phase lock method, an output uq of the Park conversion unit is taken as an input v of the second-order generalized integrator, a center frequency of the second-order generalized integrator is 100 Hz, when a three-phase power grid is unbalanced, an output v' of the second-order generalized integrator is second harmonic sin2omegat in a negative sequence component, a difference between the uq and the v' is obtained by adopting the subtracter, so that the interference of the second harmonic is eliminated, and thus the phase of the power grid can be normally tracked by the three-phase digital phase-locked loop. A standard frequency signal is generated by adopting a crystal oscillator, and a local synchronizing signal of 50 Hz is formed through frequency division, so that the phase-locked loop does not need to track the frequency of the power grid and only tracks the phase.
Description
Technical field
The present invention relates to a kind of phase-locked loop, specifically a kind of three-phase digital phase-locked loop and phase-lock technique.
Background technology
In the power electronic equipment being associated with three phase network at some, it is very important obtaining the real-time fundamental phase of three phase network, phase-locked loop (Phase-Locked Loop, PLL) be that a kind of output signal that can make keeps the automatic closed loop control system of synchronizeing in phase place and frequency with input signal, be widely used, can be used for following the tracks of electrical network phase place in the control procedure of power electronic equipment.
Three phase network is in transient fault or some situation, and it is uneven that three-phase voltage can become, and this unbalanced threephase voltage can be expressed as the intersection of a series of unbalanced harmonic compositions.Usually, three-phase voltage can be expressed as the intersection of positive sequence component, negative sequence component and zero-sequence component.For adopting the distributed power supply system that isolating transformer net side is corner connection, can ignore zero-sequence component, only comprise positive sequence component and negative sequence component.
Conventional phase locked loops is made up of phase discriminator, loop filter and voltage controlled oscillator three parts conventionally.Phase discriminator is for detection of the phase difference of input signal and output signal, and convert the phase signal detecting to voltage signal output, this voltage signal forms the control voltage of voltage controlled oscillator after low pass filter filtering, and the phase place of voltage controlled oscillator output signal is implemented to control.Conventional phase locked loops can be carried out Phase Tracking at three phase network voltage during in poised state well, but, in the time that three phase network is uneven, for same negative sequence component frequently, phase discriminator output can be subject to the interference of second harmonic, thereby make phase-locked loop can not normally follow the tracks of electrical network phase place, cause phase-locked failure.
Summary of the invention
One of object of the present invention is just to provide a kind of three-phase digital phase-locked loop, can not normally follow the tracks of the problem of electrical network phase place to solve existing phase-locked loop in the time that three phase network is uneven.
Two of object of the present invention is just to provide a kind of three-phase digital phase-lock technique, all can three phase network be carried out to Phase Tracking at three-phase grid balance and nonequilibrium condition.
One of object of the present invention is achieved in that a kind of three-phase digital phase-locked loop, comprising: Clark converter unit, joins with Park converter unit, for gathering three phase network voltage u
a, u
b, u
cand carry out Clark conversion to obtain α axle component u under two-phase rest frame
αwith beta-axis component u
β;
Park converter unit, joins with described Clark converter unit, trigonometric table memory, second order improper integral device and subtracter respectively, for receiving the local synchronization signal phase θ being exported by trigonometric table memory
0sine value and cosine value, and to α axle component u under two-phase rest frame
αwith beta-axis component u
βcarry out Park conversion to obtain q axle component u under two-phase rotating coordinate system
q;
Second order improper integral device, joins with described Park converter unit and subtracter respectively, for by the output u of described Park converter unit
qas input v, and export v ' to subtracter; The centre frequency of described second order improper integral device is 100Hz;
Subtracter, joins with described Park converter unit, described second order improper integral device and PI controller respectively, for making the output u of described Park converter unit
qask difference with the output v ' of described second order improper integral device, to obtain comprising three phase network phase theta and local synchronization signal phase θ
0the feedback information of difference Δ θ;
PI controller, joins with described subtracter and local synchronization signal generation unit respectively, adjusts for local synchronization signal phase local synchronization signal generation unit being generated according to the feedback information of described subtracter output;
Local synchronization signal generation unit, join with described PI controller and trigonometric table memory, for generation of the local synchronization signal of 50Hz, and control trigonometric table memory even output m within each cycle of local synchronization signal and organize sine value and cosine value discrete, local synchronization signal phase, simultaneously under the control of described PI controller, within each cycle of local synchronization signal, the phase difference of corresponding m group three phase network phase place and local synchronization signal phase, carries out m time to the phase place of local synchronization signal and adjusts; M is nature positive integer; And
Trigonometric table memory, join with described local synchronization signal generation unit and described Park converter unit respectively, for under the control of described local synchronization signal generation unit, within each cycle of local synchronization signal, evenly output m organizes sine value and cosine value discrete, local synchronization signal phase.
Described local synchronization signal generation unit comprises:
Mark is maker frequently, joins, for generation of the mark signal frequently of 50 × 4nm Hz with 4 frequency units; N is nature positive integer;
4 frequency units, join with described PI controller, described mark frequency maker and n frequency unit respectively, carry out 4 frequency divisions, to obtain the pulse signal of 50 × nm Hz for the mark frequency signal to described 50 × 4nm Hz; Simultaneously, under the control of described PI controller, within each cycle of local synchronization signal, mark to described 50 × 4nm Hz frequently signal carry out realizing m adjustment in the process of 4 frequency divisions, the result of adjustment is that the mark frequency signal of described 50 × 4nm Hz is carried out to 4 frequency divisions, 3 frequency divisions or 5 frequency divisions one time each time;
N frequency unit, joins with described 4 frequency units and m frequency unit respectively, for the pulse signal of described 50 × nm Hz is carried out to n frequency division, to obtain the pulse signal of 50 × m Hz; And
M frequency unit, joins with described n frequency unit and described trigonometric table memory respectively, for the pulse signal of described 50 × m Hz is carried out to m frequency division, to obtain the local synchronization signal of 50 Hz; Meanwhile, control described trigonometric table memory even output m within each cycle of local synchronization signal and organize sine value and cosine value discrete, local synchronization signal phase.
The process that described in the control of described PI controller, 4 frequency units are adjusted the phase place of local synchronization signal is specially:
As | Δ θ | when≤δ, described in the control of described PI controller 4 frequency units to the mark of described 50 × 4nm Hz frequently signal carry out 4 frequency divisions one time;
In the time of Δ θ > δ, described in the control of described PI controller 4 frequency units to the mark of described 50 × 4nm Hz frequently signal carry out 3 frequency divisions one time;
In the time of Δ θ < ﹣ δ, described in the control of described PI controller 4 frequency units to the mark of described 50 × 4nm Hz frequently signal carry out 5 frequency divisions one time;
Wherein, δ is a positive number of presetting.
Three-phase digital phase-locked loop provided by the present invention, when voltage falls or when other reasons causes three phase network uneven, the output u of Park converter unit
qmeeting stack second harmonic sin2 ω t, the interference of same negative sequence component frequently formation when this second harmonic sin2 ω t is in fact three phase network imbalance.The present invention makes the output u of Park converter unit
qas the input v of second order improper integral device, the centre frequency that second order improper integral device is set is 100Hz, the output v ' of second order improper integral device is the second harmonic sin2 ω t in negative sequence component in the time that three phase network is uneven, then adopts subtracter to make the output u of Park converter unit
qask difference with the output v ' of second order improper integral device, can eliminate the interference of second harmonic, thereby make three-phase digital phase-locked loop can normally follow the tracks of electrical network phase place.For three-phase grid balance state, due to u
qin the second harmonic that do not superpose, therefore, the output v ' of second order improper integral device is zero output, is equivalent to second order improper integral device inoperative, the output of follow-up subtracter is still the output u of Park converter unit
q, therefore, still can ensure the normal tracking of phase-locked loop to electrical network phase place.
Have, the present invention does not adopt common voltage controlled oscillator again, and adopts local synchronization signal generation unit, generate mark signal frequently by crystal oscillator, then form the local synchronization signal of 50Hz by frequency division, therefore, phase-locked loop in the present invention is without Tracking Frequency of Power Grids, and only follows the tracks of phase place.
Adopt Matlab/Simulink to do l-G simulation test to three-phase digital phase-locked loop, simulation process can be found out the impact on phase-locked loop of electrical network under different conditions.Simulation results show local synchronization signal phase in the present invention can follow the tracks of fast three phase network phase place, have that reactance voltage falls and the impact of imbalance of three-phase voltage simultaneously.
Three-phase digital phase-locked loop structures provided by the present invention is simple, is easy to realize.This phase-locked loop can be transplanted in FPGA easily, forms devices at full hardware phase-locked loop; Also can be transplanted in DSP, form full software phase-lock loop.
Two of object of the present invention is achieved in that a kind of three-phase digital phase-lock technique, comprises the steps:
A, use Clark converter unit gather three phase network voltage u
a, u
b, u
cand carry out Clark conversion, obtain α axle component u under two-phase rest frame
αwith beta-axis component u
β;
B, receive the local synchronization signal phase θ being exported by trigonometric table memory with Park converter unit
0sine value and cosine value, and to α axle component u under two-phase rest frame
αwith beta-axis component u
βcarry out Park conversion, to obtain q axle component u under two-phase rotating coordinate system
q;
C, employing second order improper integral device are to described q axle component u
qcarry out filtering, export v ' after filtering, the centre frequency of described second order improper integral device is 100Hz;
D, make described q axle component u
qask difference with the output v ' of described second order improper integral device, obtain comprising three phase network phase theta and local synchronization signal phase θ
0the feedback information of difference Δ θ;
E, produced the local synchronization signal of 50 Hz by local synchronization signal generation unit;
F, local synchronization signal generation unit control trigonometric table memory within each cycle of local synchronization signal evenly output m group discrete, the sine value of local synchronization signal phase and cosine value be to the described Park converter unit in step b;
Feedback information described in g, use PI controller receiving step d; Within each cycle of local synchronization signal, corresponding m group three phase network phase theta and local synchronization signal phase θ
0phase difference θ, the phase place of the local synchronization signal that described PI controller produces local synchronization signal generation unit according to described feedback information carry out m time adjust.
Wherein, step e specifically comprises the steps:
E-1, by mark frequently maker produce the mark signal frequently of 50 × 4nm Hz;
E-2,4 frequency units carry out 4 frequency divisions to the mark frequency signal of described 50 × 4nm Hz, obtain the pulse signal of 50 × nm Hz;
E-3, n frequency unit carry out n frequency division to the pulse signal of described 50 × nm Hz, obtain the pulse signal of 50 × m Hz;
E-4, m frequency unit carry out m frequency division to the pulse signal of described 50 × m Hz, obtain the local synchronization signal of 50 Hz.
The phase place of the local synchronization signal that the controller of PI described in step g produces local synchronization signal generation unit according to described feedback information is adjusted, and is specially:
When | Δ θ | when≤δ, in step e-2, by 4 frequency units described in the control of described PI controller, the mark frequency signal of described 50 × 4nm Hz is carried out to 4 frequency divisions one time;
In the time of Δ θ > δ, in step e-2, by 4 frequency units described in the control of described PI controller, the mark frequency signal of described 50 × 4nm Hz is carried out to 3 frequency divisions one time;
In the time of Δ θ < ﹣ δ, in step e-2, by 4 frequency units described in the control of described PI controller, the mark frequency signal of described 50 × 4nm Hz is carried out to 5 frequency divisions one time;
Wherein, δ is a positive number of presetting.
Three-phase digital phase-lock technique provided by the present invention, adopts the output u of second order improper integral device to Park converter unit
qcarry out frequency-selective filtering, in the time that three phase network is uneven, can draw u by frequency-selective filtering
qmiddle superposeed second harmonic sin2 ω t, makes the output u of Park converter unit afterwards
qdeduct the second harmonic sin2 ω t obtaining by frequency-selective filtering, thereby can eliminate the interference of second harmonic in negative sequence component; The local synchronization signal that is produced 50Hz by local synchronization signal generation unit, PI controller is according to three phase network phase theta and local synchronization signal phase θ
0phase difference θ the phase place of local synchronization signal is adjusted, thereby can realize the tracking to three phase network phase place.
Three-phase digital phase-lock technique provided by the present invention both can have been followed the tracks of electrical network phase place in the time of three-phase grid balance, also can in the time that three phase network is uneven, follow the tracks of electrical network phase place.It is simple, effective that the method is compared the method generally using now and studying, and also has in other respects good performance simultaneously.As reactance voltage falls or in the time that three phase network is uneven, all has the function of following the tracks of electrical network positive sequence fundamental voltage phase place.
Brief description of the drawings
Fig. 1 is the structured flowchart of three-phase digital phase-locked loop in the present invention.
Fig. 2 is the structured flowchart of second order improper integral device in Fig. 1.
Fig. 3 is the Bode diagram of second order improper integral device in the present invention.
Fig. 4 is the sequential logic state diagram of achievable 4 frequency divisions of 4 frequency units, 3 frequency divisions and 5 frequency divisions in the present invention.
Fig. 5 is 1. middle three-phase equilibrium voltage oscillogram of l-G simulation test of the present invention.
Fig. 6 is the 1. output u of middle Park converter unit of l-G simulation test of the present invention
qwaveform.
Fig. 7 be l-G simulation test of the present invention 1. in the oscillogram of relation between three phase network phase place and local synchronization signal phase.
Fig. 8 is 2. middle three-phase imbalance voltage oscillogram of l-G simulation test of the present invention.
Fig. 9 is the 2. output u of middle Park converter unit of l-G simulation test of the present invention
qwaveform.
Figure 10 be l-G simulation test of the present invention 2. in the oscillogram of relation between three phase network phase place and local synchronization signal phase.
Figure 11 is the 3. output u of middle Park converter unit of l-G simulation test of the present invention
qwaveform.
Figure 12 be l-G simulation test of the present invention 3. in the oscillogram of relation between three phase network phase place and local synchronization signal phase.
Figure 13 is the 4. oscillogram of middle three phase network SPA sudden phase anomalies of l-G simulation test of the present invention.
Figure 14 is the 4. output u of middle Park converter unit of l-G simulation test of the present invention
qwaveform.
Figure 15 be l-G simulation test of the present invention 4. in the oscillogram of relation between three phase network phase place and local synchronization signal phase.
Figure 16 is the oscillogram that five positive sequence harmonics appear in 5. in three phase network in l-G simulation test of the present invention.
Figure 17 is the 5. output u of middle Park converter unit of l-G simulation test of the present invention
qwaveform.
Figure 18 be l-G simulation test of the present invention 5. in the oscillogram of relation between three phase network phase place and local synchronization signal phase.
Embodiment
Embodiment 1: a kind of three-phase digital phase-locked loop.
As shown in Figure 1, three-phase digital phase-locked loop provided by the present invention comprises Clark converter unit 1, Park converter unit 2, second order improper integral device (Second Order Generalized Integra, SOGI) 3, subtracter 4, PI controller 5, local synchronization signal generation unit 6 and trigonometric table memory 7.
Clark converter unit 1 joins with Park converter unit 2, and Clark converter unit 1 gathers three phase network voltage u
a, u
b, u
c, voltage u
acorresponding phase place is θ (θ=ω t), voltage u
bcorresponding phase place is (θ-120 °), voltage u
ccorresponding phase place is (θ+120 °), and it is the rotating vector that V, angular frequency are ω that the equivalence of three phase network voltage synthesizes an amplitude.The three phase network voltage u that Clark converter unit 1 represents plane abc tri-axles
a, u
b, u
ccarry out Clark conversion, to obtain α axle component u under two-phase rest frame
αwith beta-axis component u
β.
Park converter unit 2 receives the α axle component u that Clark converter unit 1 is exported on the one hand
αwith beta-axis component u
β; Receive on the other hand the local synchronization signal phase θ that trigonometric table memory 7 is exported
0sine value sin θ
0with cosine value cos θ
0.Trigonometric table memory 7 is under the control of local synchronization signal generation unit 6, in the one-period (0.02s) of local synchronization signal (50Hz), evenly output m organizes sine value and the cosine value of local synchronization signal phases discrete, different angles, and m is nature positive integer.For example, if m is 20, the one-period of local synchronization signal is 0.02s, i.e. 360 ° of the one-periods of corresponding phase; 360 ° by 20 deciles, 18 ° every part; 0.02s is by 20 deciles, every part of 1ms; Therefore, trigonometric table memory 7 is since 0 °, at interval of 1ms, evenly exports sine value and the cosine value of 20 groups of local synchronization signal phases discrete, different angles.
Trigonometric table memory 7 in one-period, export m group discrete, the sine value of the local synchronization signal phases of different angles and cosine value be to Park converter unit 2, Park converter unit 2 is to α axle component u under two-phase rest frame
αwith beta-axis component u
βcarry out Park conversion, to obtain q axle component u under two-phase rotating coordinate system
qwith d axle component u
d(u
ddo not consider in the present invention).Anglec of rotation frequency under rotating coordinate system is local synchronization signal angular frequency
0, ω
0=θ
0t, θ
0for local synchronization signal phase.No matter how coordinate changes, and amplitude V and the angular frequency of three phase network voltage rotating vector can not change, and only coordinate form is different with expression mode.
Park converter unit 2 is exported q axle component u
q, θ is three phase network phase place.As θ-θ
0, represent local phase place locking at=0 o'clock.If there is negative sequence component in three phase network voltage, the u that Park converter unit 2 is exported
qin will occur that second harmonic sin2 ω t disturbs, this disturbs and can strengthen the phase error after phase place locking, so that exceed permissible error (1.44 °) scope.
The interference causing in order to eliminate second harmonic sin2 ω t, the present invention makes the output u of Park converter unit 2
qthrough second order improper integral device 3, second order improper integral device 3 is by the output u of Park converter unit 2
qas input v, and export v '.As shown in Figure 2, there is shown second order improper integral device 3 and comprise adder, amplifier, multiplier sum-product intergrator, second order improper integral device 3 can be realized by hardware completely.The feature of second order improper integral device 3 is: one, it is the narrow band filter with selecting frequency characteristic, be ω ' with logical central angle frequency, central angle frequency is by input signal ω ' control, and ω ' is a constant, in the present invention, ω ' is 200 π, i.e. corresponding centre frequency 100Hz; Two, it is output as the orthogonal signalling that v ' and qv ' (qv ' do not consider in the present invention) two-way angular frequency are ω '; Three, according to the Bode diagram of Fig. 3 second order improper integral device, from figure, amplitude-frequency characteristic can find out that SOGI diagonal frequencies is the signal zero decay of ω ', diagonal frequencies is that other harmonic signal of ω ' has compared with high attenuation, from figure phase-frequency characteristic can find out SOGI diagonal frequencies be the signal of ω ' without phase shift, other harmonic signal phase shift that diagonal frequencies is ω ' approaches 90 °.Based on the These characteristics of second order improper integral device, therefore, u
qas the input v of second order improper integral device 3, ω ' is 200 π, and in the time that three phase network is uneven, the output v ' of second order improper integral device 3 is u
qthe second harmonic sin2 ω t of middle homophase; And in the time of three-phase grid balance, the output v ' of second order improper integral device 3 is zero output.
The output of the output of Park converter unit 2 and second order improper integral device 3 all connects subtracter 4, makes the output u of Park converter unit 2 in the interior realization of subtracter 4
qsubtract each other the interference being caused by the second harmonic sin2 ω t in same negative sequence component frequently can eliminate three phase network imbalance time with the output v ' of second order improper integral device 3.U
qthe difference of subtracting each other with v ' is sin(θ-θ
0), wherein, θ is three phase network phase place, θ
0for local synchronization signal phase.
In Fig. 1, illustrate by independent subtracter 4 and realized u
qsubtract each other with v ', and the output of subtracter 4 is connected to the input of PI controller 5; Another kind of execution mode is: do not adopt independent subtracter 4, but make the ε of second order improper integral device 3 inside
vinput direct and PI controller 5 is joined, because the ε of second order improper integral device 3 inside
vbe that v(is u
q) with the difference of v '.
PI controller 5 is sent in the output of subtracter 4, and PI controller 5 is to received sin(θ-θ
0) amplify, the computing such as integration obtains phase difference θ signal, Δ θ=θ-θ
0, at Δ θ hour, think Δ θ and sin(θ-θ
0) equate, in the present invention, just think Δ θ and sin(θ-θ
0) equate, lower same, repeat no more; PI controller 5 regulates and controls 4 frequency units 62 in local synchronization signal generation unit 6 according to phase difference θ signal, so that the phase place of local synchronization signal is adjusted, makes phase place and the three phase network Phase synchronization of local synchronization signal.
Local synchronization signal generation unit 6 comprises mark maker 61,4 frequency units 62, n frequency unit 63 and m frequency unit 64 frequently, and n, m are nature positive integer; Such as n can be 200,300,400 etc., and m can be 20,30,40 etc.Mark frequently maker 61 can be realized by crystal oscillator, and its mark for generation of 50 × 4nm Hz is pulse signal (or claiming mark signal frequently) frequently.4 frequency units 62 join with mark frequency maker 61 on the one hand, carry out successional 4 frequency divisions, to obtain the pulse signal of 50 × nm Hz for the mark frequency signal to 50 × 4nm Hz; Join with PI controller 5 on the other hand, under the control of PI controller 5, within each cycle of local synchronization signal (0.02s), mark to 50 × 4nm Hz frequently signal in carrying out the process of continuity 4 frequency divisions, realize the adjustment of m discreteness, the result of adjusting is each time that the mark frequency signal of 50 × 4nm Hz is carried out to 4 frequency divisions, 3 frequency divisions or 5 frequency divisions one time.In one cycle, carry out m time and adjust, m time of this place with 7 one cycles of trigonometric table memory in the m that exports organize the sin θ of different angles
0with cos θ
0corresponding, that is to say, export one group of sin θ in a certain moment of trigonometric table memory 7
0with cos θ
0after, then export u by Park converter unit 2
q, u
qobtain sin(θ-θ by second order improper integral device 3, subtracter 4
0), then control 4 frequency units 62 by PI controller 5 and once adjust.
4 frequency units 62 in the present invention are a sequential logical circuit that can complete 4 frequency divisions, 3 frequency divisions and 5 frequency divisions in fact, and it can be realized by adding/subtract door.With reference to figure 4, in Fig. 4, show respectively the sequential logic state diagram of 4 frequency divisions, 3 frequency divisions and 5 frequency divisions.
In conjunction with Fig. 4, PI controller 5 is controlled 4 frequency units 62 and is entered horizontal phasing control in fact by deducting divided pulse or adding divided pulse and realize, and is specially: when | Δ θ | (Δ θ=θ-θ when≤δ
0δ is a positive number of presetting, for example, be 0.1 or 0.2 etc.), think the locking of local synchronization signal phase, now PI controller 5 does not does not regulate and control, in other words PI controller 5 control 4 frequency units 62 to the mark of 50 × 4nm Hz frequently signal carry out 4 frequency divisions (still carrying out 4 frequency divisions); In the time of Δ θ > δ, represent local synchronization signal phase θ
0lag behind, now control 4 frequency units 62 by PI controller 5 the mark frequency signal of 50 × 4nm Hz is carried out to 3 frequency divisions one time, make local synchronization signal phase θ
0move forward a burst length, carry out 3 frequency divisions of a discreteness; In the time of Δ θ < ﹣ δ, represent local synchronization signal phase θ
0in advance, now control 4 frequency units 62 by PI controller 5 the mark frequency signal of 50 × 4nm Hz is carried out to 5 frequency divisions one time, make local synchronization signal phase θ
0after move a burst length, carry out 5 frequency divisions of a discreteness.It should be noted that, this is in the adjustment of carrying out m discreteness in the cycle, and the impact that the frequency of final formed local synchronization signal is caused can be ignored, and still, but can make the phase place of local synchronization signal change.
4 frequency divisions described in the present invention can be realized by a quaternary cycle counter, quaternary cycle counter starts counting by zero, after counting reaches one-period, exports a pulse signal, and zero clearing afterwards continues counting, continue output pulse signal, thereby realize 4 frequency divisions.All the same with the principle of 4 frequency divisions for other 3 frequency divisions, 5 frequency divisions, n frequency division and m frequency division, no longer describe in detail.
The pulse signal of 50 × nm Hz that 4 frequency units 62 are exported, after n frequency unit carries out n frequency division, obtains the pulse signal of 50 × m Hz; The pulse signal of 50 × m Hz carries out m frequency division by m frequency unit again, and obtaining phase place is θ
0, frequency is the local synchronization signal of 50 Hz.
Trigonometric table memory 7 can be ROM(Read-Only Memory, read-only memory), in trigonometric table memory 7, be provided with at least m memory cell, each memory cell contains sine value and the cosine value of the local synchronization signal phase of same angle.Trigonometric table memory 7 is under the control of m frequency unit 64, within each cycle of local synchronization signal (0.02s), sequentially from m memory cell, extract corresponding data and export to Park converter unit 2, trigonometric table memory 7 is at interval of one group of data of (0.02/m) second output, the 360 °/m of phase phasic difference of local synchronization signal corresponding to adjacent output data.For example, if m is 20, m frequency unit 64 is vicenary cycle counter, and 5 address wires of vicenary cycle counter output are to trigonometric table memory 7, and trigonometric table memory 7 adopts these 5 address wires to locate 20 memory cell of its inside.The one-period of local synchronization signal is 0.02s, i.e. 360 ° of the one-periods of corresponding phase; M is 20 o'clock, and 360 ° by 20 deciles, 18 ° every part, therefore since 0 °, is stored in respectively in 20 memory cell at interval of sine value and the cosine value of the local synchronization signal phases of 18 °.0.02s is by 20 deciles, every part of 1ms; Vicenary cycle counter control trigonometric table memory 7, since 0 °, at interval of 1ms, is exported sine value and the cosine value of one group of local synchronization signal phase, 18 ° of the phase phasic differences of the local synchronization signal of adjacent output correspondence.
Adopt Matlab/Simulink to do l-G simulation test to the three-phase digital phase-locked loop in the present invention, simulation process can be found out the impact on phase-locked loop of electrical network under different conditions.Simulation results show local synchronization signal phase in the present invention can follow the tracks of fast three phase network phase place, there is reactance voltage simultaneously and fall and the impact of imbalance of three-phase voltage.Each l-G simulation test is specific as follows:
L-G simulation test 1.
Under three phase network balance of voltage condition, make three phase network phase place and local synchronization signal phase differ 90 °, adopt the three-phase digital phase-locked loop in the present invention to carry out phase-locked to it, l-G simulation test acquired results is shown in Fig. 5 ~ Fig. 7, Fig. 5 shows three-phase equilibrium voltage oscillogram, and Fig. 6 shows the output u of Park converter unit
qwaveform, Fig. 7 shows the oscillogram of relation between three phase network phase place and local synchronization signal phase.Can be found out by Fig. 5 ~ Fig. 7, at the three phase network balance of voltage, and three phase network phase place and local synchronization signal phase differ in the situation of 90 °, adopt three-phase digital phase-locked loop in the present invention to complete about 0.09s greatly phase-locked, and phase error is within allowed band.
L-G simulation test 2.
Under three phase network Voltage unbalance condition, after 0.1s, make voltage u
band u
call fall 50%, adopt the three-phase digital phase-locked loop that does not add second order improper integral device to carry out it phase-locked, l-G simulation test acquired results is shown in Fig. 8 ~ Figure 10, and Fig. 8 shows three-phase imbalance voltage oscillogram, and Fig. 9 shows the output u of Park converter unit
qwaveform, Figure 10 shows the oscillogram of relation between three phase network phase place and local synchronization signal phase.Can be found out by Fig. 8 ~ Figure 10, in the time that uneven situation appears in three phase network voltage, it will affect the output u of Park converter unit
q, in the situation that not adding second order improper integral device, phase difference is greater than 7 °, exceeds permissible error scope.
L-G simulation test 3.
Under three phase network Voltage unbalance condition, after 0.1s, make voltage u
band u
call fall 50%, the three-phase digital phase-locked loop in employing the present invention carries out phase-locked to it, and l-G simulation test acquired results is shown in Fig. 8, Figure 11 and Figure 12, and Fig. 8 shows three-phase imbalance voltage oscillogram, and Figure 11 shows the output u of Park converter unit
qwaveform, Figure 12 shows the oscillogram of relation between three phase network phase place and local synchronization signal phase.Can be found out by Fig. 8, Figure 11 and Figure 12, in the time that uneven situation appears in three phase network voltage, it will affect the output u of Park converter unit
q, in phase-locked loop, adding after second order improper integral device, phase error is within allowed band.
L-G simulation test 4.
After 0.1s, make 90 ° of three phase network SPA sudden phase anomalies, adopt the three-phase digital phase-locked loop in the present invention to carry out phase-locked to it, l-G simulation test acquired results is shown in Figure 13 ~ Figure 15, and Figure 13 shows the oscillogram of three phase network SPA sudden phase anomalies, and Figure 14 shows the output u of Park converter unit
qwaveform, Figure 15 shows the oscillogram of relation between three phase network phase place and local synchronization signal phase.Can be found out by Figure 13 ~ Figure 15, after 0.1s, 90 ° of three phase network SPA sudden phase anomalies in the situation that, adopt the three-phase digital phase-locked loop in the present invention after 0.17s, can be locked by local synchronization signal phase greatly.
L-G simulation test 5.
After 0.1s, there is positive sequence harmonic 5 times, and 5 positive sequence harmonic amplitudes are 5% of fundamental voltage amplitudes, adopt the three-phase digital phase-locked loop in the present invention to carry out phase-locked to it, l-G simulation test acquired results is shown in Figure 16 ~ Figure 18, Figure 16 shows the oscillogram that occurs five positive sequence harmonics in three phase network, and Figure 17 shows the output u of Park converter unit
qwaveform, Figure 18 shows the oscillogram of relation between three phase network phase place and local synchronization signal phase.Can be found out by Figure 16 ~ Figure 18, occur after 5 positive sequence harmonics, and harmonic amplitude is fundamental voltage amplitude 5% time, phase-locked output is had to impact, but still can locking phase, phase error is within allowed band.If harmonic amplitude exceed fundamental voltage amplitude 5% after, phase-locked error will increase gradually.
Embodiment 2, a kind of three-phase digital phase-lock technique.
With reference to figure 1, three-phase digital phase-lock technique provided by the present invention comprises the steps:
A, Clark converter unit 1 gather three phase network voltage u
a, u
b, u
cand carry out Clark conversion, obtain α axle component u under two-phase rest frame
αwith beta-axis component u
β.
B, Park converter unit 2 receive the local synchronization signal phase θ being exported by trigonometric table memory 7
0sine value and cosine value, and to α axle component u under two-phase rest frame
αwith beta-axis component u
βcarry out Park conversion, to obtain q axle component u under two-phase rotating coordinate system
q.
Trigonometric table memory 7 in one-period, export m group discrete, the sine value of the local synchronization signal phases of different angles and cosine value be to Park converter unit 2, Park converter unit 2 is to α axle component u under two-phase rest frame
αwith beta-axis component u
βcarry out Park conversion, to obtain q axle component u under two-phase rotating coordinate system
qwith d axle component u
d(u
ddo not consider in the present invention).Anglec of rotation frequency under rotating coordinate system is local synchronization signal angular frequency
0, ω
0=θ
0t, θ
0for local synchronization signal phase.
In the time there is negative sequence component in three phase network voltage, the u that Park converter unit 2 is exported
qin will occur that second harmonic sin2 ω t disturbs, this disturbs and can strengthen the phase error after phase place locking.
C, employing second order improper integral device 3 are to q axle component u
qcarry out filtering, export v ' after filtering, the centre frequency of second order improper integral device 3 is 100Hz.
As shown in Figure 2, second order improper integral device 3 comprises adder, amplifier, multiplier sum-product intergrator, and second order improper integral device 3 can be realized by hardware completely; Being characterized in: one, it is the narrow band filter with selecting frequency characteristic, is ω ' with logical central angle frequency, and central angle frequency is by input signal ω ' control, and ω ' is a constant, and in the present invention, ω ' is 200 π, i.e. corresponding centre frequency 100Hz; Two, it is output as the orthogonal signalling that v ' and qv ' (qv ' do not consider in the present invention) two-way angular frequency are ω '; Three, according to the Bode diagram of Fig. 3 second order improper integral device, from figure, amplitude-frequency characteristic can find out that SOGI diagonal frequencies is the signal zero decay of ω ', diagonal frequencies is that other harmonic signal of ω ' has compared with high attenuation, from figure phase-frequency characteristic can find out SOGI diagonal frequencies be the signal of ω ' without phase shift, other harmonic signal phase shift that diagonal frequencies is ω ' approaches 90 °.Based on the These characteristics of second order improper integral device, therefore, u
qfiltered after second order improper integral device 3, in the time that three phase network is uneven, the output v ' of second order improper integral device 3 is u
qthe second harmonic sin2 ω t of middle homophase.
D, make q axle component u
qask difference with the output v ' of second order improper integral device 3, obtain comprising three phase network phase theta and local synchronization signal phase θ
0the feedback information of difference Δ θ.
Can eliminate because of the interference with second harmonic sin2 ω t causes in frequency negative sequence component by this step.
Certainly gained q axle component u in this step,
qpoor with v ', also can be directly by the ε of second order improper integral device 3 inside
vdraw, because the ε of second order improper integral device 3 inside
vbe that v(is u
q) with the difference of v '.
E, produced the local synchronization signal of 50 Hz by local synchronization signal generation unit 6.
Concrete steps are as follows:
E-1, produced the mark pulse signal frequently of 50 × 4nm Hz by crystal oscillator, n and m are nature positive integer.
E-2,4 frequency units 62 carry out successional 4 frequency divisions to the mark frequency pulse signal of 50 × 4nm Hz, obtain the pulse signal of 50 × nm Hz.
E-3, n frequency unit 63 carry out successional n frequency division to the pulse signal of 50 × nm Hz, obtain the pulse signal of 50 × m Hz.N can be 200,300,400 etc.
E-4, m frequency unit 64 carry out successional m frequency division to the pulse signal of 50 × m Hz, obtain the local synchronization signal of 50 Hz.M can be 20,30,40 etc.
F, local synchronization signal generation unit 6 control trigonometric table memory 7 within each cycle of local synchronization signal evenly output m group discrete, the sine value of local synchronization signal phase and cosine value be to the Park converter unit 2 in step b.
M frequency unit 64 in local synchronization signal generation unit 6 is the cycle counter of m system in fact, and m frequency unit 64 is output as the address wire of trigonometric table memory 7.M frequency unit 64 control trigonometric table memory 7 in one-period (0.02s), export m group discrete, sine value and the cosine value of the local synchronization signal phases of different angles, the 360 °/m of phase phasic difference of the local synchronization signal of adjacent output correspondence.
Feedback information in g, PI controller 5 receiving step d; Within each cycle of local synchronization signal, corresponding m group three phase network phase theta and local synchronization signal phase θ
0phase difference θ, the phase place of the local synchronization signal that PI controller 5 produces local synchronization signal generation unit 6 according to feedback information carry out m time adjust.
PI controller 5 is for each received feedback information sin(θ-θ
0), draw phase difference θ signal by computing, control 4 frequency units 62 according to Δ θ local synchronization signal phase is once adjusted.In one-period (0.02s), trigonometric table memory 7 is exported sine value and the cosine value of m group local synchronization signal phase, and Park converter unit 2 is exported u m time
q, PI controller 5 receives feedback information m time, thereby control 4 frequency units 62, local synchronization signal phase is carried out to m adjustment.For adjusting each time, be 4 frequency divisions, 3 frequency divisions or 5 frequency divisions that the mark frequency pulse signal of 50 × 4nm Hz carried out to a discreteness in fact.Concrete adjustment process is: when | Δ θ | (Δ θ=θ-θ when≤δ
0, δ is a positive number of presetting), think local synchronization signal phase locking, now PI controller 5 does not does not regulate and control, in other words PI controller 5 control 4 frequency units 62 to the mark of 50 × 4nm Hz frequently pulse signal carry out 4 frequency divisions one time; In the time of Δ θ > δ, represent local synchronization signal phase θ
0lag behind, now control 4 frequency units 62 by PI controller 5 the mark frequency pulse signal of 50 × 4nm Hz is carried out to 3 frequency divisions one time, make local synchronization signal phase θ
0move forward a burst length, carry out 3 frequency divisions of a discreteness; In the time of Δ θ < ﹣ δ, represent local synchronization signal phase θ
0in advance, now control 4 frequency units 62 by PI controller 5 the mark frequency pulse signal of 50 × 4nm Hz is carried out to 5 frequency divisions one time, make local synchronization signal phase θ
0after move a burst length, carry out 5 frequency divisions of a discreteness.
Claims (6)
1. a three-phase digital phase-locked loop, is characterized in that, comprising:
Clark converter unit, joins with Park converter unit, for gathering three phase network voltage u
a, u
b, u
cand carry out Clark conversion to obtain α axle component u under two-phase rest frame
αwith beta-axis component u
β;
Park converter unit, joins with described Clark converter unit, trigonometric table memory, second order improper integral device and subtracter respectively, for receiving the local synchronization signal phase θ being exported by trigonometric table memory
0sine value and cosine value, and to α axle component u under two-phase rest frame
αwith beta-axis component u
βcarry out Park conversion to obtain q axle component u under two-phase rotating coordinate system
q;
Second order improper integral device, joins with described Park converter unit and subtracter respectively, for by the output u of described Park converter unit
qas input v, and export v ' to subtracter; The centre frequency of described second order improper integral device is 100Hz;
Subtracter, joins with described Park converter unit, described second order improper integral device and PI controller respectively, for making the output u of described Park converter unit
qask difference with the output v ' of described second order improper integral device, to obtain comprising three phase network phase theta and local synchronization signal phase θ
0the feedback information of difference Δ θ;
PI controller, joins with described subtracter and local synchronization signal generation unit respectively, adjusts for local synchronization signal phase local synchronization signal generation unit being generated according to the feedback information of described subtracter output;
Local synchronization signal generation unit, join with described PI controller and trigonometric table memory, for generation of the local synchronization signal of 50Hz, and control trigonometric table memory even output m within each cycle of local synchronization signal and organize sine value and cosine value discrete, local synchronization signal phase, simultaneously under the control of described PI controller, within each cycle of local synchronization signal, the phase difference of corresponding m group three phase network phase place and local synchronization signal phase, carries out m time to the phase place of local synchronization signal and adjusts; M is nature positive integer; And
Trigonometric table memory, join with described local synchronization signal generation unit and described Park converter unit respectively, for under the control of described local synchronization signal generation unit, within each cycle of local synchronization signal, evenly output m organizes sine value and cosine value discrete, local synchronization signal phase.
2. three-phase digital phase-locked loop according to claim 1, is characterized in that, described local synchronization signal generation unit comprises:
Mark is maker frequently, joins, for generation of the mark signal frequently of 50 × 4nm Hz with 4 frequency units; N is nature positive integer;
4 frequency units, join with described PI controller, described mark frequency maker and n frequency unit respectively, carry out 4 frequency divisions, to obtain the pulse signal of 50 × nm Hz for the mark frequency signal to described 50 × 4nm Hz; Simultaneously, under the control of described PI controller, within each cycle of local synchronization signal, mark to described 50 × 4nm Hz frequently signal carry out realizing m adjustment in the process of 4 frequency divisions, the result of adjustment is that the mark frequency signal of described 50 × 4nm Hz is carried out to 4 frequency divisions, 3 frequency divisions or 5 frequency divisions one time each time;
N frequency unit, joins with described 4 frequency units and m frequency unit respectively, for the pulse signal of described 50 × nm Hz is carried out to n frequency division, to obtain the pulse signal of 50 × m Hz; And
M frequency unit, joins with described n frequency unit and described trigonometric table memory respectively, for the pulse signal of described 50 × m Hz is carried out to m frequency division, to obtain the local synchronization signal of 50 Hz; Meanwhile, control described trigonometric table memory even output m within each cycle of local synchronization signal and organize sine value and cosine value discrete, local synchronization signal phase.
3. three-phase digital phase-locked loop according to claim 2, is characterized in that, the process that 4 frequency units are adjusted the phase place of local synchronization signal described in the control of described PI controller is specially:
As | Δ θ | when≤δ, described in the control of described PI controller 4 frequency units to the mark of described 50 × 4nm Hz frequently signal carry out 4 frequency divisions one time;
In the time of Δ θ > δ, described in the control of described PI controller 4 frequency units to the mark of described 50 × 4nm Hz frequently signal carry out 3 frequency divisions one time;
In the time of Δ θ < ﹣ δ, described in the control of described PI controller 4 frequency units to the mark of described 50 × 4nm Hz frequently signal carry out 5 frequency divisions one time;
Wherein, δ is a positive number of presetting.
4. a three-phase digital phase-lock technique, is characterized in that, comprises the steps:
A, use Clark converter unit gather three phase network voltage u
a, u
b, u
cand carry out Clark conversion, obtain α axle component u under two-phase rest frame
αwith beta-axis component u
β;
B, receive the local synchronization signal phase θ being exported by trigonometric table memory with Park converter unit
0sine value and cosine value, and to α axle component u under two-phase rest frame
αwith beta-axis component u
βcarry out Park conversion, to obtain q axle component u under two-phase rotating coordinate system
q;
C, employing second order improper integral device are to described q axle component u
qcarry out filtering, export v ' after filtering, the centre frequency of described second order improper integral device is 100Hz;
D, make described q axle component u
qask difference with the output v ' of described second order improper integral device, obtain comprising three phase network phase theta and local synchronization signal phase θ
0the feedback information of difference Δ θ;
E, produced the local synchronization signal of 50 Hz by local synchronization signal generation unit;
F, local synchronization signal generation unit control trigonometric table memory within each cycle of local synchronization signal evenly output m group discrete, the sine value of local synchronization signal phase and cosine value be to the described Park converter unit in step b;
Feedback information described in g, use PI controller receiving step d; Within each cycle of local synchronization signal, corresponding m group three phase network phase theta and local synchronization signal phase θ
0phase difference θ, the phase place of the local synchronization signal that described PI controller produces local synchronization signal generation unit according to described feedback information carry out m time adjust.
5. three-phase digital phase-lock technique according to claim 4, is characterized in that, step e specifically comprises the steps:
E-1, by mark frequently maker produce the mark signal frequently of 50 × 4nm Hz;
E-2,4 frequency units carry out 4 frequency divisions to the mark frequency signal of described 50 × 4nm Hz, obtain the pulse signal of 50 × nm Hz;
E-3, n frequency unit carry out n frequency division to the pulse signal of described 50 × nm Hz, obtain the pulse signal of 50 × m Hz;
E-4, m frequency unit carry out m frequency division to the pulse signal of described 50 × m Hz, obtain the local synchronization signal of 50 Hz.
6. three-phase digital phase-lock technique according to claim 5, is characterized in that, the phase place of the local synchronization signal that the controller of PI described in step g produces local synchronization signal generation unit according to described feedback information is adjusted, and is specially:
When | Δ θ | when≤δ, in step e-2, by 4 frequency units described in the control of described PI controller, the mark frequency signal of described 50 × 4nm Hz is carried out to 4 frequency divisions one time;
In the time of Δ θ > δ, in step e-2, by 4 frequency units described in the control of described PI controller, the mark frequency signal of described 50 × 4nm Hz is carried out to 3 frequency divisions one time;
In the time of Δ θ < ﹣ δ, in step e-2, by 4 frequency units described in the control of described PI controller, the mark frequency signal of described 50 × 4nm Hz is carried out to 5 frequency divisions one time;
Wherein, δ is a positive number of presetting.
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