CN109659983B - Software phase-locked loop implementation method and device based on IDFT - Google Patents
Software phase-locked loop implementation method and device based on IDFT Download PDFInfo
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Abstract
The invention discloses a software phase-locked loop method and a software phase-locked loop device based on IDFT (inverse discrete Fourier transform). Voltage signals of a non-ideal three-phase system are sampled, and three-phase power grid voltage is converted from an abc static coordinate system to a clarkeαβUnder a static coordinate system, voltage is extracted through IDFTA fundamental positive sequence signal ofαβConverting the voltage signal under the static coordinate system into a dq synchronous rotating coordinate system through park; obtaining the angular frequency of a voltage fundamental wave positive sequence signal through a PI controller; the device comprises: the device comprises a sampling unit, a phase-locked loop unit, a closed-loop control unit, a sine pulse width modulation unit, a driving unit and an NPC three-level inverter. The method can filter harmonic components, negative sequence components and direct current components in the nonideal power grid voltage signal under a two-phase static coordinate system, and the phase-locked loop is simple in parameter design and high in phase-locked precision.
Description
Technical Field
The invention relates to the technical field of power electronic conversion, in particular to a software phase-locked loop implementation method and device based on IDFT.
Background
In new energy applications where synchronization to a reference signal is important, such as distributed generation, the grid-connected converter must typically be synchronized to the phase and frequency of the utility grid. A Phase Locked Loop-PLL (Phase Locked Loop-PLL) may be used to synchronize with the signal. For example, a Single Synchronous frame software Phase Lock Loop (SSRF-PLL) is a widely used PLL technique that can detect the Phase angle and frequency of a Reference signal. Under certain conditions, the SSRF-PLL can quickly and accurately detect the phase angle, fundamental frequency and amplitude of the reference signal. If the reference signal is distorted due to low order harmonics, the effect of these harmonics on the output can be suppressed and eliminated by reducing the bandwidth of the SSRF-PLL feedback element. However, in some cases, reducing the PLL bandwidth may be an unacceptable solution, since the response speed of the PLL may also be reduced accordingly. In addition, the imbalance of the reference signal also has an impact on the design based on the SSRF-PLL method.
At present, a decoupling Software Phase-Locked Loop (Decoupled Double synchronized sound Phase Locked Loop-DDSRF-PLL) based on a Double synchronous coordinate system and a Software Phase-Locked Loop (Double Second Generalized Integrator or Software Phase Locked Loop-DSOGI-SPLL) based on a Double Second-Order Generalized Integrator are improved Phase-Locked loops designed based on an SSRF-PLL, which are two most widely applied to a non-ideal power grid at present, but the two types of Phase-Locked loops are not ideal for low-Order harmonic filtering, and if the filtering effect of the Phase-Locked loops on low-Order harmonics is improved, the dynamic response time of the Phase-Locked loops will be prolonged. A Software Phase-Locked Loop (cascaded Delayed Signal Cancellation Software Phase Locked Loop-CDSC-SPLL) based on a cascaded Delayed Signal Cancellation method is used for filtering all harmonic components on the basis of an SSRF-PLL, and therefore voltage positive sequence components are extracted to lock the Phase and frequency of a fundamental wave of a power grid, but signals are discontinuous in a digital system, Delayed Signal errors cannot be avoided, errors can be reduced by adopting algorithms such as weighted average values and the like, but five-stage modules need to calculate respectively, and the calculation amount is large.
Disclosure of Invention
The invention aims to provide an IDFT (Inverse Discrete Fourier transform Software Phase Locked Loop) -IDFT-SPLL (Inverse Discrete Phase Locked Loop), which can accurately and quickly eliminate the influence of faults and relock the Phase angle and angular frequency of a power grid voltage signal when the power grid voltage has faults such as unbalance, harmonic distortion, frequency sudden change, Phase sudden change and the like.
The technical solution for realizing the purpose of the invention is as follows: a software phase-locked loop implementation method based on IDFT comprises the following specific steps:
s1 sampling voltage signal u of non-ideal three-phase systema、ub、ucConverting the signal into αβ voltage signal u in stationary coordinate system by using clark conversionα、uβ；
S2, detecting the working voltage frequency value through IDFT1-SPLL, the detecting steps are:
a、uα、uβextracting a quasi-voltage positive sequence signal u through IDFT1α′、uβ′；
b. Converting the quasi-voltage positive sequence signal u by parkα′、uβ' conversion to Voltage Signal u in synchronous rotating coordinate Systemd′、uq′；
c、uqThe angular frequency omega of the quasi-voltage positive sequence signal is obtained by a PI controllerf；
d、ωfB, obtaining a quasi-voltage positive sequence signal phase angle theta through an integration link, and feeding the quasi-voltage positive sequence signal phase angle theta back to the step b to perform park transformation to complete closed-loop phase locking;
e. the angular frequency omega of the obtained quasi-voltage positive sequence signalfAfter being filtered by a low-pass filter, the sampling number K of the power frequency period is obtained and transmitted to IDFT2 for realizing frequency self-adaptionFiltering should be applied.
S3, detecting the phase angle of the working voltage through IDFT2-SPLL, wherein the detection steps are as follows:
a、uα、uβextracting a voltage fundamental wave positive sequence signal u by IDFT2α +、uβ +；
b. Converting the voltage fundamental wave positive sequence signal u by parkα +、uβ +Converting the voltage signal u into a voltage signal u under a synchronous rotating coordinate systemd +、uq +；
c、uq +Working voltage angular frequency omega is obtained through a PI controllero；
d. Operating voltage angular frequency omegaoObtaining a voltage fundamental wave positive sequence signal phase angle theta through an integral linko。
e. The phase angle theta of a voltage fundamental wave positive sequence signaloThe park transform in step b fed back to S3 completes the closed loop phase locking.
Further, the voltage signal u of the non-ideal three-phase systema、ub、ucThe method comprises the following steps:
the voltage signal of the non-ideal three-phase system consists of a fundamental wave positive sequence component and a plurality of frequency components, and the functional expression is as follows:
in the formula of U1 +Voltage amplitude, U, being the positive sequence component of the fundamental wave of the mains voltagenVoltage amplitude, phi, being the nth harmonic of the mains voltage1And phinThe initial phase angle of the grid voltage fundamental wave positive sequence component and the initial phase angle of the grid voltage nth harmonic are respectively, and omega is the grid voltage frequency.
Further, the inverse finite discrete Fourier transform 1, namely IDFT1, extracts the voltage signal uα′、uβ', the details are as follows:
in the formula, N is the periodic sampling number of fundamental waves; j is a plurality;
the limited inverse discrete Fourier transform 2, namely IDFT2 extracts a power grid voltage signal uα +、uβ +The method comprises the following steps:
wherein K is the sampling number of the power frequency period, uαβ(n-k) represents the n-k period αβ axis input value.
Further, the angular frequency omega of the obtained quasi-voltage fundamental wave positive sequence signalfObtaining the voltage fundamental angular frequency omega through a low-pass filteroThe power frequency periodic sampling number K can be obtained through operation, and the specific expression is as follows
In the formula, ωoFor operating voltage angular frequency, TsIs the sampling period.
An IDFT-based software phase-locked loop implementation device comprises:
the NPC three-level inverter is used for accessing a power grid as a main circuit of the system;
the sampling unit is used for collecting voltage and current signals of a power grid;
the phase-locked loop unit is used for locking the power grid voltage acquired by the sampling unit;
the closed-loop control unit is used for generating a modulation signal by the power grid current acquired by the sampling unit and the theta generated by the phase-locked loop unit through a current closed-loop control algorithm;
the sine pulse width modulation unit is used for comparing the modulation signal with the triangular carrier and generating a corresponding pulse signal according to the modulation signal;
and the driving unit is used for converting the pulse signal into level and driving the circuit to operate.
Further, the phase-locked loop unit includes dual phase-locked loop structures IDFT1-SPLL and IDFT2-SPLL, wherein:
the frequency detection module IDFT1-SPLL is used for locking the frequency of the power grid;
and the phase detection module IDFT2-SPLL is used for locking the phase of the power grid.
Further, the closed-loop control unit includes:
a current signal conversion module for converting the three-phase current signal ia、ib、icTransforming the coordinate system into a synchronous rotating coordinate system i through clarke and parkd、iq；
PI control module for i in synchronous rotation coordinate systemd、iqThe difference between the signal and the given signal is fed into a PI controller to obtain a dq axis modulation signal id′、iq′。
A modulation signal generation module for generating id′、iq' obtaining a modulated signal u by ipark, iclarke transformationa′、ub′、uc′。
Compared with the prior art, the invention has the following beneficial effects:
(1) by adopting an IDFT structure, harmonic components, negative sequence components and direct current components in non-ideal power grid voltage signals can be completely filtered under an αβ static coordinate system;
(2) when the power grid voltage has faults of unbalance, harmonic distortion, frequency mutation, phase mutation and the like, the influence of the faults can be accurately and quickly eliminated, and the phase angle and the frequency of the power grid voltage signal can be locked again;
(3) IDFT is simplified through a formula, the calculated amount is simplified, and the digital implementation is easier.
Drawings
FIG. 1 is a schematic diagram of an IDFT-based software PLL of the present invention;
FIG. 2 shows the bode diagram of IDFT in the present invention, (a) shows the bode diagram of IDFT1, and (b) shows the bode diagram of IDFT 2;
FIG. 3 is a schematic representation of IDFT1-SPLL (a) and IDFT2-SPLL (b) in accordance with the present invention;
FIG. 4 is a simulated waveform diagram of a phase-locked loop when the grid voltage is unbalanced;
FIG. 5 is a simulated waveform diagram of a phase-locked loop when harmonics are added to the grid voltage;
FIG. 6 is a simulated waveform diagram of a phase-locked loop when the frequency of the grid voltage suddenly changes;
FIG. 7 is a simulated waveform diagram of a phase-locked loop when the phase of the grid voltage suddenly changes;
FIG. 8 is a simulated waveform diagram of a phase-locked loop when the grid voltage drops in three phases;
FIG. 9 is a simulated waveform diagram of a phase-locked loop during a single-phase ground fault;
FIG. 10 is a simulated waveform diagram of a phase-locked loop during a frequency jump with harmonic disturbance fault;
fig. 11 is a schematic structural diagram of an IDFT-based software pll implementation apparatus according to the present invention.
Detailed Description
The invention relates to an IDFT-based software phase-locked loop, which is characterized in that an IDFT1 is used for extracting a quasi-positive sequence signal from a non-ideal power grid voltage signal, the angular frequency of the quasi-positive sequence signal is obtained through a proportional-integral controller, the phase angle of the quasi-positive sequence signal is obtained through an integral link, the power frequency cycle sampling number K of a working voltage signal is obtained through numerical operation, the positive sequence signal from the non-ideal power grid voltage signal is extracted through an IDFT2, the angular frequency of the positive sequence signal is obtained through the proportional-integral controller, and the phase angle of the positive sequence signal is obtained through the integral link, and the method specifically comprises the following steps:
a software phase-locked loop implementation method based on IDFT comprises the following steps:
sampling voltage signal u of non-ideal three-phase systema、ub、ucConverting the signal into αβ voltage signal u in stationary coordinate system by using clark conversionα、uβ；
Detecting the working voltage frequency value through IDFT1-SPLL, wherein the detection steps are as follows:
a、uα、uβextracting a quasi-voltage positive sequence signal u through IDFT1α′、uβ′；
b. Converting the quasi-voltage positive sequence signal u by parkα′、uβ' turn toConverting to voltage signal u under synchronous rotating coordinate systemd′、uq′；
c、uqThe angular frequency omega of the quasi-voltage positive sequence signal is obtained by a PI controllerf；
d、ωfB, obtaining a quasi-voltage positive sequence signal phase angle theta through an integration link, and feeding the phase angle theta back to the step b for park transformation;
e. the angular frequency omega of the obtained quasi-voltage positive sequence signalfAnd after filtering by a low-pass filter, obtaining the power frequency period sampling number K, and transmitting the power frequency period sampling number K to IDFT2 for realizing frequency self-adaptive filtering.
Detecting the phase angle of the working voltage through IDFT2-SPLL, wherein the detection steps are as follows:
a、uα、uβextracting a voltage fundamental wave positive sequence signal u by IDFT2α +、uβ +；
b. Converting the voltage fundamental wave positive sequence signal u by parkα +、uβ +Converting the voltage signal u into a voltage signal u under a synchronous rotating coordinate systemd +、uq +；
c、uq +Working voltage angular frequency omega is obtained through a PI controllero；
d. Operating voltage angular frequency omegaoObtaining a voltage fundamental wave positive sequence signal phase angle theta through an integral linko。
e. The phase angle theta of a voltage fundamental wave positive sequence signaloAnd feeding back to the park conversion in the step b to complete closed-loop phase locking.
Further, the voltage signal u of the non-ideal three-phase systema、ub、ucThe method comprises the following steps:
the voltage signal of the non-ideal three-phase system consists of a fundamental wave positive sequence component and components of various frequencies, and the functional expression of the voltage signal is as follows:
in the formula of U1 +For electricity of the electric networkVoltage amplitude of the positive sequence component of the voltage fundamental wave, UnVoltage amplitude, phi, being the nth harmonic of the mains voltage1And phinThe initial phase angle of the grid voltage fundamental wave positive sequence component and the initial phase angle of the grid voltage nth harmonic are respectively, and omega is the grid voltage frequency.
Further, the finite inverse discrete Fourier transform 1, namely IDFT1 extracts a quasi-grid voltage fundamental wave positive sequence signal uα′、uβ', the details are as follows:
in the formula, N is the periodic sampling number of fundamental waves; j is a plurality;
the finite inverse discrete Fourier transform 2, namely IDFT2 extracts a grid voltage fundamental wave positive sequence signal uα +、uβ +The concrete formula is as follows:
wherein K is the sampling number of the power frequency period, uαβ(k) Representing the k-th period αβ axis input values.
Further, the angular frequency omega of the obtained quasi-voltage fundamental wave positive sequence signalfObtaining the angular frequency omega of the working voltage through a first-order digital low-pass filteroAnd calculating to obtain the power frequency cycle sampling number K:
in the formula, ωoFor operating voltage angular frequency, TsIs the sampling period. The low pass filter may also be of a higher order.
The invention also provides a software phase-locked loop implementation device based on the IDFT, referring to fig. 11, which includes:
the NPC three-level inverter is used for accessing a power grid as a main circuit of the system;
the sampling unit is used for collecting voltage and current signals of a power grid;
the phase-locked loop unit is used for locking the power grid voltage acquired by the sampling unit;
the closed-loop control unit is used for enabling the power grid current collected by the sampling unit and the theta generated by the phase-locked loop unit to pass through a current closed-loop control algorithm to generate a modulation signal;
the sine pulse width modulation unit is used for generating a corresponding pulse signal according to the comparison between the modulation signal and the triangular carrier;
and the driving unit is used for converting the pulse signal into level and driving the circuit to operate.
Further, the phase-locked loop unit includes:
the frequency detection module is used for locking the frequency of the power grid;
the phase detection module is used for locking the phase of the power grid;
further, the closed-loop control unit includes:
a current signal conversion module for converting three-phase current signals ia、ib、icTransforming the coordinate system into a synchronous rotating coordinate system i through clarke and parkd、iq；
PI control module for synchronously rotating i in coordinate systemd、iqThe difference between the signal and the given signal is fed into a PI controller to obtain a dq axis modulation signal id′、iq′。
Modulated signal generating module id′、iq' obtaining a modulated signal u by ipark, iclarke transformationa′、ub′、uc′。
The invention is described in further detail below with reference to the figures and the embodiments.
Example 1
The implementation method of the software phase-locked loop based on the IDFT comprises the following steps:
in the formula ua(n) is the phase voltage sampling signal of the phase A of the nth switching period, ub(n) is the B phase voltage sampling signal of the nth switching period, ucAnd (n) is the C phase voltage sampling signal of the nth switching period.
The IDFT1 transfer function is as follows:
in the formula uα(k) Representing the k-th period α axis input value, uβ(k) Representing the k-th period β axis input value, uα' (k) is the k-th period α axis output value, uβ' (k) is the k-th period β axis output value;
the IDFT2 transfer function is as follows:
wherein K is the sampling number of the power frequency period, uα(k) Representing the k-th period α axis input value, uβ(k) Representing the k-th period β axis input value, uα +(k) α Axis output value, u, for the k periodβ +(k) β axis output value for the k period;
step 3, mixing uα′(n)、uβ' (n) is converted into a synchronous rotating coordinate system through Park to obtain ud′(n)、uq' (n); will uα +(n)、uβ +(n) obtaining u by Park transformation under a synchronous rotating coordinate systemd +(n)、uq +(n), the conversion formula is as follows:
park transformation formula in IDFT 1:
park transformation formula in IDFT 2:
in the formula, thetaoTheta is the phase angle obtained in step 4, uα +(n)、uβ +(n) is the Park transform αβ axis input in IDFT1, uα′(n)、uβ' (n) is the Park transform αβ axis input in IDFT 2.
Step 5, the angular frequency omega of the quasi-fundamental wave positive sequence signal obtained in the step 4 is usedfObtaining the angular frequency omega of the working voltage after first-order digital filteringoAnd obtaining a power frequency period sampling number K through numerical operation, wherein the numerical operation formula is as follows:
in the formula, ωoFor operating voltage angular frequency, TsIs the sampling period.
The method includes the steps that PLECS is adopted to build a phase-locked loop simulation model, various parameters are shown in table 1, seven non-ideal power grid states are verified, wherein a power grid voltage drop is shown in fig. 4, an A phase drops to 90%, a B phase amplitude drops to 80%, a C phase amplitude drops to 60%, power grid voltage harmonic interference is shown in fig. 5, five negative sequence harmonics with the amplitude of 10% of fundamental wave amplitude, 10% seven positive sequence harmonics, 5% eleven negative sequence harmonics and 5% thirteen positive sequence harmonics are injected into power grid voltage, power grid voltage frequency sudden change is shown in fig. 6, angular frequency is changed from 50 × 2 pi rad/s to 45 × 2 pi rad/s, power grid voltage phase sudden change is shown in fig. 7, the phase sudden change is 0.1 pi rad, power grid voltage three-phase balanced simulation waveforms are shown in fig. 8, amplitude drops to 50%, an A phase full-drop simulation waveform is shown in fig. 9, fig. 10 is shown in fig. 5 and 6, superposition of conditions is shown in the fig. 5 and fig. DSOGI-SPLL is adopted for comparison, phase-SPFT simulation phase-SPLL is set, phase-SPLL parameters are set, ideal phase-SPLL parameters are set, ideal phase sudden change simulation results, ideal phase-SPFT harmonic simulation results are shown, and accurate harmonic distortion of SPOG harmonic disturbance resistance and SPOG harmonic disturbance can be better compared under the condition, SPOG.
TABLE 1
| Parameter(s) | Set value |
| Fundamental voltage amplitude U | 311V |
| Fundamental voltage angular frequency omega | 50×2πrad/s |
| Sampling period Ts | 5e-5s |
| Fundamental wave periodic |
400 |
| Fundamental wavePeriod Tω | 0.02s |
| PI controller kp,ki | 0.482、25.568 |
Claims (6)
1. A software phase-locked loop implementation method based on IDFT is characterized by comprising the following steps:
s1 sampling voltage signal u of non-ideal three-phase systema、ub、ucConversion of the signal to a voltage signal u in αβ stationary frame using a clark transformationα、uβ；
S2, detecting the working voltage frequency value through IDFT1-SPLL, the detecting steps are:
S21、uα、uβextracting a quasi-voltage fundamental wave positive sequence signal u through IDFT1α′、uβ′；
S22, converting the quasi-voltage fundamental wave positive sequence signal u through parkα′、uβ' conversion to Voltage Signal u in dq synchronous rotating coordinate Systemd′、uq′；
S23、uqThe angular frequency omega of the quasi-voltage fundamental wave positive sequence signal is obtained by a PI controllerf；
S24、ωfObtaining a quasi-voltage fundamental wave positive sequence signal phase angle theta through an integration link, and feeding the phase angle theta back to the step S22 for park transformation to complete closed-loop phase locking;
s25, obtaining the angular frequency omega of the quasi-voltage fundamental wave positive sequence signalfAfter filtering by a low-pass filter, calculating the sampling number K of a power frequency period, and transmitting the sampling number K to IDFT2 for realizing frequency self-adaptive filtering;
s3, detecting the phase angle of the working voltage through IDFT2-SPLL, wherein the detection steps are as follows:
S31、uα、uβextracting a voltage fundamental wave positive sequence signal u by IDFT2 in combination with the power frequency cycle sampling number Kα +、uβ +；
S32, converting the voltage fundamental wave positive sequence signal u through park conversionα +、uβ +Converting to voltage signal u under dq synchronous rotating coordinate systemd +、uq +；
S33、uq +Working voltage angular frequency omega is obtained through a PI controllero；
S34 operating voltage angular frequency omegaoObtaining a voltage fundamental wave positive sequence signal phase angle theta through an integral linkoAnd the feedback is made to step S32 for park conversion to complete the closed-loop phase locking.
2. The IDFT-based software phase-locked loop implementation method of claim 1, wherein the voltage signal u of the non-ideal three-phase systema、ub、ucThe frequency-variable filter consists of a fundamental wave positive-negative sequence component and a plurality of frequency components, and the functional expression is as follows:
in the formula of U1 +Voltage amplitude, U, being the positive sequence component of the fundamental wave of the mains voltagenVoltage amplitude, phi, being the nth harmonic of the mains voltage1And phinThe initial phase angle of the grid voltage fundamental wave positive sequence component and the initial phase angle of the grid voltage nth harmonic are respectively, and omega is the grid voltage fundamental wave angular frequency.
3. The IDFT-based software phase-locked loop implementation method of claim 1, wherein the software phase-locked loop implementation adopts a double phase-locked loop structure;
wherein the IDFT1 extracts a quasi-grid voltage fundamental wave positive sequence signal uα′、uβ', the specific expression is as follows:
in the formula, N is the periodic sampling number of fundamental waves; j is a plurality;
IDFT2 extracts grid voltage fundamental wave positive sequence signal uα +、uβ +The specific expression is as follows:
wherein K is the sampling number of the power frequency period, uαβ(k) Representing the k-th period αβ axis input values.
4. The IDFT-based software phase-locked loop implementation method of claim 1, wherein in step S25, the solving formula of the power frequency cycle sampling number K is as follows:
in the formula, ωoFor operating voltage angular frequency, TsIs the sampling period.
5. An apparatus for implementing a software phase-locked loop based on an IDFT (inverse discrete Fourier transform), comprising:
the NPC three-level inverter is used for accessing a power grid as a main circuit of the system;
the sampling unit is used for collecting voltage and current signals of a power grid;
the phase-locked loop unit is used for locking the power grid voltage acquired by the sampling unit;
the closed-loop control unit is used for generating a modulation signal by the power grid current acquired by the sampling unit and the theta generated by the phase-locked loop unit through a current closed-loop control algorithm;
the sine pulse width modulation unit is used for comparing the modulation signal with the triangular carrier to generate a corresponding pulse signal;
the driving unit is used for converting the pulse signal into level and driving the circuit to operate;
the phase-locked loop unit comprises a double phase-locked loop structure IDFT1-SPLL and IDFT2-SPLL, wherein the IDFT1-SPLL is used for detecting a power grid frequency signal, and the IDFT2-SPLL is used for detecting a power grid phase;
detecting the working voltage frequency value through IDFT1-SPLL, wherein the detection steps are as follows:
S21、uα、uβextracting a quasi-voltage fundamental wave positive sequence signal u through IDFT1α′、uβ′；
S22, converting the quasi-voltage fundamental wave positive sequence signal u through parkα′、uβ' conversion to Voltage Signal u in dq synchronous rotating coordinate Systemd′、uq′；
S23、uqThe angular frequency omega of the quasi-voltage fundamental wave positive sequence signal is obtained by a PI controllerf；
S24、ωfObtaining a quasi-voltage fundamental wave positive sequence signal phase angle theta through an integration link, and feeding the phase angle theta back to the step S22 for park transformation to complete closed-loop phase locking;
s25, obtaining the angular frequency omega of the quasi-voltage fundamental wave positive sequence signalfAfter filtering by a low-pass filter, calculating the sampling number K of a power frequency period, and transmitting the sampling number K to IDFT2 for realizing frequency self-adaptive filtering;
detecting the phase angle of the working voltage through IDFT2-SPLL, wherein the detection steps are as follows:
S31、uα、uβextracting a voltage fundamental wave positive sequence signal u by IDFT2 in combination with the power frequency cycle sampling number Kα +、uβ +；
S32, converting the voltage fundamental wave positive sequence signal u through park conversionα +、uβ +Converting to voltage signal u under dq synchronous rotating coordinate systemd +、uq +；
S33、uq +Working voltage angular frequency omega is obtained through a PI controllero；
S34 operating voltage angular frequency omegaoObtaining a voltage fundamental wave positive sequence signal phase angle theta through an integral linkoAnd the feedback is made to step S32 for park conversion to complete the closed-loop phase locking.
6. The IDFT-based software phase-locked loop implementation device of claim 5, wherein the closed-loop control unit comprises:
a current signal conversion module for converting the three-phase current signal ia、ib、icTransforming the coordinate system into a synchronous rotating coordinate system i through clarke and parkd、iq；
PI control module for i in synchronous rotation coordinate systemd、iqThe difference between the signal and the target current enters a PI controller to obtain a dq axis modulation signal id′、iq′；
A modulation signal generation module for generating id′、iq' obtaining a modulated signal u by ipark, iclarke transformationa′、ub′、uc′。
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| CN102761281B (en) * | 2011-04-28 | 2015-01-21 | 特变电工新疆新能源股份有限公司 | Phase-locked control system for inverter and phase locking method thereof |
| CN104022668A (en) * | 2014-05-30 | 2014-09-03 | 江苏大学 | Three-phase NPC grid-connected inverter based on quasi-proportional resonance control |
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