CN109659983A - Software phase-lock loop implementation method and device based on IDFT - Google Patents
Software phase-lock loop implementation method and device based on IDFT Download PDFInfo
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Classifications
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02J—CIRCUIT ARRANGEMENTS OR SYSTEMS FOR SUPPLYING OR DISTRIBUTING ELECTRIC POWER; SYSTEMS FOR STORING ELECTRIC ENERGY
- H02J3/00—Circuit arrangements for ac mains or ac distribution networks
- H02J3/38—Arrangements for parallely feeding a single network by two or more generators, converters or transformers
- H02J3/40—Synchronising a generator for connection to a network or to another generator
- H02J3/44—Synchronising a generator for connection to a network or to another generator with means for ensuring correct phase sequence
Abstract
The software phase-lock loop method and device based on IDFT that the invention discloses a kind of, samples the voltage signal of non-ideal three-phase system, and three-phase power grid voltage is turned to transform to through clarke by abc rest frameαβUnder rest frame, voltage fundamental positive-sequence signals are extracted through IDFT, it willαβVoltage signal under rest frame is converted under dq synchronous rotating frame through park；Voltage fundamental positive-sequence signals angular frequency is obtained through PI controller；Device includes: sampling unit, phase locked-loop unit, Closed Loop Control Unit, sinusoidal pulse width modulation unit, driving unit, NPC three-level inverter.The method of the present invention can filter out harmonic component, negative sequence component and DC component in non-ideal mains voltage signal under two-phase stationary coordinate system, and pll parameter design is simple, and locking phase precision is high.
Description
Technical field
The present invention relates to Technics of Power Electronic Conversion technical field, especially a kind of software phase-lock loop implementation method based on IDFT
And device.
Background technique
Synchronize it is critically important with reference signal, such as in distributed power generation in field of new energy applications, connects power grid
Converter generally have to it is synchronous with the phase and frequency of utility network.Phaselocked loop (Phase Locked Loop-PLL) can be with
For synchronous with signal.For example, single synchronous coordinate system software phase-lock loop (Single Synchronous Reference Frame
Software Phase Lock Loop-SSRF-PLL) it is widely used PLL technology, it is able to detect the phase of reference signal
Angle and frequency.Under certain condition, SSRF-PLL can phase angle, fundamental frequency and width quick and that accurately detect reference signal
Value.If reference signal is distorted due to low-order harmonic, can by reduce SSRF-PLL feedback element bandwidth inhibit and
Eliminate influence of these harmonic waves to output.However in some cases, because therefore the response speed of PLL can also reduce, so
Reducing PLL bandwidth may be unacceptable solution.In addition, the uneven of reference signal also can be to based on the side SSRF-PLL
The design of method has an impact.
Currently, decoupling software phase-lock loop (the Decoupled Double Synchronous based on double synchronous coordinate systems
Reference Frame Software Phase Locked Loop-DDSRF-PLL), based on double Second Order Generalized Integrators
Software phase-lock loop (Double Second Order Generalized Integrator Software Phase Locked
Loop-DSOGI-SPLL), it is the improvement phaselocked loop that designs based on SSRF-PLL, is to be applied to non-ideal power grid the most at present
Extensive two kinds of software phase-lock loops, but both phaselocked loops are less desirable to low-order harmonic filtration result, if improving locking phase
Filter out effect of the ring to low-order harmonic, dynamic response time will be elongated.Software locks based on cascade time delayed signal null method
Xiang Huan (Cascade Delayed Signal Cancellation Software Phase Locked Loop-CDSC-
SPLL), all harmonic components are filtered out using cascade delay elimination approach on the basis of SSRF-PLL phaselocked loop, to extract voltage just
Order components are to lock power grid fundamental phase and frequency, but signal is discontinuous in digital display circuit, and time delayed signal error can not
It avoids, error can be reduced using weighted average scheduling algorithm, but Pyatyi module needs calculate separately, it is computationally intensive.
Summary of the invention
The purpose of the present invention is to provide a kind of software phase-lock loop (the Inverse Discrete Fourier based on IDFT
Transform Software Phase Locked Loop-IDFT-SPLL), it is abnormal to there is imbalance, harmonic wave in network voltage
When the failures such as change, frequency discontinuity and SPA sudden phase anomalies, can accurately and quickly debug influence, relock network voltage letter
Number phase angle and angular frequency.
Realize the object of the invention technical solution are as follows: a kind of software phase-lock loop implementation method based on IDFT is specific to walk
Suddenly include:
The voltage signal u of S1, the non-ideal three-phase system of samplinga、ub、uc, it is quiet that α β is converted a signal into using clark transformation
The only voltage signal u under coordinate systemα、uβ；
S2, operating voltage frequency values, detecting step are detected through IDFT1-SPLL are as follows:
a、uα、uβQuasi- voltage positive-sequence signals u is extracted through IDFT1α′、uβ′；
B, it is converted by park by quasi- voltage positive-sequence signals uα′、uβ' conversion to the voltage signal under synchronous rotating frame
ud′、uq′；
c、uq' through PI controller obtain quasi- voltage positive-sequence signals angular frequencyf；
d、ωfIntegrated link obtains quasi- voltage positive-sequence signals phase angle θ, and park change is carried out in step b for feeding back to
It changes and completes closed loop phase lock；
E, the quasi- voltage positive-sequence signals angular frequency that will be obtainedfPower frequency period sampling is sought out after low-pass filtered device filtering
Number K, passes to IDFT2, for realizing frequency adaptive-filtering.
S3, operating voltage phase angle, detecting step are detected through IDFT2-SPLL are as follows:
a、uα、uβVoltage fundamental positive-sequence signals u is extracted through IDFT2α +、uβ +；
B, it is converted by park by voltage fundamental positive-sequence signals uα +、uβ +It converts to the voltage letter under synchronous rotating frame
Number ud +、uq +；
c、uq +Voltage fundamental positive-sequence signals angular frequency is obtained through PI controller；
D, the integrated link of voltage fundamental positive-sequence signals angular frequency obtains voltage fundamental positive-sequence signals phase angle θo。
E, by voltage fundamental positive-sequence signals phase angle θoClosed loop phase lock is completed in the park transformation fed back in the step b of S3.
Further, the voltage signal u of the non-ideal three-phase systema、ub、uc, it is specific as follows:
The voltage signal of non-ideal three-phase system is made of fundamental positive sequence and multi-frequency component, function expression
Are as follows:
In formula, U1 +For the voltage magnitude of network voltage fundamental positive sequence, UnFor the voltage amplitude of network voltage nth harmonic
Value, φ1And φnThe respectively initial phase of the starting phase angle of network voltage fundamental positive sequence and network voltage nth harmonic
Angle, ω are network voltage frequency.
Further, the finite discrete inverse Fourier transform 1 is IDFT1, extracts voltage signal uα′、uβ', specifically such as
Under:
In formula, N is primitive period number of samples；J is plural number；
The finite discrete inverse Fourier transform 2 is that IDFT2 extracts mains voltage signal uα +、uβ +, it is specific as follows:
In formula, K is power frequency period number of samples, uαβ(n-k) the n-th-k period alpha β axis input value is indicated.
Further, the quasi- voltage fundamental positive-sequence signals angular frequency that will be obtainedf, low-pass filtered device acquisition voltage fundamental
Angular frequencyo, through the available power frequency period number of samples K of operation, expression is as follows
In formula, ωoFor operating voltage angular frequency, TsFor the sampling period.
A kind of software phase-lock loop realization device based on IDFT, comprising:
NPC three-level inverter, for accessing power grid as system main circuit；
Sampling unit, for acquiring the voltage and current signal of power grid；
Phase locked-loop unit, for locking the network voltage of the sampling unit acquisition；
Closed Loop Control Unit, the θ that power network current and phase locked-loop unit for acquiring the acquisition unit generate, passes through
Closed-loop current control algorithm generates modulated signal；
Sinusoidal pulse width modulation unit, modulated signal is compared with triangular carrier, for generating corresponding arteries and veins according to modulated signal
Rush signal；
Driving unit, for pulse signal to be converted into level and driving circuit operation.
Further, the phase locked-loop unit includes two phase-locked loop structure I DFT1-SPLL and IDFT2-SPLL, in which:
Frequency detection module IDFT1-SPLL, for locking mains frequency；
Phase detecting module IDFT2-SPLL, for locking grid phase.
Further, the Closed Loop Control Unit, comprising:
Current signal conversion module is used for three-phase current signal ia、ib、icSynchronous rotary is converted into through clarke, park
Coordinate system id、iq；
PI control module, for by the i under synchronous rotating framed、iqSignal and Setting signal enter PI after making the difference and control
Device obtains dq axis modulated signal id′、iq′。
Modulated signal generation module, by id′、iq' through ipark, iclarke transformation acquisition modulated signal ua′、ub′、uc′。
Compared with prior art, the present invention having the following beneficial effects:
(1) IDFT structure is used, harmonic wave in non-ideal mains voltage signal can be filtered out completely under α β rest frame
Component, negative sequence component and DC component；
It (2), can be accurate when the failures such as imbalance, harmonic distortion, frequency discontinuity and SPA sudden phase anomalies occurs in network voltage
Quickly debugging influences, and relocks phase angle and the frequency of mains voltage signal；
(3) IDFT is simplified by simplified formula, calculation amount, it is easier to Digital Implementation.
Detailed description of the invention
Fig. 1 is that the present invention is based on the schematic diagrames of the software phase-lock loop of IDFT；
Fig. 2 is the Bode diagram of IDFT in the present invention, and (a) is the Bode diagram of IDFT1, (b) is the Bode diagram of IDFT2；
Fig. 3 is the schematic diagram of IDFT1-SPLL (a) and IDFT2-SPLL (b) in the present invention；
The simulation waveform of phaselocked loop when Fig. 4 is unbalanced source voltage；
Fig. 5 is the simulation waveform of phaselocked loop when harmonic wave being added into network voltage；
The simulation waveform of phaselocked loop when Fig. 6 is network voltage frequency discontinuity；
Fig. 7 is the simulation waveform of phaselocked loop when electric network voltage phase is mutated；
The simulation waveform of phaselocked loop when Fig. 8 falls for grid voltage three-phase；
The simulation waveform of phaselocked loop when Fig. 9 is singlephase earth fault；
Figure 10 is simulation waveform of the frequency discontinuity with phaselocked loop when harmonic wave interference failure；
Figure 11 is that the present invention is based on the structural schematic diagrams of the software phase-lock loop realization device of IDFT.
Specific embodiment
The present invention is based on the software phase-lock loop of IDFT, application ID FT1 extracts the quasi- positive sequence in non-ideal mains voltage signal
Signal obtains the angular frequency of quasi- positive-sequence signals through pi controller, then obtains quasi- positive-sequence signals by integral element
Phase angle is extracted non-ideal using power frequency period the number of samples K, application ID FT2 that numerical operation obtains operating voltage signal
Positive-sequence signals in mains voltage signal obtain the angular frequency of positive-sequence signals through pi controller, then by integral ring
Section obtains the phase angle of positive-sequence signals, specific as follows:
A kind of software phase-lock loop implementation method based on IDFT, comprising:
Sample the voltage signal u of non-ideal three-phase systema、ub、uc, the static seat of α β is converted a signal into using clark transformation
Voltage signal u under mark systemα、uβ；
Operating voltage frequency values, detecting step are detected through IDFT1-SPLL are as follows:
a、uα、uβQuasi- voltage positive-sequence signals u is extracted through IDFT1α′、uβ′；
B, it is converted by park by quasi- voltage positive-sequence signals uα′、uβ' conversion to the voltage signal under synchronous rotating frame
ud′、uq′；
c、uq' through PI controller obtain quasi- voltage positive-sequence signals angular frequencyf；
d、ωfIntegrated link obtains quasi- voltage positive-sequence signals phase angle θ, and park is carried out in step S22 for feeding back to
Transformation；；
E, the quasi- voltage positive-sequence signals angular frequency that will be obtainedfPower frequency period sampling is sought out after low-pass filtered device filtering
Number K, passes to IDFT2, for realizing frequency adaptive-filtering.
Operating voltage phase angle, detecting step are detected through IDFT2-SPLL are as follows:
a、uα、uβVoltage fundamental positive-sequence signals u is extracted through IDFT2α +、uβ +；
B, it is converted by park by voltage fundamental positive-sequence signals uα +、uβ +It converts to the voltage letter under synchronous rotating frame
Number ud +、uq +；
c、uq +Voltage fundamental positive-sequence signals angular frequency is obtained through PI controller；
D, the integrated link of voltage fundamental positive-sequence signals angular frequency obtains voltage fundamental positive-sequence signals phase angle θo。
E, by voltage fundamental positive-sequence signals phase angle θoClosed loop phase lock is completed in the park transformation fed back in step b.
Further, the voltage signal u of the non-ideal three-phase systema、ub、uc, it is specific as follows:
The voltage signal of non-ideal three-phase system is made of the component of fundamental positive sequence and multi-frequency, function representation
Formula are as follows:
In formula, U1 +For the voltage magnitude of network voltage fundamental positive sequence, UnFor the voltage amplitude of network voltage nth harmonic
Value, φ1And φnThe respectively initial phase of the starting phase angle of network voltage fundamental positive sequence and network voltage nth harmonic
Angle, ω are network voltage frequency.
Further, the finite discrete inverse Fourier transform 1 is that IDFT1 extracts quasi- network voltage positive sequence of fundamental frequency
uα′、uβ', it is specific as follows:
In formula, N is primitive period number of samples；J is plural number；
The finite discrete inverse Fourier transform 2 is that IDFT2 extracts network voltage positive sequence of fundamental frequency uα +、uβ +, specifically
Formula is as follows:
In formula, K is power frequency period number of samples, uαβ(k) kth period alpha β axis input value is indicated.
Further, the quasi- voltage fundamental positive-sequence signals angular frequency that will be obtainedf, obtained through single order wave digital lowpass filter
Press fundamental wave frequency ωo, through the available power frequency period number of samples K of operation:
In formula, ωoFor operating voltage angular frequency, TsFor the sampling period.Low-pass filter is also possible to high-order.
The present invention also provides a kind of software phase-lock loop realization device based on IDFT, referring to Fig.1 1 comprising:
NPC three-level inverter, for accessing power grid as system main circuit；
Sampling unit, for acquiring the voltage and current signal of power grid；
Phase locked-loop unit, for locking the network voltage of the sampling unit acquisition；
Closed Loop Control Unit, the θ that the power network current for acquiring the acquisition unit is generated with phase locked-loop unit pass through
Closed-loop current control algorithm generates modulated signal；
Sinusoidal pulse width modulation unit generates corresponding pulse signal according to modulated signal compared with triangular carrier；
Driving unit, for pulse signal to be converted into level and driving circuit operation.
Further, the phase locked-loop unit, comprising:
Frequency detection module, for locking mains frequency；
Phase detecting module, for locking grid phase；
Further, the Closed Loop Control Unit, comprising:
Current signal conversion module, by three-phase current signal ia、ib、icSynchronously rotating reference frame is converted into through clarke, park
It is id、iq；
PI control module, by the i under synchronous rotating framed、iqSignal and Setting signal enter PI controller after making the difference,
Obtain dq axis modulated signal id′、iq′。
Modulated signal generation module, id′、iq' through ipark, iclarke transformation acquisition modulated signal ua′、ub′、uc′。
With reference to the accompanying drawing and specific embodiment is described in further details the present invention.
Embodiment 1
Software phase-lock loop implementation method of the present embodiment based on IDFT, comprising the following steps:
Step 1, in conjunction with attached drawing 1, Fig. 3, in n-th of switch periods, by voltage signal ua(n)、ub(n)、uc(n) pass through
Clark transformation is transformed under α β rest frame, obtains uα(n)、uβ(n), conversion formula is as follows:
In formula, uaIt (n) is the n-th switch periods A phase voltage sampled signal, ubIt (n) is the n-th switch periods B phase voltage sampling letter
Number, ucIt (n) is the n-th switch periods C phase voltage sampled signal.
Step 2, by uα(n)、uβ(n) through (the Inverse Discrete Fourier of inverse discrete fourier transform 1
Transform 1, IDFT1) extract quasi- positive sequence of fundamental frequency uα′(n)、uβ′(n)；By uα(n)、uβ(n) anti-through discrete fourier
It converts 2 (Inverse Discrete Fourier Transform 2, IDFT2) and extracts quasi- positive sequence of fundamental frequency uα′(n)、uβ′
(n)；
IDFT1 transmission function is as follows:
In formula, uα(k) kth period alpha axis input value, u are indicatedβ(k) kth period β axis input value, u are indicatedα' (k) is kth week
Phase α axis output valve, uβ' (k) is kth period β axis output valve；
IDFT2 transmission function is as follows:
In formula, K is power frequency period number of samples, uα(k) kth period alpha axis input value, u are indicatedβ(k) kth period β axis is indicated
Input value, uα +It (k) is kth period alpha axis output valve, uβ +It (k) is kth period β axis output valve；
Step 3, by uα′(n)、uβ' (n) is converted under synchronous rotating frame through Park, obtains ud′(n)、uq′(n)；It will
uα +(n)、uβ +(n) it is converted under synchronous rotating frame through Park, obtains ud +(n)、uq +(n), conversion formula is as follows:
Park transformation for mula in IDFT1:
Park transformation for mula in IDFT2:
In formula, θo, θ be step 4 gained phase angle, uα +(n)、uβ +(n) input of α β axis, u are converted for Park in IDFT1α′
(n)、uβ' (n) is that Park converts the input of α β axis in IDFT2.
Step 4, by uq' (n) obtains quasi- positive sequence of fundamental frequency phase angle θ and angular frequency by PI controller and integrator
ωf, by uq +(n) positive sequence of fundamental frequency phase angle θ is obtained by PI controller and integratoro。
The angular frequency of step 5, the quasi- positive sequence of fundamental frequency for obtaining step 4f, fundamental wave is obtained after single order digital filtering
Angular frequencyo, power frequency period hits K is obtained through numerical operation, numerical operation formula is as follows:
In formula, ωoFor operating voltage angular frequency, TsFor the sampling period.
The present embodiment builds phaselocked loop simulation model using PLECS.Parameters are as shown in table 1.The present embodiment is verified altogether
Seven kinds of non-ideal electric network states, wherein Fig. 4 is grid voltage sags, and wherein A phase drops to 90%, B phase amplitude and falls 80%,
C phase amplitude falls 60%；Fig. 5 is Voltage Harmonic interference, to five times that network voltage injection amplitude is fundamental voltage amplitude 10%
Negative sequence harmonic, 10% seven positive sequence harmonics, 5% ten Negative sequence harmonics, the positive sequence harmonic three times of the ten of 5%；Fig. 6 is power grid
Electric voltage frequency mutation, angular frequency are mutated by 50 × 2 π rad/s to 45 × 2 π rad/s；Fig. 7 is electric network voltage phase mutation, phase
It is mutated 0.1 π rad；Fig. 8 is that grid voltage three-phase balances dropping simulation waveform, and amplitude falls 50%；Fig. 9 is the full dropping simulation of A phase
Waveform；Figure 10 is the superposition of Fig. 5 and Fig. 6 conditional.Using DSOGI-SPLL, two kinds of phaselocked loops of IDFT-SPLL carry out emulation pair
Than pll parameter setting is identical.IDFT-SPLL is abnormal in network voltage appearance imbalance, harmonic wave it can be seen from simulation result
Under the non-ideal grid conditions such as change, frequency discontinuity and SPA sudden phase anomalies, there is preferable anti-interference ability, quick dynamic response；
By analogous diagram 5 it is found that relative to DSOGI-SPLL, IDFT-SPLL can filter out low-order harmonic well, and locking phase is more accurate.
Table 1
| Parameter | Setting value |
| Voltage fundamental amplitude U | 311V |
| Voltage fundamental angular frequency | 50×2πrad/s |
| Sampling period Ts | 5e-5s |
| Primitive period hits N | 400 |
| Primitive period Tω | 0.02s |
| PI controller kp,ki | 0.482、25.568 |
Claims (7)
1. a kind of software phase-lock loop implementation method based on IDFT, which comprises the steps of:
The voltage signal u of S1, the non-ideal three-phase system of samplinga、ub、uc, the static seat of α β is converted a signal into using clark transformation
Voltage signal u in mark systemα、uβ；
S2, operating voltage frequency values, detecting step are detected through IDFT1-SPLL are as follows:
S21、uα、uβQuasi- voltage fundamental positive-sequence signals u is extracted through IDFT1α′、uβ′；
S22, it is converted by park by quasi- voltage fundamental positive-sequence signals uα′、uβ' conversion to the voltage under dq synchronous rotating frame
Signal ud′、uq′；
S23、uq' through PI controller obtain quasi- voltage fundamental positive-sequence signals angular frequencyf；
S24、ωfIntegrated link obtains quasi- voltage fundamental positive-sequence signals phase angle θ, and park is carried out in step S22 for feeding back to
Closed loop phase lock is completed in transformation；
S25, the quasi- voltage fundamental positive-sequence signals angular frequency that will be obtainedfPower frequency period sampling is found out after low-pass filtered device filtering
Number K, passes to IDFT2, for realizing frequency adaptive-filtering；
S3, operating voltage phase angle, detecting step are detected through IDFT2-SPLL are as follows:
S31、uα、uβThrough IDFT2, and power frequency period number of samples K is combined to extract voltage fundamental positive-sequence signals uα +、uβ +；
S32, it is converted by park by voltage fundamental positive-sequence signals uα +、uβ +It converts to the voltage signal under dq synchronous rotating frame
ud +、uq +；
S33、uq +Operating voltage angular frequency is obtained through PI controllero；
S34, the integrated link of voltage fundamental positive-sequence signals angular frequency obtain voltage fundamental positive-sequence signals phase angle θo, feed back to step
Rapid S32 completes closed loop phase lock for park transformation.
2. the software phase-lock loop implementation method according to claim 1 based on IDFT, which is characterized in that described non-ideal three
The voltage signal u of phase systema、ub、ucIt is made of the component of the positive and negative order components of fundamental wave and multi-frequency, function expression are as follows:
In formula, U1 +For the voltage magnitude of network voltage fundamental positive sequence, UnFor the voltage magnitude of network voltage nth harmonic, φ1
And φnRespectively the starting phase angle of the starting phase angle of network voltage fundamental positive sequence and network voltage nth harmonic, ω are
Network voltage fundamental wave frequency.
3. the software phase-lock loop implementation method according to claim 1 based on IDFT, which is characterized in that software phase-lock loop is real
Now use two phase-locked loop structure；
Wherein IDFT1 extracts quasi- network voltage positive sequence of fundamental frequency uα′、uβ', expression is as follows:
In formula, N is primitive period number of samples；J is plural number；
IDFT2 extracts network voltage positive sequence of fundamental frequency uα +、uβ +, expression is as follows:
In formula, K is power frequency period number of samples, uαβ(k) kth period alpha β axis input value is indicated.
4. the software phase-lock loop according to claim 1 based on IDFT, which is characterized in that in step S25, power frequency period is adopted
The solution formula of sample number K are as follows:
In formula, ωoFor operating voltage angular frequency, TsFor the sampling period.
5. a kind of software phase-lock loop realization device based on IDFT characterized by comprising
NPC three-level inverter, for accessing power grid as system main circuit；
Sampling unit, for acquiring the voltage and current signal of power grid；
Phase locked-loop unit, for locking the network voltage of the sampling unit acquisition；
Closed Loop Control Unit, the θ that power network current and phase locked-loop unit for acquiring the acquisition unit generate, passes through electric current
Closed loop control algorithm generates modulated signal；
Sinusoidal pulse width modulation unit, modulated signal generate corresponding pulse signal compared with triangular carrier；
Driving unit, for pulse signal to be converted into level and driving circuit operation.
6. the software phase-lock loop realization device according to claim 5 based on IDFT, which is characterized in that the phaselocked loop list
Member includes two phase-locked loop structure I DFT1-SPLL and IDFT2-SPLL, and wherein IDFT1-SPLL is used to detect mains frequency signal,
IDFT2-SPLL is for detecting grid phase.
7. the software phase-lock loop realization device according to claim 5 based on IDFT, which is characterized in that the closed-loop control
Unit, comprising:
Current signal conversion module is used for three-phase current signal ia、ib、icSynchronously rotating reference frame is converted into through clarke, park
It is id、iq；
PI control module, for by the i under synchronous rotating framed、iqSignal and target current enter PI controller after making the difference,
Obtain dq axis modulated signal id′、iq′。
Modulated signal generation module, by id′、iq' through ipark, iclarke transformation acquisition modulated signal ua′、ub′、uc′。
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111537809A (en) * | 2020-06-21 | 2020-08-14 | 陕西航空电气有限责任公司 | Digital phase sequence detection method suitable for alternating current power supply system |
| CN111999558A (en) * | 2020-07-08 | 2020-11-27 | 中国人民解放军94625部队 | Improved dq rotation coordinate system harmonic detection method |
| CN112054661A (en) * | 2020-10-12 | 2020-12-08 | 四川科陆新能电气有限公司 | Harmonic suppression static quantity output control method for single-phase electric system |
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| CN102761281A (en) * | 2011-04-28 | 2012-10-31 | 特变电工新疆新能源股份有限公司 | Phase-locked control system for inverter and phase locking method thereof |
| CN104022668A (en) * | 2014-05-30 | 2014-09-03 | 江苏大学 | Three-phase NPC grid-connected inverter based on quasi-proportional resonance control |
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| CN111537809A (en) * | 2020-06-21 | 2020-08-14 | 陕西航空电气有限责任公司 | Digital phase sequence detection method suitable for alternating current power supply system |
| CN111537809B (en) * | 2020-06-21 | 2022-06-07 | 陕西航空电气有限责任公司 | Digital phase sequence detection method suitable for alternating current power supply system |
| CN111999558A (en) * | 2020-07-08 | 2020-11-27 | 中国人民解放军94625部队 | Improved dq rotation coordinate system harmonic detection method |
| CN112054661A (en) * | 2020-10-12 | 2020-12-08 | 四川科陆新能电气有限公司 | Harmonic suppression static quantity output control method for single-phase electric system |
| CN112054661B (en) * | 2020-10-12 | 2023-06-27 | 四川科陆新能电气有限公司 | Harmonic suppression static quantity output control method for single-phase electric system |
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