CN113109691A - Portable circuit board test equipment based on VI curve - Google Patents
Portable circuit board test equipment based on VI curve Download PDFInfo
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- CN113109691A CN113109691A CN202110239972.6A CN202110239972A CN113109691A CN 113109691 A CN113109691 A CN 113109691A CN 202110239972 A CN202110239972 A CN 202110239972A CN 113109691 A CN113109691 A CN 113109691A
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/2832—Specific tests of electronic circuits not provided for elsewhere
- G01R31/2834—Automated test systems [ATE]; using microprocessors or computers
Abstract
The invention relates to the field of circuit board test equipment, in particular to portable circuit board test equipment based on a VI curve, which comprises an upper computer, a lower computer and a control system, wherein the upper computer is used for human-computer interaction and graphical display of the VI curve, the lower computer is used for generating and filtering output of a USB communication transmission sinusoidal excitation signal of the upper computer, configuring internal resistance between an output port and an input port, and extracting and processing signals, and the lower computer also comprises: the FPGA control system comprises an FPGA control core and a minimum system thereof, a DA circuit, an input processing circuit, an AD circuit, an output processing circuit, a JTAG/CONFIG circuit and a USB communication circuit, wherein equipment is arranged in a portable case, is convenient for a user to move and can be used in various scenes and environments; meanwhile, all operations of the user are finished on the touch screen, and the operation process is simple and quick; the conversion rate of the excitation source and the signal acquisition device is high, and continuous setting and acquisition of signals in a large frequency range can be realized.
Description
Technical Field
The invention relates to the field of circuit board test equipment, in particular to portable circuit board test equipment based on a VI curve.
Background
VI curve testing is one of the most important, most commonly used circuit board maintenance testing techniques. At present, domestic research mainly focuses on application of VI curve testing, for example, journal of "journal of the institute of aerospace and occupational technology, changsha", published in 12 months in 2012, discloses a circuit board fault diagnosis technology based on VI curve testing, fault points are located by detecting VI characteristic curves of circuits or devices, journal of "modern manufacturing technology and equipment", published in 11 months in 2018, discloses an application method of VI characteristic curves in PCB fault detection, but the two papers are only introduction of a work flow, research on working principles and equipment development of VI curves is not performed, and VI curve testing equipment used at present is mainly a desktop or rack-type device with a large volume and a large weight; for example, in a journal of electronic design engineering published in 12 months 2014, a design and a use method of a circuit board in-circuit test maintenance instrument are disclosed, but the introduction of the design part of the maintenance instrument is too brief, and more details are not disclosed.
Disclosure of Invention
In order to solve the above problems, the present invention provides a portable circuit board testing device based on VI curves.
The utility model provides a portable circuit board test equipment based on VI curve, includes the host computer that is used for the graphical display of human-computer interaction and VI curve, with the USB communication transmission sinusoidal excitation signal's of host computer production and filtering output, output and input port internal resistance's configuration, the lower computer of the back-extraction and the processing of signal still includes:
the FPGA control core and the minimum system thereof need to ensure the running speed of the microcontroller thereof and are used for controlling the generation of sinusoidal excitation signals, the acquisition of measurement signals and the communication with an upper computer;
the DA circuit is used for converting an excitation signal generated by the FPGA control core from a digital type to an analog type, sending the excitation signal to the measurement section and generating a required voltage scanning signal;
the input processing circuit is used for conditioning the input signal by using the attenuation and offset circuit and converting the differential signal into a smaller single-ended signal form suitable for the AD chip processing;
the AD circuit is used for converting the measured voltage signal from an analog type to a digital type and sending the voltage signal to the microcontroller;
the output processing circuit is designed for conditioning the differential signal into a single-ended signal because the signal generated by the AD circuit is the differential signal, and a 7-order elliptic passive LC filter and a post-stage signal amplifier are also designed for expanding the sine wave output bandwidth and the signal intensity;
the JTAG/CONFIG circuit is used for developing and debugging the lower computer and curing the lower computer;
and the USB communication circuit is used for transmitting the VI data to an upper computer for further processing.
The internal resistance is adaptively configured according to the uncertainty of the impedance of the element to be tested, a form of parallel connection of various resistances is adopted, each resistance is connected with a jumper cap in series, the resistance participating in the parallel connection is determined through the jumper, and the voltage drop at two ends of the configured internal resistance is an important basis for solving the current signal of the test point.
The PGA control core and the minimum system thereof comprise a clock circuit for providing a clock signal for FPGA work, an external reset button for a MAX706SESA chip, a falling edge reset signal generated when the button is pressed, a reset circuit connected to a 24-pin of EP3C53144C, a power circuit for providing required voltage, and a configuration chip circuit for filling an FPGA program into FPGA hardware in a short time after the system is powered on again.
The DA circuit is a 14-path parallel DA converter, the conversion rate reaches 125MSPS, and the range of the analog signal output peak value is 600 mV-6V.
The AD circuit is a 12-bit high-speed AD converter, a multi-stage differential pipeline architecture is adopted, and the maximum sampling rate reaches 65 MSPS.
The JTAG/CONFIG circuit comprises a JTAG circuit used for developing and debugging the FPGA of the lower computer and a CONFIG circuit used for downloading and solidifying the program of the lower computer, and the configuration chip selects an EPCS16 serial memory.
The USB communication circuit selects an FT245 chip as a USB transmission protocol chip, the chip has the fastest transmission rate of 1MB/s, 8-bit parallel data and USB signals can be mutually converted, and actually serial port data are sent according to a USB format without being driven and installed.
The FPGA of the lower computer runs the top layer code by adopting a BDF file, and after compiling each module by using a Verilog HDL language and instantiating, the BDF file is formed by mutually connecting and compiling the top layer code in the top layer file by lines.
The FPGA comprises a PLL clock module for generating the working frequency of a designated chip, a DA control module for sending a signal with a preset waveform to the DA chip according to a certain frequency, an AD simulation module for outputting the digital quantity converted by the AD chip and simultaneously outputting the AD conversion frequency in a matching manner, and a USB control module for realizing serial port control with an upper computer.
The appointed chips are AD chips and DA chips which work at 65MHz and 130MHz at most.
The invention has the beneficial effects that: the equipment is arranged in the portable case, is convenient for the user to move, and can be used in various scenes and various environments; meanwhile, all operations of the user are finished on the touch screen, and the operation process is simple and quick; the conversion rate of the excitation source and the signal acquisition device is high, and continuous setting and acquisition of signals in a large frequency range can be realized.
Drawings
The invention is further illustrated with reference to the following figures and examples.
FIG. 1 is a VI curve test module overall framework of the present invention;
FIG. 2 is a schematic diagram of the FPGA microcontroller minimum system of the present invention;
FIG. 3 is a DA circuit schematic of the present invention;
FIG. 4 is a schematic diagram of an output processing circuit of the present invention;
FIG. 5 is a schematic diagram of the circuit for configuring internal resistance of the present invention;
FIG. 6 is a schematic diagram of an input processing circuit of the present invention;
FIG. 7 is a schematic diagram of an AD circuit of the present invention;
FIG. 8 is a JTAG/CONFIG circuit of the present invention;
FIG. 9 is a schematic diagram of a USB communication circuit of the present invention;
FIG. 10 is a block diagram of the top level files of the FPGA of the present invention;
FIG. 11 is a block diagram of the lower computer software flow of the present invention;
fig. 12 is a block diagram of a usage flow of the present invention.
Detailed Description
In order to make the technical means, the creation characteristics, the achievement purposes and the effects of the invention easy to understand, the invention is further explained below.
As shown in fig. 1 to 12, a portable circuit board testing device based on VI curves includes an upper computer for human-computer interaction and graphical display of VI curves, a lower computer for generating and filtering an excitation signal transmitted by USB communication with the upper computer, configuring internal resistance between an output and an input port, and performing signal recovery and processing, and further includes:
the FPGA control core and the minimum system thereof need to ensure the running speed of the microcontroller thereof and are used for controlling the generation of sinusoidal excitation signals, the acquisition of measurement signals and the communication with an upper computer;
the DA circuit is used for converting an excitation signal generated by the FPGA control core from a digital type to an analog type, sending the excitation signal to the measurement section and generating a required voltage scanning signal;
the input processing circuit is used for conditioning the input signal by using the attenuation and offset circuit and converting the differential signal into a smaller single-ended signal form suitable for the AD chip processing;
the AD circuit is used for converting the measured voltage signal from an analog type to a digital type and sending the voltage signal to the microcontroller;
the output processing circuit is designed for conditioning the differential signal into a single-ended signal because the signal generated by the AD circuit is the differential signal, and a 7-order elliptic passive LC filter and a post-stage signal amplifier are also designed for expanding the sine wave output bandwidth and the signal intensity;
the JTAG/CONFIG circuit is used for developing and debugging the lower computer and curing the lower computer;
and the USB communication circuit is used for transmitting the VI data to an upper computer for further processing.
The equipment is arranged in the portable case, is convenient for the user to move, and can be used in various scenes and various environments; meanwhile, all operations of the user are finished on the touch screen, and the operation process is simple and quick; the conversion rate of the excitation source and the signal acquisition device is high, and continuous setting and acquisition of signals in a large frequency range can be realized.
As shown in fig. 2, by using the FPGA to control the core and the minimum system thereof, the conversion rate of the AD chip and the DA chip, and the data transmission rate both reach a relatively high level, and the operation rate of the microcontroller needs to be ensured; in addition, because the number of modules is large, the requirement for IO resources of the controller is high, the FPGA in various microcontrollers has a great speed advantage due to the characteristic of a parallel structure, and simultaneously has a large number of configurable peripheral interfaces, so that through repeated research and demonstration, the FPGA is selected as a final type selection scheme of the microcontroller, and EP3C5E144C of Cyclone III series is selected.
The internal resistance is adaptively configured according to the uncertainty of the impedance of the element to be tested, a form of parallel connection of various resistances is adopted, each resistance is connected with a jumper cap in series, the resistance participating in the parallel connection is determined through the jumper, and the voltage drop at two ends of the configured internal resistance is an important basis for solving the current signal of the test point.
The PGA control core and the minimum system thereof comprise a clock circuit for providing a clock signal for FPGA work, an external reset button for a MAX706SESA chip, a falling edge reset signal generated when the button is pressed, a reset circuit connected to a 24-pin of EP3C53144C, a power circuit for providing required voltage, and a configuration chip circuit for filling an FPGA program into FPGA hardware in a short time after the system is powered on again.
The clock circuit is designed to be a 50MHz active crystal oscillator connected to the 23 pins of the chip EP3C53144C and used for providing a clock signal for the FPGA to work.
The reset circuit is used for generating a reset signal for FPGA work, mainly a MAX706SESA chip is externally connected with a reset button, and a falling edge reset signal is generated when the button is pressed and is connected to a 24 pin of EP3C 53144C.
A power supply circuit: EP3C5E144 needs three voltages of 3.3V, 2.5V and 1.2V for work, MPC7128, HS-3282 and HS-3182 need 5V for work, and in addition, the positive and negative reference level ends of the HS-3182 chip need to be respectively connected with +/-15V voltage, so the power supply scheme is that 5V direct current is externally input, and the power supply conversion circuit is designed on the basis. 3.3V, 2.5V and 1.2V circuits are respectively built by using LMS1117-3.3, LMS1117-2.5 and LMS1117-1.2 chips.
The configuration chip circuit uses the EPCS16 as a configuration chip and is used for filling the FPGA program into FPGA hardware in a short time after the system is powered on again.
As shown in fig. 3, because a sine wave with adjustable frequency is generated, the requirement on DA conversion rate is high, and a common DA chip cannot meet the requirement of the present invention, through investigation and experimental verification, an AD9764 chip is selected as a conversion chip of a DA circuit, the chip is a 14-way parallel DA converter, the conversion rate can reach 125MSPS, the range of the analog signal output peak-to-peak value is 600mV to 6V, and the project requirement can be completely met.
As shown in fig. 4, since the signal generated by the AD circuit is a differential signal, the output processing circuit needs to be designed to condition the differential signal into a single-ended signal, and a 7 th-order elliptical passive LC filter and a subsequent signal amplifier are also designed to expand the sine wave output bandwidth and signal strength.
As shown in fig. 5, the present invention is further provided with a configuration resistor, the voltage drop at two ends of the configuration resistor is an important basis for calculating the current signal of the test point, and because the impedance of the tested element is uncertain, the internal resistor needs to be configured adaptively according to the impedance of the tested element, the adopted mode is a mode of adopting a plurality of resistance values in parallel, each resistance value is connected in series with a jumper cap, the resistors participating in parallel connection are determined by the jumper, and the size of the internal resistor can be changed flexibly.
The AD circuit shown in the figure 7 has the same requirement as a DA circuit for higher AD sampling rate, and after investigation and experimental verification, an AD9226 chip is selected to build the AD circuit for signal acquisition and conversion, the AD9226 chip is a 12-bit high-speed AD converter, a multi-level differential pipeline architecture is adopted, the maximum sampling rate reaches 65MSPS, and the requirement of the invention can be met.
As shown in fig. 8, the JTAG/CONFIG circuit includes a JTAG circuit for developing and debugging the FPGA of the lower computer and a CONFIG circuit for downloading and solidifying the program of the final lower computer, and the configuration chip selects an EPCS16 serial memory.
As shown in fig. 9, the USB communication circuit selects an FT245 chip as a USB transmission protocol chip, the fastest transmission rate of the chip is 1MB/s, 8-bit parallel data and a USB signal can be mutually converted, and actually serial data is sent according to a USB format without being driven and installed.
The FPGA of the lower computer runs the top layer code by adopting a BDF file, and after compiling each module by using a Verilog HDL language and instantiating, the BDF file is formed by mutually connecting and compiling the top layer code in the top layer file by lines.
As shown in fig. 10, the code running top-level code of the FPGA of the lower computer is formed by compiling each module in a BDF file using Verilog HDL language and instantiating the module, and then connecting and compiling the top-level file with lines.
As shown in fig. 11, the main functions of the upper computer software include receiving data transmitted by the lower computer through the USB, calculating values of voltage and current, and displaying the calculated values in the form of a dot diagram on a computer screen.
The FPGA comprises a PLL clock module for generating the working frequency of a designated chip, a DA control module for sending a signal with a preset waveform to the DA chip according to a certain frequency, an AD simulation module for outputting digital quantity converted by the AD chip and simultaneously outputting AD conversion frequency in a matching manner, and a USB control module for realizing serial port control with an upper computer, and the FPGA has high support degree on various operating systems of Windows7 and Ubuntu16.04 and is simple and convenient to develop and operate.
A PLL clock module: the working frequency of the FPGA is 50MHz generated by an active crystal oscillator connected with a hardware circuit, the AD chip and the DA chip selected by the project can work at 65MHz and 130MHz respectively to the maximum, and the maximum transmission frequency of the USB chip is 1MB/s, so that the working frequency of the chips can be generated by a PLL module.
A DA control module: the DA control module is mainly responsible for sending signals with preset waveforms to the DA chip according to a certain frequency, and the framework of the DA control module is shown in fig. 4. The main method is to store the waveform signal coding value in the internal ROM of the FPGA according to the resolution of 4096, and output the corresponding voltage value to the address in turn by the form of table lookup, and the update speed of the table lookup determines the frequency of the output waveform.
An AD simulation module: the module outputs digital quantity converted by the AD chip, and meanwhile, the AD conversion frequency is output in a matching manner, data converted by the AD chip can be checked in real time by a Signal Tap II Logic Analyzer tool of the Quartus software, the module is used for checking whether AD conversion is successful or not when a data transmission module is not equipped, great help is provided in the debugging process, the AD debugging is successful, and the conversion function can be ensured not to be used any more after no problem exists.
The USB control module: actually, serial port control uses an RS232 serial bus protocol with an upper computer, but now many computers do not have ports and are more equipped with USB interfaces, so that the protocol chip adopts an FT245 chip by using the interface form of USB.
The appointed chips are AD chips and DA chips which work at 65MHz and 130MHz at most.
The method comprises the following steps:
(1) connecting a USB port of the device with a USB of an upper computer;
(2) powering up the device;
(3) opening the upper computer software;
(4) measuring electronic components on normal and fault circuit boards simultaneously;
(5) and comparing the upper computer software images when the electronic components on the normal circuit board and the fault circuit board are measured, if the images are consistent, the components are normal, and if the images are different, the components are likely to be damaged or desoldered.
The foregoing shows and describes the general principles, essential features, and advantages of the invention. It will be understood by those skilled in the art that the present invention is not limited to the embodiments described above, which are merely illustrative of the principles of the invention, but that various changes and modifications may be made without departing from the spirit and scope of the invention, which fall within the scope of the invention as claimed. The scope of the invention is defined by the appended claims and equivalents thereof.
Claims (10)
1. The utility model provides a portable circuit board test equipment based on VI curve, is including the host computer that is used for the graphical demonstration of human-computer interaction and VI curve, with the USB communication transmission sinusoidal excitation signal's of host computer production and filtering output, output and input port internal resistance's configuration, the lower computer of the recovery and the processing of signal, its characterized in that: further comprising:
the FPGA control core and the minimum system thereof need to ensure the running speed of the microcontroller thereof and are used for controlling the generation of sinusoidal excitation signals, the acquisition of measurement signals and the communication with an upper computer;
the DA circuit is used for converting an excitation signal generated by the FPGA control core from a digital type to an analog type, sending the excitation signal to the measurement section and generating a required voltage scanning signal;
the input processing circuit is used for conditioning the input signal by using the attenuation and offset circuit and converting the differential signal into a smaller single-ended signal form suitable for the AD chip processing;
the AD circuit is used for converting the measured voltage signal from an analog type to a digital type and sending the voltage signal to the microcontroller;
the output processing circuit is designed for conditioning the differential signal into a single-ended signal because the signal generated by the AD circuit is the differential signal, and a 7-order elliptic passive LC filter and a post-stage signal amplifier are also designed for expanding the sine wave output bandwidth and the signal intensity;
the JTAG/CONFIG circuit is used for developing and debugging the lower computer and curing the lower computer;
and the USB communication circuit is used for transmitting the VI data to an upper computer for further processing.
2. The VI curve based portable circuit board testing device of claim 1, wherein: the internal resistance is configured in a self-adaptive manner according to the uncertainty of the impedance of the tested element, a plurality of resistance values are connected in parallel, each resistance value is connected with a jumper cap in series, the resistors participating in parallel connection are determined through the jumper, and the voltage drop at two ends of the configured internal resistance is an important basis for solving the current signal of the test point.
3. The VI curve based portable circuit board testing device of claim 1, wherein: the PGA control core and the minimum system thereof comprise a clock circuit for providing a clock signal for FPGA work, an external reset button for a MAX706SESA chip, a falling edge reset signal generated when the button is pressed, a reset circuit connected to a 24-pin of EP3C53144C, a power circuit for providing required voltage, and a configuration chip circuit for filling an FPGA program into FPGA hardware in a short time after the system is powered on again.
4. The VI curve based portable circuit board testing device of claim 1, wherein: the DA circuit is a 14-path parallel DA converter, the conversion rate reaches 125MSPS, and the range of the analog signal output peak value is 600 mV-6V.
5. The VI curve based portable circuit board testing device of claim 1, wherein: the AD circuit is a 12-bit high-speed AD converter, a multi-stage differential pipeline architecture is adopted, and the maximum sampling rate reaches 65 MSPS.
6. The VI curve based portable circuit board testing device of claim 1, wherein: the JTAG/CONFIG circuit comprises a JTAG circuit used for developing and debugging the FPGA of the lower computer and a CONFIG circuit used for downloading and solidifying the program of the lower computer, and the configuration chip selects an EPCS16 serial memory.
7. The VI curve based portable circuit board testing device of claim 1, wherein: the USB communication circuit selects an FT245 chip as a USB transmission protocol chip, the chip has the fastest transmission rate of 1MB/s, 8-bit parallel data and USB signals can be mutually converted, and actually serial port data are sent according to a USB format without being driven and installed.
8. The VI curve based portable circuit board testing device of claim 1, wherein: the FPGA of the lower computer runs the top layer code by adopting a BDF file, and after compiling each module by using a Verilog HDL language and instantiating, the BDF file is formed by mutually connecting and compiling the top layer code in the top layer file by lines.
9. The VI curve based portable circuit board testing device of claim 8, wherein: the FPGA comprises a PLL clock module for generating the working frequency of a designated chip, a DA control module for sending a signal with a preset waveform to the DA chip according to a certain frequency, an AD simulation module for outputting the digital quantity converted by the AD chip and simultaneously outputting the AD conversion frequency in a matching manner, and a USB control module for realizing serial port control with an upper computer.
10. The VI curve based portable circuit board testing device of claim 9, wherein: the appointed chips are AD chips and DA chips which work at 65MHz and 130MHz at most.
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Cited By (1)
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| CN116578072A (en) * | 2023-07-13 | 2023-08-11 | 西安康创电子科技有限公司 | Testing device and method for electronic anti-asthma controller |
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Application publication date: 20210713 |