CN114884511A - Universal analog-digital converter testing device - Google Patents
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Abstract
The invention provides a universal analog-to-digital converter testing device, which at least comprises: the test device comprises an analog-to-digital converter test module, a plurality of test interface boards, a test mainboard, an external power supply, a signal generator and a logic analyzer, wherein the analog-to-digital converter test module is sequentially connected to the test interface boards and the test mainboard, and the external power supply, the signal generator and the logic analyzer are connected with each other and are all connected to the analog-to-digital converter test module. The testing device can work independently in a modularized mode, has strong expandability, can realize different functions only by a simple building block mode, can independently run each part, can be spliced when needed, has stronger realized functions when more spliced module assemblies are used, is simple to operate and good in maintainability, and can well solve the testing problem of the actual analog-digital converter.
Description
Technical Field
The invention belongs to the field of chip testing, and particularly relates to a universal analog-to-digital converter testing device.
Background
In order to be suitable for evaluation of various analog-to-digital converters (ADCs), such as Flash, SAR, Pipeline, Sigma Delta, and the like, a general integrated automatic test system (ATE) is adopted in a conventional test method, and the machine is mainly used for Wafer (Wafer) tests, such as tyranda, UltraFlex, Advantest, and agilent, and although the structure is general and the hardware is unified, for high-precision and high-speed ADC tests, the performance test of the machine is difficult to truly embody the IP performance. However, in some low-voltage, high-precision and high-speed tests, the parasitic parameters of the general test channel affect the performance index, and if the high-level probe and hardware configuration are used instead, the cost is very high. In the face of differentiated ADC testing, an extensible customized test platform is increasingly important in various classes of IP testing.
Another common test solution is a dedicated package test system, such as the national instruments NI Labview, which provides a complete solution, such as a DUT test board, a dedicated signal stimulus source, and a signal acquisition and processing unit.
The evaluation scheme is a special ADC evaluation system of international factories such as ADI and TI, and a software and hardware evaluation scheme with a comparison system mainly aims at the demonstration of the functions and the performances of user products at a packaging level. These customized product demonstration systems are all optimized for single board circuit design. According to the division, the product companies divide the test of ADC into two levels of low speed and high speed, wherein the low speed interface is generally a CMOS serial or parallel interface with the interface speed lower than 200MHz, and the high speed interface is generally LVDS, JESD204B/C Transceiver interface with the speed reaching 12.5 Gbps. Therefore, a flexible and convenient test scheme which simultaneously considers high-speed and low-speed ADC tests is very important for ADC IP tests, namely, hardware configuration is unified, and maintenance is very convenient.
In summary, in order to perform final product evaluation, especially, package-level testing is generally used for mixed signal IP such as ADC, or application-level testing of final products, because the influence of actual product packaging is considered in the scheme, and the performance of the final testing is closer to the performance of the real environment, how to design a customized extensible testing platform can be combined with the evaluation method of mainstream products, and can be combined with high-precision instruments and meters, and can realize automated testing, and the open architecture is very needed in actual work.
Disclosure of Invention
In view of the above-mentioned shortcomings of the prior art, the present invention provides a universal testing apparatus for analog-to-digital converters, which can meet the requirements of modular design, can integrate required testing instruments, and can integrate a third-party evaluation system to enhance or expand the IP evaluation capability of analog-to-digital converters of different processes.
To achieve the above and other related objects, the present invention provides a universal testing apparatus for an analog-to-digital converter, the testing apparatus at least comprising: the test device comprises an analog-to-digital converter test module, a plurality of test interface boards, a test mainboard, an external power supply, a signal generator and a logic analyzer, wherein the analog-to-digital converter test module is sequentially connected to the test interface boards and the test mainboard, and the external power supply, the signal generator and the logic analyzer are connected with each other and are all connected to the analog-to-digital converter test module.
Preferably, the analog-to-digital converter testing module comprises a signal conditioning unit, a sine wave generator unit, an analog-to-digital converter, a multiplexing unit, a power management unit, a high-speed connecting seat unit, a module code and a standard sample unit, wherein the signal conditioning unit is connected with the signal generator and the sine wave generator unit and is used for conditioning signals output by the signal generator or the sine wave generator unit and outputting the signals to the analog-to-digital converter; the multiplexing unit is connected with the external power supply, the signal conditioning unit, the analog-to-digital converter, the power supply management unit and the high-speed connecting seat unit; the power supply management unit is connected with the 5V power supply adapter; the analog-to-digital converter is connected with an FPGA/logic analyzer interface and an FPGA/third-party evaluation board interface through the high-speed connecting seat unit; the module code is connected with the analog-to-digital converter and the high-speed connecting seat unit.
Preferably, a bridge resistor is further connected between the high-speed connection seat unit and the analog-to-digital converter.
Preferably, the analog-to-digital converter comprises a signal source input, a reference power supply, an IP power supply, a control input, a digital output and a coding pin; the signal source input is connected with the signal conditioning unit, the reference power supply and the IP power supply are connected with the multiplexing unit, the control input and the digital output unit are connected with the high-speed connecting seat unit, and the coding pin is connected with the module code.
Preferably, the analog-to-digital converter is one of a Flash analog-to-digital converter, a SAR analog-to-digital converter, a Pipeline analog-to-digital converter and a Sigma Delta analog-to-digital converter.
Preferably, the external power supply is an instrument external power supply and/or a precision voltage source.
Preferably, the testing device further comprises a main control computer, the main control computer is connected with the testing mainboard, the analog-to-digital converter testing module, the external power supply and the signal generator, and the main control computer is further connected to a network server and a data processing server.
Preferably, the testing device further comprises a high-low temperature control box, and the high-low temperature control box is connected with the main control computer, the analog-to-digital converter testing module and the testing interface board.
As described above, the universal analog-to-digital converter testing apparatus of the present invention has the following advantages:
the testing device provided by the invention can work independently in a modularized mode, has strong expandability, can realize different functions only by a simple building block form, can independently run each component before the whole system is built, and can be spliced when required, the more the spliced module components are, the stronger the realized functions are, in order to adapt to the test evaluation of analog-to-digital converters of different processes, different types and different working conditions as far as possible, and also in order to fully utilize the resources of high-grade instruments and equipment in the existing laboratory, a complex and comprehensive system is not designed, the purpose is to simplify the design of an analog-to-digital converter module so as to improve the system performance of the analog-to-digital converter, integrate other resources, and quickly build the system capacity, thereby completely meeting the test requirements of the analog-to-digital converter.
The testing device provided by the invention is modularized and has an open framework, and is suitable for testing analog-to-digital converter chips of different grades.
The test device provided by the invention is cheap, has strong adaptability, has a constant whole framework, and can solve all ADC tests by only replacing instruments and meters and test boards.
The testing device provided by the invention has low cost, and the system is easy to characterize aiming at the change of the IP of the tested object.
The testing device system and the special code of the DUT of the tested object provided by the invention are convenient for application in different scenes.
The test flow of the test device provided by the invention is standardized, and the system management and maintenance are convenient.
The testing device system provided by the invention adopts LABVIEW imaging language and GPIB interface, and is convenient for modular debugging and instrument system expansion.
Drawings
FIG. 1 is a diagram of a testing apparatus for an analog-to-digital converter according to the present invention.
FIG. 2 is a diagram of an ADC test module in the ADC test apparatus according to the present invention.
FIG. 3 is a block diagram of an embodiment of an analog-to-digital converter testing module in the universal analog-to-digital converter testing apparatus according to the present invention.
Fig. 4 is a hardware configuration diagram of a testing apparatus for an analog-to-digital converter according to the present invention.
Description of the element reference
1 analog-to-digital converter test module
11 Signal conditioning unit
12 sine wave generator unit
13 analog-to-digital converter
14 multiplexing unit
15 power management unit
16 high-speed connecting socket unit
17 modular coding
18 standard sample unit
2 test interface board
3 test mainboard
4 external power supply
41 external power supply for instrument
42 precision voltage source
5 Signal generator
6 logic analyzer
7 Main control computer
8 network server
9 data processing server
10 high-low temperature control box
Detailed Description
The embodiments of the present invention are described below with reference to specific embodiments, and other advantages and effects of the present invention will be easily understood by those skilled in the art from the disclosure of the present specification. The invention is capable of other and different embodiments and of being practiced or of being carried out in various ways, and its several details are capable of modification in various respects, all without departing from the spirit and scope of the present invention.
Please refer to the attached drawings. It should be noted that the drawings provided in the present embodiment are only for illustrating the basic idea of the present invention, and the components related to the present invention are only shown in the drawings rather than drawn according to the number, shape and size of the components in actual implementation, and the type, quantity and proportion of the components in actual implementation may be changed freely, and the layout of the components may be more complicated.
Example 1
As shown in fig. 1, the present embodiment provides a universal testing apparatus for an analog-to-digital converter, the testing apparatus at least includes: the test system comprises an analog-to-digital converter test module 1, a plurality of test interface boards 2, a test mainboard 3, an external power supply, a signal generator 5 and a logic analyzer 6, wherein the analog-to-digital converter test module 1 is sequentially connected to the test interface boards 2 and the test mainboard 3, and the external power supply, the signal generator 5 and the logic analyzer 6 are connected with each other and are all connected to the analog-to-digital converter test module 1.
As shown in fig. 1, the testing apparatus further includes a main control computer 7, the main control computer 7 is connected to the testing motherboard 3, the analog-to-digital converter testing module 1, the external power supply, and the signal generator 5, and the main control computer 7 is further connected to a network server 8 and a data processing server 9.
As shown in fig. 1, the testing apparatus further includes a high-low temperature control box 10, and the high-low temperature control box 10 is connected to the main control computer 7, the analog-to-digital converter testing module 1, and the testing interface board 2. The external power source 4 is an instrument external power source 41 and/or a precision voltage source 42.
The invention can realize all test data processing, analysis and generation of test reports through the network server and the data processing server, and is responsible for external network services. The main control computer 7 realizes communication control through a GPIB, an Ethernet, a USB, a serial port and instrument external power supply 41, a signal generator 5, a precision voltage source 42, a logic analyzer 6, an analog-to-digital converter testing module 1, a testing mainboard 3 and a high-low temperature control box 10, and completes control of the whole system. The software of the main control computer can be controlled by LABVIEW graphical software, and the software programming is more convenient.
Specifically, as shown in fig. 2, the analog-to-digital converter testing module 1 includes a signal conditioning unit 11, a sine wave generator unit 12, an analog-to-digital converter 13, a multiplexing unit 14, a power management unit 15, a high-speed connection socket unit 16, a module code 17, and a standard sample unit 18.
The signal conditioning unit 11 is connected to the signal generator 5 and the sine wave generator unit 12, and is configured to condition the signal output by the signal generator 5 or the sine wave generator unit 12, and output the signal to the analog-to-digital converter 1. Furthermore, the DDS sine wave generator is adopted in the embodiment, the scheme is simple, the size is small, and the FPGA system control is facilitated. The signal conditioning unit 11 may be a low pass filter, and is configured to perform conditioning on a sine wave signal or an external arbitrary waveform generator, such as signal conditioning of amplification buffering, anti-aliasing filtering, noise reduction, and the like, in order to perform optimal matching with the analog-to-digital converter test chip, where the signal conditioning unit has a positive power supply VDD and a negative power supply VEE of an independent BUFFER (BUFFER), and a common mode power supply VCOM of an amplifier, and these power supplies are configured to be manually adjustable to satisfy optimal input signal amplitude matching of the analog-to-digital converter test chip, and the signal conditioning unit 11 may use an external precision signal source when the signal quality cannot satisfy the input signal quality of the analog-to-digital converter test chip, except for an onboard sine wave generator, and this configuration may satisfy requirements of different IP test precisions.
The multiplexing unit 14 is connected to the external power supply 4, the signal conditioning unit 11, the analog-to-digital converter 13, the power management unit 15, and the high-speed connection socket unit 16.
The power management unit 15 is connected with a 5V power adapter. The power management unit 15 comprises a power configuration of the analog-to-digital converter 13, a power configuration of the signal conditioning unit 11, a power configuration of the sine wave generator unit 12 and a power configuration of the standard sample unit 18, in order to meet the requirements of chips to be tested of different types of analog-to-digital converters, a plurality of groups of power supplies are reserved in the system, in order to maximize the performance of the system, LDOs (low dropout regulators) with low power noise are basically selected, the RMS noise is less than 20uV, which is equivalent to the accuracy of 16bit of the chips to be tested of 1.8V, the groups of power supplies are all adjustable to meet the requirements of different chips to be tested, when an onboard power supply cannot meet the quality of input signals of the chips to be tested, an external precise voltage current source can be used, the configuration mode is very flexible, and the requirements of different IP test accuracies can be met.
The analog-to-digital converter 13 is connected to the FPGA/logic analyzer interface and the FPGA/third party evaluation board interface through the high-speed connection socket unit 16. The high-speed connecting seat unit 16 is an interface for connecting an analog-digital converter testing chip and an FPGA (which can be positioned on a testing mainboard), for different processes, the condition of different input and output IO voltages can occur, for convenient connection, the IO power supply on the FPGA board is provided by the analog-digital converter testing module 1, when the IP is different, as long as the VCCIO power supply of the analog-digital converter testing module 1 is changed, the corresponding power supply of the corresponding main control board level converter is also set with a correct value, and thus, the design requirement can be met. The FPGA/logic analyzer interface is used for connecting an FPGA or an external instrument (such as a logic analyzer) and collecting output data of the analog-to-digital converter. The FPGA/third party evaluation board interface is used for connecting a test interface board, can be fused with a third party evaluation system (such as TI and ADI), such as an evaluation system for connecting TI and ADI products of the same category, and realizes the scheme that an output signal of a mixed signal IP is connected to the FPGA through an FPGA conversion bridge, the FPGA converts the digital input of the IP according to the interface of the TI or ADI evaluation system, and parallel-serial conversion, serial-parallel conversion, digit conversion, format conversion and rate conversion can possibly occur, and the purpose is to realize the sampling of the data of a correct analog-to-digital converter.
As an example, a bridge resistor is further connected between the high-speed connector socket unit 16 and the analog-to-digital converter 1. When there is an unused IO port of the high speed connection socket in the adc test module 1, the bridge resistor should be disconnected to improve the signal integrity of the high speed connection socket.
The module code 17 is connected to the adc 13 and the high-speed connector unit 16. The module code 17 is set for module identification, firmware loading and self-checking during system automation test, and may be hard coded or may be a nonvolatile memory for storing characteristic information of the test module. The module code 17 can be located in the analog-to-digital converter 13 or other positions of the test module, one scheme in the analog-to-digital converter 13 is to use a coded resistor, different IPs are represented by different coded resistors, for example, the coded resistors are distinguished by using the size of the coded resistor value, different divided voltages are obtained by connecting the coded resistors in series with an external resistor, and the system controller can identify different IPs and load different applications by collecting the divided voltages. In addition, it should be noted that, in order to adapt to the test of all the analog-to-digital converters, the analog-to-digital converters are classified according to the IP rate, and can be divided into two types, namely, a low speed and a high speed, both of which can be connected to a high speed connection socket, each analog-to-digital converter test module has a module code, which is equivalent to its own identification, when the system is powered on, a test main control computer in the test platform will first query the information of the onboard module code, and select the required application software according to the information, and configure the appropriate parameters of the system, the test schemes of the analog-to-digital converters of the two speeds are basically the same, from the aspect of hardware, only the difference of the connection channels of the high speed interface is found, the low speed and the high speed are connected through different interfaces, the low speed and the high speed adopt the serial and parallel interfaces of CMOS level, the high speed is connected through high speed electrical serial standards such as LVDS, SSTL and the like, currently, ultra-high speed ADC IP supports the JESD204B/C serial transceiver standard, and the JESD204B interface is developed to support the ever-increasing bandwidth requirements of higher speed converters, providing higher channel rates (up to 12.5Gbps per channel). The interface can easily transmit a large amount of data to be processed by means of an extensible high-performance converter compatible with an open market FPGA solution, and a high-speed ADC IP test platform is very conveniently constructed because the test mainboard in the test framework comprises an FPGA part. Except for different interfaces, the high-speed analog-to-digital converter and the low-speed analog-to-digital converter have the same test contents, such as static indexes, dynamic indexes, time sequences, power consumption tests and the like.
The standard sample unit 18 is a standard component of the analog-to-digital converter 13, or a third party product of the same kind, and is used for performing a performance comparison between the two and performing an environmental check verification test comparison.
The analog-to-digital converter testing module 1 further comprises a signal source interface, an instrument interface and a power supply interface, the signal conditioning unit is connected with the signal generator 5 through the signal source interface 11, the multiplexing unit 14 is connected with the external power supply 4 through the instrument interface, and the power supply management unit 15 is connected with the 5V power supply adapter through the power supply interface.
More specifically, as shown in fig. 2, the analog-to-digital converter 13 includes a source input, a reference power supply, an IP power supply, a control input, a digital output, and a coding pin; the signal source input is connected with the signal conditioning unit 11, the reference power supply and the IP power supply are connected with the multiplexing unit 14, the control input and the digital output unit are connected with the high-speed connecting seat unit 16, and the coding pin is connected with the module code 17.
The source inputs V1+, V1-, there may also be multiple channels. The input signal can be a single-ended or double-ended differential input, and the signal amplitude supports 5V at most.
The analog-to-digital converter 13 may also include an excitation source, either onboard or externally selectable, that can extend the external precision signal source or instrumentation, maximizing the system's testing capabilities.
The reference power source VREF is an onboard precise reference source and can be provided onboard, and if the onboard precision reference source cannot meet the requirements, the reference power source VREF can be provided by an external instrument through an instrument interface.
The IP power supply is used to provide power for the analog-to-digital converter 13, and may be provided onboard, or may be provided by an external instrument through an instrument interface if the onboard cannot meet the requirement.
The control input DIN, such as the conversion clock or start signal of the analog-to-digital converter and the mode setting signal, is controlled by the digital DIN, and can be generated in various ways, either by any signal generator or by the FPGA.
The digital output DOUT is mainly used for outputting code values after conversion control of the analog-to-digital converter, and mainly comprises 8, 10, 12, 14, 16 and 18 bits.
Analog signals are input at the signal source input end of the analog-to-digital converter, a reference power source VREF is used for generating converted digital code value output corresponding to analog levels under the control of a digital input end DIN (time sequence), the analog-to-digital converter can be chips to be tested with different voltages and different accuracies, a plurality of analog input channels can be provided, and the analog-to-digital converter to be tested can also be chips of different types, such as a Flash analog-to-digital converter, a SAR analog-to-digital converter, a Pipeline analog-to-digital converter, a Sigma Delta analog-to-digital converter and the like.
In addition, in this embodiment, the signal source interface is an external necessity, such as a standard function generator or a standard arbitrary signal generator. The instrument interface is externally selectable, and may need to be provided externally in high-precision wide-range IP tests, so that the test capability of the environment is greatly improved. The power interface is an external optional power interface, and if the onboard power supply cannot meet the requirement, external power is generally required, so that the testing capability of the environment is greatly improved. If boundary performance testing is performed, a wide range of power supplies, and a wide range of analog input signals are also required. How to maintain the specification requirements over a wide range of signals also presents challenges to the testing device. In the testing process, in order to meet the testing requirements of the analog-to-digital converters IP with different precisions, speeds and interfaces, the working conditions of the existing single board can not completely cover the testing requirements of the IP, and in order to cover all the condition tests, the extensible interface is adopted to greatly enhance the evaluation breadth and depth of the IP.
The universal analog-digital converter testing device has the capability of being compatible with high-speed and low-speed hardware interfaces, the interface signal level is automatically connected with the analog-digital converter, the interface signal level and the analog-digital converter share a high-speed connecting seat, the interface voltages of different processes are different, the core and IO voltages of chips are different due to the difference of the processes, and the chip can support the voltage between 0.7V and 5.5V power supplies from 14nm to 55 nm. Therefore, IO voltages of different process IPs are easy to match, the method is also suitable for an international standard high-speed ADC interface JESD204B/C circuit, and interfaces with different speeds use different hardware connecting pins. LVDS high-speed signal can be connected to the high-speed analog-to-digital converter test board, single-ended input and output can be connected to the low-speed analog-to-digital converter test board, VCCIO is a power supply signal connecting the level converter of the main board and the IO level of the analog-to-digital converter, the power supply signal is a power supply signal provided for the analog-to-digital converter, in the whole system, the conversion control and conversion output of the analog-to-digital converter need to be connected with the data acquisition and control unit, the signals are actually provided for FPGA after being converted to proper voltage through the level converter of the main control board, for convenience, the power supply of the level converter on the main control board side is not fixed, but is matched with the VCCIO of the analog-to-digital converter module, so that the input and output of the main control board can be ensured to be the same with the level of the analog-to-digital converter no matter how the IO voltage of the unit to be tested is, and the problem of level matching is well solved.
The testing device can work independently in a modularized mode, has strong expandability, can realize different functions only by a simple building block form, can operate each component independently before the whole system is built, can be spliced when required, has stronger realized functions when more spliced module assemblies are used, aims to adapt to the test evaluation of analog-to-digital converters with different processes, different types and different working conditions as far as possible, and also aims to fully utilize the resources of high-grade instruments and equipment in the existing laboratory without designing a complex and comprehensive system, aims to simplify the design of an analog-to-digital converter module to improve the system performance of the analog-to-digital converter, integrate other resources and quickly build the system capability, and can realize the following functions by combining typical modules:
the first scheme is as follows: the main control board (test mainboard) + analog-to-digital converter test module +5V power adapter can realize the function: and the IP complete function test and the performance test (possibly partial performance) can not realize the power consumption test, and can be used as IP demonstration and prototype system verification.
Scheme II: the test mainboard, the analog-to-digital converter test module, the information source (optional), the external power supply (optional) can realize the functions: IP complete function test, performance test and DC test.
The third scheme is as follows: test mainboard + adc test module +5V power adapter + third party IP aassessment board (test interface board), fuse the test function, can realize the function: the complete function test of the IP, the performance test (possibly partial performance), the power consumption test can not be realized, and the test can be used as the IP demonstration.
And the scheme is as follows: the test mainboard, the analog-to-digital converter test module, the information source (optional), the external power supply (optional), the third-party IP evaluation board (test interface board) can realize the following functions: IP complete function test, performance test, DC test and test comparison.
And a fifth scheme: the test module of the analog-to-digital converter, the 5V power supply, the external information source, the code Pattern generator (Pattern generator), the logic analyzer and the data analysis processing software can manually complete the test function and the test comparison of the analog-to-digital converter.
In all schemes, the performance evaluation can be carried out on the standard sample unit, whether the test environment meets the design requirements can be verified, the performance comparison with the standard sample unit can be carried out, and the difference between the chips can be further analyzed and researched. The automated testing is realized by LABVIEW or PC software, all the testing items have basically the same flow, and the general program flow chart of the analog-to-digital converter testing device is as follows:
firstly, the system determines the peripheral power supply of a test instrument and the state of the instrument according to test items and completes the preparation work of a test environment;
then, the test items send test commands to the lower computer through the upper computer, and the system main control processor or the FPGA receives the test commands of the upper computer, analyzes the commands and generates corresponding control signals to the analog-to-digital converter test module;
then, the analog-to-digital converter testing module generates corresponding actions, such as a sine wave generator, relay response and the like, and the unit to be tested generates output response according to input excitation;
and finally, the test control main board collects data and calculates results and then stores the results, or transmits the original data to an upper computer for analysis and processing, and stores the results or the original data.
Example 2
As shown in fig. 3, the difference between the present embodiment and the first embodiment is that the model and the unit circuit of each unit in the analog-to-digital converter testing module 1 are further listed.
As shown in fig. 3, the analog-to-digital converter testing module 1 includes a signal conditioning unit 11, a sine wave generator unit 12, an analog-to-digital converter 13, a multiplexing unit 14, a power management unit 15, a high-speed connection socket unit 16, a module code 17, and a standard sample unit 18.
The signal conditioning unit 11 is connected to the signal generator 5 and the sine wave generator unit 12, and is configured to condition the signal output by the signal generator 5 or the sine wave generator unit 12, and output the signal to the analog-to-digital converter 13. The DDS sine wave generator is adopted in the scheme of the system, the scheme is simple, and the control is convenient. For example, the ADI company in the united states, the highly integrated frequency synthesizer AD9850 includes a programmable DDS system and a high-speed comparator, and can implement all-digital programming controlled frequency synthesis. The core of the programmable DDS system is a phase accumulator which consists of an adder and an N-phase register, wherein N is generally 24-32, a look-up table maps phase information of an input address into a sine wave amplitude signal, and then a DAC is driven to output a mode quantity.
The signal conditioning unit 11 can condition a sine wave signal or an external arbitrary waveform generator, such as signal conditioning of amplification buffering, anti-aliasing filtering, noise reduction and the like, and aims to realize optimal matching with an analog-to-digital converter test chip, the signal conditioning unit is provided with a positive power supply VDD and a negative power supply VEE of an independent BUFFER (BUFFER), and a common mode power supply VCOM of an amplifier, the power supplies are not completely fixed but are manually adjustable to meet the optimal input signal amplitude matching of the test chip, the signal conditioning unit can also use an external precise signal source besides the onboard sine wave generator, a differential amplifier for signal conditioning adopts a product of TI corporation THS4551, and the configuration mode can meet the requirement of IP test precision, low noise, precision, 150MHz, a fully differential amplifier, and differential input voltage noise: 3.3nV/√ Hz, 18bit settling time: 4V step, <500ns, is suitable for 16-bit to 20-bit differential high-speed Successive Approximation Register (SAR) driver, the THS4551 fully differential amplifier can provide a simple interface between single end and differential output, thus meeting the requirements of various high-precision analog-to-digital converters (ADC), the device has excellent direct current precision, low noise and stable capacitive load driving capability, and is very suitable for a data acquisition system with high-precision requirements; meanwhile, under the synergistic action of the amplifier and the ADC, excellent signal-to-noise ratio (SNR) and Spurious Free Dynamic Range (SFDR) can be obtained.
The multiplexing unit 14 is connected to the external power supply 4, the signal conditioning unit 11, the analog-to-digital converter 13, the power management unit 15, and the high-speed connection socket unit 16.
The power management unit 15 is connected with a 5V power adapter. The power management unit 15 comprises a power configuration of the analog-to-digital converter 13, a power configuration of the signal conditioning unit 11, a power configuration of the sine wave generator unit 12 and a power configuration of the standard sample unit 18, in order to meet the requirements of chips to be tested of different types of analog-to-digital converters, multiple groups of power supplies are reserved in the system, in order to meet the requirement of 16-bit high precision, a TI TLV75801PDBVR LDO is selected, 0.55V to 5.5V can be output in an adjustable mode, the groups of power supplies are all set to be adjustable to meet the requirements of different chips to be tested, when the power supplies cannot meet the quality of input signals of the chips to be tested, an external precision voltage current source can be used, the configuration mode is very flexible, and the requirements of different IP test precisions can be met.
The analog-to-digital converter 13 is connected to the FPGA/logic analyzer interface and the FPGA/third party evaluation board interface through the high-speed connection socket unit 16. The high-speed connecting seat unit 16 selects SAMTEC QTH/QSH series 180PIN connecting pieces, the performance is reliable, the model QTH-090-07-F-D-A is an interface for connecting an analog-digital converter testing chip and an FPGA (which can be positioned on a testing mainboard), for different processes, the condition that input and output IO voltages are different can occur, for convenience of connection, an IO power supply on the FPGA board is provided by an analog-digital converter testing module, when the IP is different, only a VCCIO power supply of the analog-digital converter testing module is changed, and a correct value is also set for a corresponding power supply of a corresponding main control board level converter, so that the design requirement can be met.
The FPGA/logic analyzer interface is used for being connected with an FPGA or an external instrument (such as a logic analyzer TEK TLA6103) and collecting output data of the analog-digital converter, wherein the logic analyzer can only collect the output data of the analog-digital converter and can not calculate results, and the FPGA can directly complete data collection and operation. The FPGA/third-party evaluation board interface is used for connecting a test interface board, can be fused with a third-party evaluation system TI ADS7057EVM, and is an ADC with a 14-bit SAR 2M sampling rate, and the scheme is realized by mainly providing a bridging effect between an ADC IP and the TI ADS7057EVM through an FPGA conversion logic, connecting an output signal of the analog-to-digital converter IP to the FPGA, and converting the digital input of the analog-to-digital converter IP by the FPGA according to the interface requirement of the TI ADS7057EVM to realize the accurate sampling of the data of the analog-to-digital converter.
A bridge resistor is further connected between the high-speed connector base unit 16 and the analog-to-digital converter 13.
The module code 17 is connected to the adc 13 and the high-speed connector unit 16. The module code 17 can be located in the analog-to-digital converter 13 or other locations of the test module, one scheme in the analog-to-digital converter 13 is to use resistors R _ DIE of different sizes to distinguish, different partial voltages are obtained by connecting with an external resistor RUP in series, a system controller can identify different IPs by collecting the partial voltages, different applications are loaded, and active or passive devices can be used for implementing R _ DIE.
The standard sample unit 18 is a standard component of the analog-to-digital converter 13, or a third party product of the same kind, and is used for performing a performance comparison between the two and performing an environmental check verification test comparison.
More specifically, as shown in fig. 3, the analog-to-digital converter 13 includes a source input, a reference power supply, an IP power supply, a control input, and a digital output; the signal source input is connected with the signal conditioning unit 11, the reference power supply and the IP power supply are connected with the multiplexing unit 14, and the control input and the digital output unit are connected with the high-speed connecting seat unit 16.
The signal selection of the source input V1+ and V1-is obtained by conditioning a TEK AFG3102C 14bit precision or an ADI AD 579120 bit DAC evaluation board.
The reference power source VREF selects TI REF1925 AIDCR for an on-board precision reference source, and if the on-board precision reference source cannot meet the requirement, the reference power source VREF can be provided by an external instrument, such as GS 200.
The IP power supply (VCC) is used for providing a power supply of the analog-to-digital converter, can be provided by an onboard TI TLV75801PDBVR adjustable LDO, has a range of 0.55V-5.5V, and can be provided by an external instrument and meter, such as Keysight N6075B/C, if the onboard can not meet the requirements.
The control input DIN is digital DIN, the DIN comprises clock signal SCLK, starting control signal STC and Mode setting signal, the Mode setting signal is set in SAR A/D converter, the system is generated by FPGA programmable logic, and the FPGA selects Xilinx Spartan XC6SLX 16.
The digital output DOUT is used for outputting code values after conversion control of the analog-to-digital converter, the signals comprise a conversion end signal ETC and digital output signals Dout [ N:0], and N values mainly comprise 8, 10, 12, 14, 16 and 18 bits.
Analog signals are input at the signal source input end of the analog-to-digital converter, a reference power source VREF is used for generating converted digital code value output corresponding to analog levels under the control of a digital input end DIN (time sequence), the analog-to-digital converter can be chips to be tested with different voltages and different accuracies, a plurality of analog input channels can be provided, and the analog-to-digital converter to be tested can also be chips of different types, such as a Flash analog-to-digital converter, a SAR analog-to-digital converter, a Pipeline analog-to-digital converter, a Sigma Delta analog-to-digital converter and the like.
In addition, in the embodiment, the signal source interface is an optional component, and the instrument interface and the external power supply interface are necessary components. If boundary performance testing is performed, a wide range of power supplies, and a wide range of analog input signals are also required. How to maintain the specification requirements over a wide range of signals also presents challenges to the test equipment. In the testing process, in order to meet the testing requirements of the analog-to-digital converters IP with different precisions, speeds and interfaces, the working conditions of the existing single board can not completely cover the testing requirements of the IP, and in order to cover all the condition tests, the extensible interface is adopted to greatly enhance the evaluation breadth and depth of the IP.
The universal analog-digital converter testing device has the capability of being compatible with high-speed and low-speed hardware interfaces, the interface signal level is automatically connected with the analog-digital converter, the interface signal level and the analog-digital converter share a high-speed connecting seat, the interface voltages of different processes are different, the core and IO voltages of chips are different due to the difference of the processes, and the chip can support the voltage between 0.7V and 5.5V power supplies from 14nm to 55 nm. Therefore, IO voltages of different process IPs are easy to match, the method is also suitable for an international standard high-speed ADC interface JESD204B/C circuit, and interfaces with different speeds use different hardware connecting pins. LVDS high-speed signals can be connected to a high-speed analog-to-digital converter test board, single-ended input and output can be connected to a low-speed analog-to-digital converter test board, VCCIO is a power supply signal for connecting a mainboard level converter and an IO level of an analog-to-digital converter, the power supply signal is a power supply signal provided for the analog-to-digital converter, in the whole system, conversion control and conversion output of the analog-to-digital converter need to be connected with a data acquisition and control unit, the signals are actually converted into proper voltage through a level converter of a main control board and then provided for an FPGA, and for convenience, the power supply of the level converter on the main control board side is not fixed and is matched with the VCCIO of an analog-to-digital converter module, so that the input and output of the main control board can be guaranteed to be the same as the level of the analog-to-digital converter no matter how the IO voltage of a unit to be tested is, and the problem of level matching is well solved.
But the testing arrangement modularization independent work of this embodiment, expandability is strong, only need simple building block form just can realize different functions, before the whole system is established, every part can the isolated operation, can splice when needs and form, the modular component of concatenation is more, the function that realizes is just stronger, in order to adapt to various different technologies as far as possible, the different grade type, the test evaluation of the adc of different operating condition, also in order to make full use of the senior instrument and equipment resource in current laboratory, and design complicated comprehensive system, the purpose is to simplify the design of adc module in order to improve adc's system performance, fuse other resources, the ability of system is established fast, the function that typical several kinds of module combination can be realized is as follows:
the first scheme is as follows: the main control board (test mainboard) + analog-to-digital converter test module +5V power adapter can realize the function: and the IP complete function test and the performance test (possibly partial performance) can not realize the power consumption test, and can be used as IP demonstration and prototype system verification.
Scheme II: the main control board, the analog-to-digital converter test module, the signal source (AFG3102 is optional) + the external power supply (GS200 is optional), and can realize the following functions: IP complete function test, performance test and DC test.
And a third scheme is as follows: the main control board + analog-to-digital converter test module +5V power adapter + third party IP aassessment board (ADS9100EVM), fuse the test function, can realize the function: the complete function test of the IP, the performance test (possibly partial performance), the power consumption test can not be realized, and the test can be used as the IP demonstration.
And the scheme is as follows: the main control board, the analog-to-digital converter testing module, the information source (AFG3102 is optional), the external power source (GS200 is optional), the third-party IP evaluation board (ADS9100EVM), and the functions of: IP complete function test, performance test, DC test and test comparison.
And a fifth scheme: the test module of the analog-digital converter +5V power supply + external information source + control signal generation AWG5014C + logic analyzer + data analysis processing software can manually realize the test function of the analog-digital converter.
Fig. 4 shows a hardware configuration diagram of the analog-to-digital converter module. The HSTC high-speed interface (high-speed connection base unit) of the system is connected into a stacked PCB, and output signals of the HSTC high-speed interface and the output signals of the HSTC high-speed interface are connected with a series resistor and close to the SOCKET (SOCKET) side.
As shown in fig. 4, the flow scheme of this embodiment is as follows:
in the first scheme, the analog-to-digital converter ADC IP + resistor + FPGA _ HSTC + FPGA + PC (computer) can realize the test of the analog-to-digital converter ADC.
And in the second scheme, the analog-to-digital converter ADC IP + resistor + FPGA _ HSTC + FPGA + resistor + J1/J2 is switched to the proper position + TI EVM Capaciure Board Socket + TI EVM + PC, so that TI system evaluation can be achieved in a fusion mode.
In all schemes, the performance evaluation can be carried out on the standard sample, whether the test environment meets the design requirements can be verified, and the performance comparison with the standard sample can be carried out, so that the comparison and analysis can be further carried out. The automatic test is realized through LABVIEW or PC software, all test items have basically the same flow, the following is a specific test flow example of the dynamic performance index of the analog-to-digital converter, and other test flows are the same.
Firstly, the system determines the peripheral power supply of a test instrument and the state of the instrument according to test items and completes the preparation work of a test environment;
then, the test module receives a test command of the upper computer;
then, signal excitation such as sine wave generation and working mode setting of an analog-digital converter IP are realized;
then, the FPGA of the control mainboard acquires digital codes after analog conversion of the analog-to-digital converter IP;
and then, after the main control board or the PC finishes continuously collecting the number of data points, calculating the test index through FFT.
Finally, the test result and the original data are stored,
the foregoing embodiments are merely illustrative of the principles and utilities of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or change the above-mentioned embodiments without departing from the spirit and scope of the present invention. Accordingly, it is intended that all equivalent modifications or changes which can be made by those skilled in the art without departing from the spirit and technical spirit of the present invention be covered by the claims of the present invention.
Claims (8)
1. A universal analog-to-digital converter testing arrangement, characterized in that the testing arrangement comprises at least: the test device comprises an analog-to-digital converter test module, a plurality of test interface boards, a test mainboard, an external power supply, a signal generator and a logic analyzer, wherein the analog-to-digital converter test module is sequentially connected to the test interface boards and the test mainboard, and the external power supply, the signal generator and the logic analyzer are connected with each other and are all connected to the analog-to-digital converter test module.
2. The universal analog-to-digital converter testing device of claim 1, wherein: the analog-to-digital converter testing module comprises a signal conditioning unit, a sine wave generator unit, an analog-to-digital converter, a multiplexing unit, a power supply management unit, a high-speed connecting seat unit and a module coding and standard sample unit,
the signal conditioning unit is connected with the signal generator and the sine wave generator unit and is used for conditioning the signal output by the signal generator or the sine wave generator unit and outputting the signal to the analog-to-digital converter;
the multiplexing unit is connected with the external power supply, the signal conditioning unit, the analog-to-digital converter, the power supply management unit and the high-speed connecting seat unit;
the power supply management unit is connected with the 5V power supply adapter;
the analog-to-digital converter is connected with an FPGA/logic analyzer interface and an FPGA/third-party evaluation board interface through the high-speed connecting seat unit;
the module code is connected with the analog-to-digital converter and the high-speed connecting seat unit.
3. The universal analog-to-digital converter testing device of claim 2, wherein: and a bridging resistor is also connected between the high-speed connecting seat unit and the analog-to-digital converter.
4. The universal analog-to-digital converter testing device of claim 2, wherein: the analog-to-digital converter comprises an information source input, a reference power supply, an IP power supply, a control input, a digital output and a coding pin; the signal source input is connected with the signal conditioning unit, the reference power supply and the IP power supply are connected with the multiplexing unit, the control input and the digital output unit are connected with the high-speed connecting seat unit, and the coding pin is connected with the module code.
5. The universal analog-to-digital converter testing device of claim 2, wherein: the analog-to-digital converter is one of a Flash analog-to-digital converter, an SAR analog-to-digital converter, a Pipeline analog-to-digital converter and a Sigma Delta analog-to-digital converter.
6. The universal analog-to-digital converter testing device of claim 1 or 2, characterized in that: the external power supply is an instrument external power supply and/or a precision voltage source.
7. The universal analog-to-digital converter testing device of claim 1, wherein: the testing device further comprises a main control computer, the main control computer is connected with the testing mainboard, the analog-to-digital converter testing module, the external power supply and the signal generator, and the main control computer is further connected to a network server and a data processing server.
8. The universal analog-to-digital converter testing device of claim 7, wherein: the testing device also comprises a high-low temperature control box, and the high-low temperature control box is connected with the main control computer, the analog-to-digital converter testing module and the testing interface board.
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