CN104198918A - Testing system for small-lot production of high-speed and -precision ADC (analog to digital converter) chips - Google Patents
Testing system for small-lot production of high-speed and -precision ADC (analog to digital converter) chips Download PDFInfo
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- CN104198918A CN104198918A CN201410464379.1A CN201410464379A CN104198918A CN 104198918 A CN104198918 A CN 104198918A CN 201410464379 A CN201410464379 A CN 201410464379A CN 104198918 A CN104198918 A CN 104198918A
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Abstract
The invention discloses a testing system for small-lot production of high-speed and -precision ADC (analog to digital converter) chips. The testing system comprises a mainstream PC (personal computer), a data acquiring module, a PCI-e (peripheral component interface express) module, a high-performance signal source, a band-pass filter set, a DUT (device under test) testing carrier plate and a double-channel digital power source, wherein the DUT testing carrier plate is connected with the high-speed data acquiring module in the form of mother and daughter boards and is connected with the high-performance signal source via a radio frequency cable, the double-channel digital power source supplies power for the high-speed data acquiring module and the DUT testing carrier plate through a power source socket, the PCI-e module serves as a daughter card to be inserted into a PCI-e slot of the PC and is connected with the high-speed data acquiring module through an optical fiber, and high-speed and -precision ADC chips to be tested are mounted into high-density SOCKET slots in the DUT testing carrier plate. The testing system is low in investment cost, high in testing accuracy and applicable to performance testing and small-lot production testing before large-scale production of the high-speed and -precision ADC chips.
Description
Technical field
The present invention relates to technical field of integrated circuits, related in particular to a kind of test macro for the small serial production of High Speed High Precision ADC chip, be suitable for small serial production and prototype test before ADC chip batch is produced.
Background technology
Digital receiver is widely used in the fields such as communication, digital TV in high resolution, radar, electronic countermeasure, sonar and Medical Instruments, for traditional receiver, digital receiver tool has great advantage, its core component is high-end analog to digital converter (ADC) chip, and the performance index of such chip are directly limiting the characteristics such as the frequency, bandwidth, power consumption, volume of digital receiver.The machine system implementations such as next generation communication base station, radar are intermediate frequency (IF) Direct Sampling, single receiver is supported channel transmission, this scheme requires harsh more a lot than conventional architectures to ADC chip performance, consider multiple radio frequency planning simultaneously, more than system requirements bandwidth will reach 100MHz, therefore develop High Speed High Precision ADC chip to implementing high-end IC industry development strategy, seize the commanding elevation of high-end core integrated circuit (IC) design, there is positive effect.
High Speed High Precision ADC chip is developed flow process and is comprised the links such as design, manufacture, laboratory test, batch product test and reliability testing, wherein criticizes product test and comprises middle survey, becomes survey.Become to survey in chip research and development and occupy extremely important status, batch product testing expense of high-end ADC chip product has occupied most of cost of chip research and development, it is very expensive that its main cause is to develop a set of High Speed High Precision ADC chip testing environment (comprising software and hardware) expense for ATE board, if find the design defect of chip product in one-tenth survey process, that becomes to survey previous R&D work needs closed loop again, and such caused time cost and financial cost are unaffordable to a company.
Summary of the invention
The deficiency existing for prior art, object of the present invention is just to provide a kind of test macro for the small serial production of High Speed High Precision ADC chip, not only can help design team before ADC chip is produced in enormous quantities, it to be carried out fast, comprehensively function and performance test, discovery relates to the problem and blemish in stage, design problem and defect are positioned, feeding back to designer revises again, simultaneously for batch ATE board test program development that product test team carries out provides guidance, to reach optimization test parameter, reduce the test duration, reduce batch target of producing testing cost, the ability that provides the short run print of testing through knowing the real situation to produce for client is also provided, help chip enterprise to shorten the research and development of products cycle thereby reach, accelerate Time To Market, obtain the target of economic benefit faster and betterly.
To achieve these goals, the technical solution used in the present invention is such: a kind of test macro for the small serial production of High Speed High Precision ADC chip, formed by main flow PC, data acquisition module, PCI-e module, high performance signal source, band-pass filter group, DUT test carrier plate and two-way digital power, described main flow PC is connected with data acquisition module, PCI-e module, high performance signal source respectively, and data acquisition module is connected by optical fiber with PCI-e module; Described high performance signal source has three, and its output signal is first passed through band-pass filter group, and band-pass filter group output signal is connected with DUT test carrier plate through radio-frequency cable again; Described data acquisition module is connected with DUT test carrier plate, two-way digital power respectively, described data acquisition module is connected in mother baby plate mode by high speed receptacle with DUT test carrier plate, described two-way digital power is data acquisition module power supply by high-speed high-density electric connector socket, and is the power supply of DUT test carrier plate by high-speed high-density electric connector socket.
When system works, High Speed High Precision ADC chip to be measured is packed in DUT test carrier plate, High Speed High Precision ADC chip converts simulating signal digital signal to and delivers to data acquisition module, digital collection module is sent to PCI-e module by optical fiber data, PCI-e module is stored in the data that receive on the hard disk of main flow PC, last performance evaluation program is carried out performance evaluation to these data, and whole testing process full automation, does not need manual intervention.
As a kind of preferred version, described PCI-e module is that PCI-e module, the data acquisition module based on fpga chip is the data acquisition module based on fpga chip, the model of the fpga chip that the described PCI-e module based on fpga chip, the data acquisition module based on fpga chip all adopt is XC5VLX110T, wherein the logic that realizes of fpga chip inside all realizes as basis taking the IP CORE of XILINX company, this implementation not only contributes to improve the stability of system, and can accelerate the construction cycle of whole project.The fpga chip of the fpga chip of the PCI-e module based on fpga chip, the data acquisition module based on fpga chip is all connected with Flash configuring chip, Flash pin-saving chip, DDR3 memory chip, clock driver circuit, optical interface module, jtag interface, LED light, reset circuit, AccessPort circuit, and described clock driver circuit includes crystal oscillator; Described reset circuit is made up of reset chip and reset button, and reset chip is connected with reset button; Described AccessPort circuit is by serial port chip and nine core point connectors, and AccessPort circuit is connected with nine core point connectors by serial port chip; The described PCI-e module based on fpga chip also includes digital power module group and PCI-e bus golden finger, and PCI-e bus golden finger is connected with the fpga chip of the PCI-e module based on fpga chip; Described digital power module group is connected in PCI-e bus golden finger; The described data acquisition module based on fpga chip also includes power circuit and high-speed high-density electric connector socket, and high-speed high-density electric connector socket is connected with the fpga chip of the data acquisition module based on fpga chip; Described power circuit is by supply socket and digital power module, the external two-way digital power of supply socket and being connected with digital power module.
Described PCI-e module is inserted in the PCI-e slot of main flow PC, for receiving the digital signal being converted to by ADC chip of data acquisition module block transfer, again these data are stored in to main flow PC hard disk with the form of dat form and carry out performance evaluation for Performance Analysis Software, test analysis software carries out fft analysis to these data, the counting as 16K/32K/64K/1M/2M/4M of intercepting.The core devices of PCI-e module is to adopt the fpga chip that Xilinx company model is XC5VLX110T, has realized the communication of Aurora fiber optic protocols, the PCI-e protocol communication of RS232 protocol communication, XILINX company and has controlled function.PCI-e module external interface has RS232 serial ports, optical communication interface, PCI-e interface, LED light, reseting interface, various interface circuit is all connected with fpga chip, its panel has four openings, LED light, reset circuit, AccessPort circuit and optical interface module are exposed from opening portion, for debugging, being connected and data communication with other module.
Described data acquisition module is connected with mother baby plate form with DUT test carrier plate as motherboard, and the digital signal that ADC chip is converted to is stored in the inner FIFO of FPGA, then by optical fiber, data is sent to PCI-e module.Data acquisition module core devices is to adopt the fpga chip that Xilinx company model is XC5VLX110T, has realized the Aurora fiber optic protocols communication, RS232 of RS232 protocol communication, SPI communication protocol, XILINX company to communication Protocol Conversion, the logic control function of SPI.Data acquisition module external interface has RS232 serial ports, optical communication interface, LED light, reseting interface, high-speed high-density electric connector socket, and total interface circuit is all connected with fpga chip.Wherein the high-speed high-density electric connector socket of data acquisition module docks mutually with the high-speed high-density electric connector socket on DUT test carrier plate, for the pins such as the data of ADC chip to be measured, clock, configuration, control are connected with the IO pin of fpga chip.
Simultaneously, after data acquisition module is connected with DUT test carrier plate, can be placed in high-low temperature test chamber, by power lead, data acquisition module is powered, by optical fiber, data are sent to PCI-e module, i.e. the present invention supports the performance test of High Speed High Precision ADC chip under high and low temperature environment.
As a kind of preferred version, described DUT test carrier plate comprises high density SOCKET slot, high-speed high-density electric connector socket, ADC chip reset circuit, ADC chip clock circuit, analog input signal commutation circuit, IMD index test input circuit, the 3rd common dynamic indicator input SMA connector SMA3, LED light, analog power module, digital power module, and described high-speed high-density electric connector socket, ADC chip reset circuit, ADC chip clock circuit, analog input signal commutation circuit are all connected with high density SOCKET slot; Described IMD index test input circuit, common dynamic indicator input SMA connector SMA3 are connected in analog input signal commutation circuit; Described analog power module, digital power module are all connected with high-speed high-density electric connector socket.
Described DUT test carrier plate, dock with mother baby plate form with data acquisition module as daughter board, be used for loading High Speed High Precision ADC chip to be measured, and by high density SOCKET slot, the pins such as the output data of ADC chip, clock, control be connected with the fpga chip IO pin on data acquisition module.When system works, the digital signal of ADC chip conversion can be stored in the inner FIFO of FPGA.
As a kind of preferred version, described ADC chip reset circuit is shown in that by 5 constant virtues dynamic indicator input SMA connector SMA5 and differential driving chip form, and 5 constant virtues sees that dynamic indicator input SMA connector SMA5 is connected with differential driving chip; Described ADC chip clock circuit is made up of the 4th common dynamic indicator input SMA connector SMA4 and the first differential transformers, and the 4th common dynamic indicator input SMA connector SMA4 is connected with the first differential transformers; Described analog input signal commutation circuit is made up of radio frequency converting switch and the second differential transformers, and radio frequency converting switch is connected with the second differential transformers; Described IMD index test input circuit is made up of the first common dynamic indicator input SMA connector SMA1, the second common dynamic indicator input SMA connector SMA2 and power combiner, the first common dynamic indicator input SMA connector SMA1, the second common dynamic indicator input SMA connector SMA2 are all connected with power combiner, and power combiner is connected in radio frequency converting switch.
As a kind of preferred version, described band-pass filter group comprises the first bandpass filter, the second bandpass filter and the 3rd bandpass filter, high performance signal source comprises the first high performance signal source, the second high performance signal source and third high performance signals source, described the first external the first bandpass filter in high performance signal source is as clock signal, the second external the second bandpass filter in high performance signal source is as the first analog input signal, external the 3rd bandpass filter in third high performance signals source is as the second analog input signal, and clock signal, the first analog input signal, the second analog input signal all transfers to DUT test carrier plate.
Described clock signal, the first analog input signal, the second analog input signal all transfer to the ADC chip on DUT test carrier plate, the data-signal amplitude peak that wherein enters ADC chip is-1dBFS, and frequency and the amplitude of the first analog input signal, the second analog input signal can be adjusted.
Compared with prior art, beneficial effect of the present invention:
1. can evaluate and test LVDS(supporting rate 800MHz) high-speed, high precision, the super high-speed A/D C chip performance index of interface or LVCMOS interface;
2. can evaluate and test the dynamic indicator of ADC chip: SNR, SFDR, SINAD, IMD, ENOB, THD, harmonic wave; Can evaluate and test the static parameter of ADC chip: INL, DNL;
3. support the frequency-domain analysis of time domain, 32K/64K/1M/2M/4M sampled point;
4. support light mouth, general SPI interface, the control of GPIO interface;
5. ADC chip data interface optional (LVDS or LVCMOS);
6. supporting signal incoming frequency Lookup protocol (GPIO control);
7. as long as change DUT test carrier plate and performance test analysis software, the present invention just can be applicable to the testing performance index of the chips such as DAC, receiving system integrated monolithic, base band signal process;
8. cost of the present invention is low, efficiency is high, flexible, help ADC chip R&D team proofing chip function and performance rapidly and accurately, avoided expensive ATE (automatic test equipment) development brings heavy cost burden to chip simultaneously; Not only help that finished product test team develops efficiently as early as possible, the ADC chip product test vector of high precision; And do not increasing under development cost prerequisite, can provide the short run print through high and low temperature test for client, help the rapid completion system checking of client, accelerate the Time To Market of client's product, thereby obtain faster and better economic benefit.
Brief description of the drawings
Fig. 1 is the system architecture schematic diagram of the embodiment of the present invention;
Fig. 2 is the circuit structure diagram of PCI-e module in the embodiment of the present invention;
Fig. 3 is the circuit structure diagram of data acquisition module in the embodiment of the present invention;
Fig. 4 is the DUT test carrier plate circuit structure diagram in the embodiment of the present invention.
Embodiment
Below with reference to specific embodiment, technical scheme provided by the invention is elaborated, should understands following embodiment and only be not used in and limit the scope of the invention for the present invention is described.
Embodiment:
As shown in Figure 1, a kind of test macro for the small serial production of High Speed High Precision ADC chip, formed by main flow PC, data acquisition module, PCI-e module, high performance signal source, band-pass filter group, DUT test carrier plate and two-way digital power, described main flow PC is connected with data acquisition module, PCI-e module, high performance signal source respectively, and data acquisition module is connected by optical fiber with PCI-e module; Described high performance signal source has three, and its output signal is first passed through band-pass filter group, and band-pass filter group output signal is connected with DUT test carrier plate through radio-frequency cable again; Described data acquisition module is connected with DUT test carrier plate, two-way digital power respectively, described data acquisition module is connected in mother baby plate mode by high-speed high-density electric connector socket with DUT test carrier plate, described two-way digital power is data acquisition module power supply by supply socket, and is the power supply of DUT test carrier plate by high-speed high-density electric connector socket; Described high performance signal source is high frequency, low phase noise cancellation signal source.
As shown in Figure 2, described PCI-e module is the PCI-e module based on fpga chip, the model of its fpga chip is XC5VLX110T, the fpga chip of the PCI-e module based on fpga chip is connected with Flash configuring chip, Flash pin-saving chip, DDR3 memory chip, clock driver circuit, optical interface module, jtag interface, LED light, reset circuit, AccessPort circuit, and described clock driver circuit includes crystal oscillator; Described reset circuit is made up of reset chip and reset button, and reset chip is connected with reset button; Described AccessPort circuit is by serial port chip and nine core point connectors, and AccessPort circuit is connected with nine core point connectors by serial port chip; The described PCI-e module based on fpga chip also includes digital power module group and PCI-e bus golden finger, and PCI-e bus golden finger is connected with the fpga chip of the PCI-e module based on fpga chip; Described digital power module group is connected in PCI-e bus golden finger.Described Flash configuring chip loads the configuration data of FPGA in the time that system powers on; The data message that Flash data-carrier store chip-stored FPGA design is wanted, these information can not lost because of system power failure; The data in enormous quantities that DDR3 memory chip is sent here for buffered optical fibers interface, then through PCI-e interface, data are write to hard disc of computer; Clock driver circuit produces two-way clock, and a road is for fpga logic clock, and a road is as the HSSI High-Speed Serial Interface special clock of PCI-E, the use of optical interface module.Optical interface module is for the communication between PCI-e module and data acquisition module, and in the present invention, optical communications protocols adopts the Aurora agreement of XILINX company, transfer rate 3.125GSPS; Reset circuit provides reset signal for FPGA design logic, and it is controlled by two kinds of modes, the first be by reset button by manual reset, after the second loads by fpga chip completion logic, " DONE " signal is realized and being automatically reset; AccessPort circuit is for debugging and the condition monitoring of fpga chip; The various chips that digital power module group uses for PCI-e module provides various DC voltage, and kind has 3.3V, 1.8V, 1.2V and 1V.
As shown in Figure 3, described data acquisition module is the data acquisition module based on fpga chip, the model of its fpga chip adopting is XC5VLX110T, the fpga chip of the data acquisition module based on fpga chip is all connected with Flash configuring chip, Flash pin-saving chip, DDR3 memory chip, clock driver circuit, optical interface module, jtag interface, LED light, reset circuit, AccessPort circuit, and described clock driver circuit includes crystal oscillator; Described reset circuit is made up of reset chip and reset button, and reset chip is connected with reset button; Described AccessPort circuit is by serial port chip and nine core point connectors, and AccessPort circuit is connected with nine core point connectors by serial port chip; The described data acquisition module based on fpga chip also includes power circuit and high-speed high-density electric connector socket, and high-speed high-density electric connector socket is connected with the fpga chip of the data acquisition module based on fpga chip; Described power circuit is by supply socket and digital power module, the external two-way digital power of supply socket and being connected with digital power module.Described optical interface module is for realizing the optical fiber communication of data acquisition module and PCI-e module, and communication protocol adopts the Aurora agreement of XILINX company, transfer rate 3.125GSPS; Power circuit is by supply socket and digital power module composition, the external two-way digital power of supply socket, 7.5 volts of input voltages, digital power module converts 3.3V, 1.8V, 1.2V and 1V to 7.5 volts, in addition, 7.5 volts of input voltages are also received the power pin of high-speed high-density electric connector socket, are used to the power supply of DUT test carrier plate; The connection corresponding to fpga chip IO pin of the signal pin of high-speed high-density electric connector socket, that is to say that clock, data, control and the configuration pin of ADC chip to be measured is connected with the IO pin of fpga chip by this connector.DDR3 memory chip, for the translation data of buffer memory high-speed ADC chip, improves the throughput of system; Flash data-carrier store chip, Flash configuring chip, clock driver circuit, reset circuit are the same with the function of corresponding circuits in PCI-e module.
As shown in Figure 4, described DUT test carrier plate comprises high density SOCKET slot, high-speed high-density electric connector socket, ADC chip reset circuit, ADC chip clock circuit, analog input signal commutation circuit, IMD index test input circuit, the 3rd common dynamic indicator input SMA connector SMA3, LED light, analog power module, digital power module, and described high-speed high-density electric connector socket, ADC chip reset circuit, ADC chip clock circuit, analog input signal commutation circuit are all connected with high density SOCKET slot; Described IMD index test input circuit, the 3rd common dynamic indicator input SMA connector SMA3 are connected in analog input signal commutation circuit; Described analog power module, digital power module are all connected with high-speed high-density electric connector socket; Described ADC chip reset circuit is shown in that by 5 constant virtues dynamic indicator input SMA connector SMA5 and differential driving chip form, and 5 constant virtues sees that dynamic indicator input SMA connector SMA5 is connected with differential driving chip; Described ADC chip clock circuit is made up of the 4th common dynamic indicator input SMA connector SMA4 and the first differential transformers, and the 4th common dynamic indicator input SMA connector SMA4 is connected with the first differential transformers; Described analog input signal commutation circuit is made up of radio frequency converting switch and the second differential transformers, and radio frequency converting switch is connected with the second differential transformers; Described IMD index test input circuit is made up of the first common dynamic indicator input SMA connector SMA1, the second common dynamic indicator input SMA connector SMA2 and power combiner, the first common dynamic indicator input SMA connector SMA1, the second common dynamic indicator input SMA connector SMA2 are all connected with power combiner, and power combiner is connected in radio frequency converting switch.Described high density SOCKET slot loads High Speed High Precision ADC chip to be measured, and the pins such as the output clock of ADC chip to be measured, data, control, configuration are connected with the corresponding pin of high-speed high-density electric connector socket through it.DUT test carrier plate is connected with mother baby plate form with data acquisition module by high-speed high-density electric connector socket, and this just equals relevant ADC chip to be measured output pin to be connected on the IO pin of fpga chip on data acquisition module.ADC chip reset circuit converts difference reset signal single side reset signal to by differential driving chip, then completes the reset to ADC chip to be measured; ADC chip clock circuit converts differential clock signal single-ended clock signal to by the first differential transformers and is input to ADC chip to be measured by the corresponding pin of high density SOCKET slot again; Analog input signal commutation circuit, according to the Different Dynamic performance of test ADC chip, is selected different analog input signal modes, in the time of test I MD index, selects double-tone input signal, in the time of other dynamic indicator of test, selects single-tone input signal.IMD index test input circuit produces the needed double-tone input signal of test ADC chip I MD performance index, two single-ended single-tone simulating signals become double-tone single-ended signal after power combiner is synthetic, the signal input part that converts differential analog signal to and deliver to again ADC chip to be measured through the second differential transformers, the second differential transformers has solved the problem of signalling channel impedance matching simultaneously; The 3rd common dynamic indicator input SMA connector SMA3 is used to ADC chip to provide single-tone single-ended analog input signal, this signal converts differential analog signal to and delivers to the signal input part of ADC chip to be measured again through the second differential transformers, the second differential transformers has also solved the problem of signalling channel impedance matching simultaneously; LED light is for information such as fpga chip running statuses on monitoring power supply, data acquisition module; Analog power module and digital power module are for voltage transitions, their power supply input is 7.5 volts of voltages that high-speed high-density electric connector socket provides, output voltage kind comprises 1.8 volts, digital 1.8 volts of simulations, 3.3 volts, digital 3.3 volts of simulations, and these kind power supplys are used to the chip on DUT test carrier plate, ADC chip power supply to be measured.
Embodiment 1: while specifically enforcement, comprise the steps:
(1) High Speed High Precision ADC chip to be measured is packed into the high-speed and high-density SOCKET slot on DUT test carrier plate;
(2) open external two-way digital power, for data acquisition module and DUT test carrier plate provide 7.5 volts of power supplys;
(3) use the first high performance signal source to provide clock signal for ADC chip to be measured, the clock signal that described the first high performance signal source provides requires to possess extremely low phase noise, as far as possible for ADC chip to be measured provides desirable clock source, in order further to promote clock source quality, the centre frequency of the first bandpass filter of described the first high performance signal source output terminal serial connection is 1～2MHz;
(4) analog input signal commutation circuit is set on DUT test carrier plate, analog channel is chosen as to the 3rd common dynamic indicator input SMA connector SMA3, use the second high performance signal source to provide analog input signal for ADC chip to be measured, the analog input signal that described the second high performance signal source provides requires to possess extremely low phase noise, could accurately test out like this performance index of ADC chip to be measured, the performance not so testing out is likely just the index of input signal; In order to promote analog input signal quality, meet the needs of ADC chip index test to be measured to phase noise or shake, the centre frequency of the second bandpass filter of described the second high performance signal source output terminal serial connection is 1～2MHz, the performance index of test ADC chip under different frequency, need to the corresponding bandpass filter of this frequency, therefore, need high performance band-pass filter group;
(5) operation " ADC chip performance analysis software " on main flow PC, open human-computer interaction interface, it is the one in 16K/32K/64K/1M/2M/4M that sampling number is set, conventionally dynamic indicator test selection 16K/32K/64K, Static State Index test selection 1M/2M/4M, the then dynamic performance index of analysis of running performance process analysis ADC chip to be measured.
The dynamic indicator that described step (1) ~ (5) can be analyzed has SNR, SFDR, SINAD, ENOB, THD, harmonic wave.
Embodiment 2: while specifically enforcement, comprise the steps:
(1) High Speed High Precision ADC chip to be measured is packed into the high-speed and high-density SOCKET slot on DUT test carrier plate;
(2) open external two-way digital power, for data acquisition module and DUT test carrier plate provide 7.5 volts of power supplys;
(3) use the first high performance signal source to provide clock signal for ADC chip to be measured, the clock signal that described the first high performance signal source provides requires to possess extremely low phase noise, as far as possible for ADC chip to be measured provides desirable clock source, in order further to promote clock source quality, the centre frequency of the first bandpass filter of described the first high performance signal source output terminal serial connection is 1～2MHz;
(4) analog input signal commutation circuit is set on DUT test carrier plate, analog channel is chosen as to IMD index test input circuit, use the second high performance signal source and third high performance signals source to simulate double-tone input signal for ADC chip to be measured provides;
(5) operation main flow PC testing software, open human-computer interaction interface, it is the one in 16K/32K/64K/1M/2M/4M that sampling number is set, conventionally dynamic indicator test selection 16K/32K/64K, Static State Index test selection 1M/2M/4M, the then dynamic performance index of analysis of running performance process analysis ADC chip to be measured.
The dynamic indicator that described step (1) ~ (5) can be analyzed is IMD index.
Embodiment 3: while specifically enforcement, comprise the steps:
(1) High Speed High Precision ADC chip to be measured is packed into the high-speed and high-density SOCKET slot on DUT test carrier plate;
(2) open external two-way digital power, for data acquisition module and DUT test carrier plate provide 7.5 volts of power supplys;
(3) use the first high performance signal source to provide clock signal for ADC chip to be measured, the clock signal that described the first high performance signal source provides requires to possess extremely low phase noise, as far as possible for ADC chip to be measured provides desirable clock source, in order further to promote clock source quality, the centre frequency of the first bandpass filter of described the first high performance signal source output terminal serial connection is 1～2MHz;
(4) analog input signal commutation circuit is set on DUT test carrier plate, analog channel is chosen as to the 3rd common dynamic indicator input SMA connector SMA3, use the second high performance signal source to provide analog input signal for ADC chip to be measured, the analog input signal that described the second high performance signal source provides requires to possess extremely low phase noise, could accurately test out like this performance index of ADC chip to be measured, the performance not so testing out is likely just the index of input signal; In order to promote analog input signal quality, meet the needs of ADC chip index test to be measured to phase noise or shake, the centre frequency of the second bandpass filter of described the second high performance signal source output terminal serial connection is 1～2MHz, the performance index of test ADC chip under different frequency, need to the corresponding bandpass filter of this frequency, therefore, need high performance band-pass filter group; The second differential transformers of described DUT test carrier plate is replaced by low-frequency transformer simultaneously;
(5) operation main flow PC testing software, open human-computer interaction interface, it is the one in 16K/32K/64K/1M/2M/4M that sampling number is set, conventionally dynamic indicator test selection 16K/32K/64K, Static State Index test selection 1M/2M/4M, the then dynamic performance index of analysis of running performance process analysis ADC chip to be measured.
The Static State Index that described step (1) ~ (5) can be analyzed has INL, DNL.
Embodiment 4: if will carry out the testing performance index under high and low temperature condition to ADC chip to be measured, first use hot-fluid cover that the high density SOCKET slot (301) that loads ADC chip to be measured is heated up (85 DEG C of technical grade product high temperature) or cooling (technical grade product low temperature is-40 DEG C), then adopt the step of embodiment 1, embodiment 2, embodiment 3 to test the index of needs test.
Embodiment 5: when completing after an ADC chip performance test, turn off two-way digital power, take out ADC chip from high-speed and high-density SOCKET slot, put into integrated circuit purpose-made pallet, and then adopt the step of embodiment 1, embodiment 2, embodiment 3, embodiment 4 to retest new ADC chip to be measured.
: finally it should be noted that, above embodiment is the non-limiting technical scheme in order to technical scheme of the present invention to be described only, those of ordinary skill in the art is to be understood that, those are modified or are equal to replacement technical scheme of the present invention, and do not depart from aim and the scope of the technical program, all should be encompassed in the middle of claim scope of the present invention.
Claims (5)
1. the test macro for the small serial production of High Speed High Precision ADC chip, it is characterized in that: described test macro is made up of main flow PC, data acquisition module, PCI-e module, high performance signal source, band-pass filter group, DUT test carrier plate and two-way digital power, described main flow PC is connected with data acquisition module, PCI-e module, high performance signal source respectively, and data acquisition module is connected by optical fiber with PCI-e module; Described high performance signal source has three, and its output signal is first passed through band-pass filter group, and band-pass filter group output signal is connected with DUT test carrier plate through radio-frequency cable again; Described data acquisition module is connected with DUT test carrier plate, two-way digital power respectively, described data acquisition module is connected in mother baby plate mode by high-speed high-density electric connector socket with DUT test carrier plate, described two-way digital power is data acquisition module power supply by supply socket, and is the power supply of DUT test carrier plate by high-speed high-density electric connector socket.
2. a kind of test macro for the small serial production of High Speed High Precision ADC chip according to claim 1, it is characterized in that: described PCI-e module is the PCI-e module based on fpga chip, data acquisition module is the data acquisition module based on fpga chip, the described PCI-e module based on fpga chip, the model of the fpga chip that the data acquisition module based on fpga chip all adopts is XC5VLX110T, the fpga chip of the PCI-e module based on fpga chip, the fpga chip of the data acquisition module based on fpga chip is all connected with Flash configuring chip, Flash pin-saving chip, DDR3 memory chip, clock driver circuit, optical interface module, jtag interface, LED light, reset circuit, AccessPort circuit, described clock driver circuit includes crystal oscillator, described reset circuit is made up of reset chip and reset button, and reset chip is connected with reset button, described AccessPort circuit is by serial port chip and nine core point connectors, and AccessPort circuit is connected with nine core point connectors by serial port chip, the described PCI-e module based on fpga chip also includes digital power module group and PCI-e bus golden finger, and PCI-e bus golden finger is connected with the fpga chip of the PCI-e module based on fpga chip, described digital power module group is connected in PCI-e bus golden finger, the described data acquisition module based on fpga chip also includes power circuit and high-speed high-density electric connector socket, and high-speed high-density electric connector socket is connected with the fpga chip of the data acquisition module based on fpga chip, described power circuit is by supply socket and digital power module, the external two-way digital power of supply socket and being connected with digital power module.
3. a kind of test macro for the small serial production of High Speed High Precision ADC chip according to claim 1, it is characterized in that: described DUT test carrier plate comprises high density SOCKET slot, high-speed high-density electric connector socket, ADC chip reset circuit, ADC chip clock circuit, analog input signal commutation circuit, IMD index test input circuit, the 3rd common dynamic indicator input SMA connector SMA3, LED light, analog power module, digital power module, described high-speed high-density electric connector socket, ADC chip reset circuit, ADC chip clock circuit, analog input signal commutation circuit is all connected with high density SOCKET slot, described IMD index test input circuit, the 3rd common dynamic indicator input SMA connector SMA3 are connected in analog input signal commutation circuit, described analog power module, digital power module are all connected with high-speed high-density electric connector socket.
4. a kind of test macro for the small serial production of High Speed High Precision ADC chip according to claim 3, it is characterized in that: described ADC chip reset circuit is shown in that by 5 constant virtues dynamic indicator input SMA connector SMA5 and differential driving chip form, and 5 constant virtues sees that dynamic indicator input SMA connector SMA5 is connected with differential driving chip; Described ADC chip clock circuit is made up of the 4th common dynamic indicator input SMA connector SMA4 and the first differential transformers, and the 4th common dynamic indicator input SMA connector SMA4 is connected with the first differential transformers; Described analog input signal commutation circuit is made up of radio frequency converting switch and the second differential transformers, and radio frequency converting switch is connected with the second differential transformers; Described IMD index test input circuit is made up of the first common dynamic indicator input SMA connector SMA1, the second common dynamic indicator input SMA connector SMA2 and power combiner, the first common dynamic indicator input SMA connector SMA1, the second common dynamic indicator input SMA connector SMA2 are all connected with power combiner, and power combiner is connected in radio frequency converting switch.
5. a kind of test macro for the small serial production of High Speed High Precision ADC chip according to claim 1, it is characterized in that: described band-pass filter group comprises the first bandpass filter, the second bandpass filter and the 3rd bandpass filter, high performance signal source comprises the first high performance signal source, the second high performance signal source and third high performance signals source, described the first external the first bandpass filter in high performance signal source is as clock signal, the second external the second bandpass filter in high performance signal source is as the first analog input signal, external the 3rd bandpass filter in third high performance signals source is as the second analog input signal, and clock signal, the first analog input signal, the second analog input signal all transfers to DUT test carrier plate.
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| CN201410464379.1A CN104198918A (en) | 2014-09-12 | 2014-09-12 | Testing system for small-lot production of high-speed and -precision ADC (analog to digital converter) chips |
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| CN201410464379.1A CN104198918A (en) | 2014-09-12 | 2014-09-12 | Testing system for small-lot production of high-speed and -precision ADC (analog to digital converter) chips |
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Application publication date: 20141210 |