CN203260029U - System chip prototype verification debugging device based on field programmable gate array (FPGA) - Google Patents
System chip prototype verification debugging device based on field programmable gate array (FPGA) Download PDFInfo
- Publication number
- CN203260029U CN203260029U CN 201320230874 CN201320230874U CN203260029U CN 203260029 U CN203260029 U CN 203260029U CN 201320230874 CN201320230874 CN 201320230874 CN 201320230874 U CN201320230874 U CN 201320230874U CN 203260029 U CN203260029 U CN 203260029U
- Authority
- CN
- China
- Prior art keywords
- module
- chip
- bus
- soc
- fpga
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Images
Abstract
The utility model relates to a system chip prototype verification debugging device based on a field programmable gate array (FPGA). The system chip prototype verification debugging device comprises an FPGA chip for prototype verification and a personable computer (PC) host computer provided with application programs, wherein a communication module for serial-to-parallel conversion or parallel-to-serial conversion is connected between the FPGA chip and the PC host computer. A bus module, a memory control module and a memorizer connected with the memory control module are arranged on the FPGA chip, the bus module is connected with the memory control module and a to-be-tested system chip module through an internal bus and connected with the communication module. The system chip prototype verification debugging device is connected with the PC host computer and the FPGA chip through the communication module, controls the internal bus of an FPGA prototype, accordingly can facilitate configuration and state detection of the system chip and improves the data transmission rate remarkably.
Description
Technical field
The utility model relates to System on Chip/SoC verifying and debugging technical field, relates in particular to a kind of System on Chip/SoC prototype verification debugging apparatus based on FPGA.
Background technology
Along with the development of Electronic Design and ic manufacturing technology, nowadays integrated circuit (IC) design develops into again the integrated of IP, i.e. System on Chip/SoC (System-On-Chip, SoC) designing technique from transistorized integrated the integrated of logic gate that develop into.Adopting SoC design system circuit can effectively reduce the cost of development of electronics, infosystem product, shorten the construction cycle, improve the competitive power of product, is the topmost product development mode that futurity industry circle will generally adopt.
Along with System on Chip/SoC is that the logic scale of SoC chip constantly increases, the debugging checking of SoC chip is vital, is the key that can SoC succeed in developing.Current System on Chip/SoC major part is that CPU serves as main control unit, controls other module cooperative work, and PC connects control CPU by JTAG, thereby reaches the whole SoC chip purpose of control.This traditional verification method, in the use of reality and operating process, exist following two problems: the one, because connect PC and FPGA verification platform by JTAG, transmission speed can only be confined to the 5-6M bit, transmission speed is very limited, is difficult to satisfy the rate request as needs big data quantities such as video code flows; The 2nd, be difficult to internal signal to System on Chip/SoC and effectively gather and show, be unfavorable for the verifying and debugging of System on Chip/SoC.
Summary of the invention
Technical problem to be solved in the utility model is to come the verifying and debugging System on Chip/SoC to have the slow problem of transmission speed for existing by JTAG, provides a kind of transmission speed the fast System on Chip/SoC prototype verification debugging apparatus based on FPGA.
For addressing the above problem, the technical solution of the utility model is:
A kind of System on Chip/SoC prototype verification debugging apparatus based on FPGA, comprise fpga chip and the PC main frame that is provided with application program for prototype verification, be connected with between described fpga chip and the PC main frame for string and or the communication module of parallel-serial conversion, communication module is used for data-switching to be made and satisfies communicating by letter between fpga chip and the PC main frame; Described fpga chip is provided with bus module, storage control module and the storer that links to each other with storage control module, bus module links to each other with System on Chip/SoC module to be measured with storage control module respectively by internal bus, bus module links to each other with communication module, the parallel data that bus module received communication module sends, and parallel data is sent in the storer parallel data by internal bus is used for configuration and starts System on Chip/SoC module to be measured, the data message that System on Chip/SoC module to be measured transmits after processing is preserved in storer, and the PC main frame is by the data message in communication module and the bus module read memory.
Be compared to prior art, System on Chip/SoC prototype verification debugging apparatus based on FPGA of the present utility model connects PC main frame and fpga chip by communication module, and the internal bus of FPGA prototype controlled, thereby can be configured and state-detection System on Chip/SoC easily, significantly improve the speed of data transmission.
Preferably, described bus module comprises the parallel data grabbing card module, bus interface module and internal signal acquisition module, the parallel data grabbing card module links to each other with the internal signal acquisition module with bus interface module respectively, the parallel data grabbing card module is used for receiving or sending parallel data information, the parallel data grabbing card module links to each other with communication module, bus interface module links to each other with System on Chip/SoC module to be measured with storage control module respectively by internal bus, the internal signal acquisition module links to each other with System on Chip/SoC module to be measured, the internal signal in the internal signal acquisition module Real-time Collection System on Chip/SoC module to be measured.
The internal signal acquisition module is used for Real-time Collection and stores System on Chip/SoC module to be measured and need the internal signal observed, the PC main frame can read the data message in the internal signal acquisition module, in order to observe easily state variation and the waveform of System on Chip/SoC inside during the verifying and debugging System on Chip/SoC, for the verifying and debugging of System on Chip/SoC provides convenience.
Preferably, described PC main frame links to each other with communication module by usb data line or netting twine.
Preferably, described internal bus is the AXI bus.
Description of drawings
Fig. 1 is that the utility model is based on the theory diagram of the System on Chip/SoC prototype verification debugging apparatus of FPGA.
Fig. 2 is that the utility model is based on the theory diagram of bus module in the System on Chip/SoC prototype verification debugging apparatus of FPGA.
Embodiment
Further describe the utility model below in conjunction with drawings and Examples, but protection domain of the present utility model is not limited to this.
With reference to Fig. 1, the debugging checking that it is the SoC chip that System on Chip/SoC prototype verification debugging apparatus based on FPGA of the present utility model is used for System on Chip/SoC module to be measured, verifying and debugging device comprise PC main frame, the communication module that links to each other in turn and the fpga chip that is used for prototype verification.
Be provided with in the PC main frame for the driver element and the PC application program that drive communication module, driver element is mainly finished the identification of communication module and driving, and the PC application program is finished data acquisition, data demonstration and man-machine interface with the bottom layer driving of communication module.The electrical connection of PC main frame and communication module can have various ways, and the utility model adopts usb data line or netting twine to connect.
Communication module is responsible for communicating by letter between fpga chip and the PC, communication module be used for string and or parallel-serial conversion, data after the conversion are made satisfy communicating by letter between fpga chip and the PC main frame.The communication of communication module is specially: when verifying and debugging begins, and the serial data that communication module receives and conversion PC main frame sends, and the parallel data after will changing sends in the fpga chip; After System on Chip/SoC module startup configuration to be measured was finished, communication module received the also parallel data of conversion fpga chip transmission, and the serial data after will changing sends in the PC main frame.The Parallel Digital interface of communication module is the Universal FIFO interface, can conveniently connect with MCU or fpga chip, can keep good compatibility and the complexity of reduction Interface design.
Referring to Fig. 1 and Fig. 2, the storer that fpga chip is provided with bus module, storage control module and links to each other with storage control module, bus module links to each other with System on Chip/SoC module to be measured with storage control module respectively by the AXI internal bus, and bus module links to each other with communication module.Bus module comprises parallel data grabbing card module, bus interface module and internal signal acquisition module, the parallel data grabbing card module links to each other with the internal signal acquisition module with bus interface module respectively, the parallel data grabbing card module is used for receiving or sending parallel data information, the parallel data grabbing card module links to each other with communication module, is used for carrying out exchanges data with communication module.Bus interface module links to each other with System on Chip/SoC module to be measured with storage control module respectively by the AXI internal bus, the internal signal acquisition module links to each other with System on Chip/SoC module to be measured, the internal signal in the internal signal acquisition module Real-time Collection System on Chip/SoC module to be measured.
Can realize that by bus module the access of System on Chip/SoC AXI internal bus, read-write and the image data of storer upload etc.The parallel data that parallel data grabbing card module received communication module in the bus module sends, wherein parallel data comprises parallel data information and parallel control information, under the control of storage control module, utilize the AXI internal bus to be sent in the storer by bus interface module parallel data information, parallel control information is directly used in configuration and starts System on Chip/SoC module to be measured, and storer can be external memory storage or internal storage.In System on Chip/SoC module verification debug process to be measured, internal signal acquisition module Real-time Collection is stored needs the internal signal observed in the System on Chip/SoC module to be measured, make the PC main frame can read data message in the internal signal acquisition module, in order to can observe easily state variation and the waveform of System on Chip/SoC inside during the verifying and debugging System on Chip/SoC.Under the control of storage control module, the data message that System on Chip/SoC module to be measured transmits after processing is preserved in storer, and the PC main frame is by the data message in communication module and the bus module read memory.
In concrete verifying and debugging process, bus module is connected in the AXI internal bus of System on Chip/SoC, realize bus interconnection, and the signal that will need to observe is linked in the internal signal acquisition module.The Parallel Digital interface of communication module is connected on the parallel data grabbing card module of bus module, the other end of communication module is linked on the PC main frame, and so the inside PC application program of PC main frame just can be carried out prototype verification, control, data transmission and signal demonstration to System on Chip/SoC by communication module.System on Chip/SoC module to be measured need to be configured, realize the input and output of data, and the configuration interface of System on Chip/SoC module to be measured is connected on the AXI internal bus, and the PC main frame can directly be read and write; The data that System on Chip/SoC module to be measured needs can be sent in the storer from the PC main frame, then configuration starts System on Chip/SoC module to be measured and carries out the data processing, the data of handling are put in the storer, application program in the PC main frame PC main frame that the data after processing can be read back, simultaneously, the application program in the PC main frame also can read data message in the internal signal acquisition module.Data message with debugging compares with actual result at last, judges the working condition of System on Chip/SoC module to be measured with this, and the register that the PC main frame also can read in the System on Chip/SoC module to be measured is at any time understood intermediate state.
In the above-mentioned explanation, all special instructions that do not add all adopt technological means of the prior art.
Claims (4)
1. System on Chip/SoC prototype verification debugging apparatus based on FPGA, comprise fpga chip and the PC main frame that is provided with application program for prototype verification, it is characterized in that, be connected with between described fpga chip and the PC main frame for string and or the communication module of parallel-serial conversion, communication module is used for data-switching to be made and satisfies communicating by letter between fpga chip and the PC main frame;
Described fpga chip is provided with bus module, storage control module and the storer that links to each other with storage control module, bus module links to each other with System on Chip/SoC module to be measured with storage control module respectively by internal bus, bus module links to each other with communication module, the parallel data that bus module received communication module sends, and parallel data is sent in the storer by internal bus, parallel data is used for configuration and starts System on Chip/SoC module to be measured, the data message that System on Chip/SoC module to be measured transmits after processing is preserved in storer, and the PC main frame is by the data message in communication module and the bus module read memory.
2. the System on Chip/SoC prototype verification debugging apparatus based on FPGA according to claim 1, it is characterized in that, described bus module comprises the parallel data grabbing card module, bus interface module and internal signal acquisition module, the parallel data grabbing card module links to each other with the internal signal acquisition module with bus interface module respectively, the parallel data grabbing card module is used for receiving or sending parallel data information, the parallel data grabbing card module links to each other with communication module, bus interface module links to each other with System on Chip/SoC module to be measured with storage control module respectively by internal bus, the internal signal acquisition module links to each other with System on Chip/SoC module to be measured, the internal signal in the internal signal acquisition module Real-time Collection System on Chip/SoC module to be measured.
3. the System on Chip/SoC prototype verification debugging apparatus based on FPGA according to claim 1 is characterized in that, described PC main frame links to each other with communication module by usb data line or netting twine.
4. the System on Chip/SoC prototype verification debugging apparatus based on FPGA according to claim 1 is characterized in that described internal bus is the AXI bus.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 201320230874 CN203260029U (en) | 2013-04-28 | 2013-04-28 | System chip prototype verification debugging device based on field programmable gate array (FPGA) |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 201320230874 CN203260029U (en) | 2013-04-28 | 2013-04-28 | System chip prototype verification debugging device based on field programmable gate array (FPGA) |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN203260029U true CN203260029U (en) | 2013-10-30 |
Family
ID=49472578
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN 201320230874 Expired - Lifetime CN203260029U (en) | 2013-04-28 | 2013-04-28 | System chip prototype verification debugging device based on field programmable gate array (FPGA) |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN203260029U (en) |
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105808396A (en) * | 2016-03-04 | 2016-07-27 | 浙江大华技术股份有限公司 | Chip debugging device, debugging method and SOC (System of Chip) chip system |
| CN110473589A (en) * | 2019-07-19 | 2019-11-19 | 苏州浪潮智能科技有限公司 | A kind of Multifunctional memory chip test system |
| CN110988662A (en) * | 2019-12-09 | 2020-04-10 | 思尔芯(上海)信息科技有限公司 | Signal debugging system and method based on FPGA prototype verification development board |
| CN111475437A (en) * | 2020-04-14 | 2020-07-31 | 深圳忆联信息系统有限公司 | DDR (double data Rate) verification device and method for SOC (System on chip) chip FPGA prototype of solid state disk, computer equipment and storage medium |
| CN111984494A (en) * | 2020-08-28 | 2020-11-24 | 思尔芯(上海)信息科技有限公司 | Multi-chip parallel deep debugging system, debugging method and application |
| CN115269293A (en) * | 2022-07-31 | 2022-11-01 | 北京汤谷软件技术有限公司 | Interconnection interface testing method based on chip FPGA prototype verification equipment |
-
2013
- 2013-04-28 CN CN 201320230874 patent/CN203260029U/en not_active Expired - Lifetime
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105808396A (en) * | 2016-03-04 | 2016-07-27 | 浙江大华技术股份有限公司 | Chip debugging device, debugging method and SOC (System of Chip) chip system |
| CN110473589A (en) * | 2019-07-19 | 2019-11-19 | 苏州浪潮智能科技有限公司 | A kind of Multifunctional memory chip test system |
| CN110988662A (en) * | 2019-12-09 | 2020-04-10 | 思尔芯(上海)信息科技有限公司 | Signal debugging system and method based on FPGA prototype verification development board |
| CN110988662B (en) * | 2019-12-09 | 2022-08-02 | 上海国微思尔芯技术股份有限公司 | Signal debugging system and method based on FPGA prototype verification development board |
| CN111475437A (en) * | 2020-04-14 | 2020-07-31 | 深圳忆联信息系统有限公司 | DDR (double data Rate) verification device and method for SOC (System on chip) chip FPGA prototype of solid state disk, computer equipment and storage medium |
| CN111984494A (en) * | 2020-08-28 | 2020-11-24 | 思尔芯(上海)信息科技有限公司 | Multi-chip parallel deep debugging system, debugging method and application |
| CN115269293A (en) * | 2022-07-31 | 2022-11-01 | 北京汤谷软件技术有限公司 | Interconnection interface testing method based on chip FPGA prototype verification equipment |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN203260029U (en) | System chip prototype verification debugging device based on field programmable gate array (FPGA) | |
| CN103530216B (en) | A kind of PCIE based on UVM verifies system | |
| CN104820637B (en) | A kind of hand-held USB3.0 protocol analyzers | |
| US8281280B2 (en) | Method and apparatus for versatile controllability and observability in prototype system | |
| CN105738854A (en) | Simulation memory test board system for intelligent ammeter embedded application and test method | |
| CN102917242A (en) | Testing system and testing method of multi-format video decoder | |
| CN104375915A (en) | Method for using interaction of server motherboard BMC and CPLD for rapid diagnosis of motherboard timing | |
| CN104504187A (en) | FPGA (Field Programmable Gate Array) online verification structure and method based on serial communication interface | |
| CN101770417A (en) | Hardware fault injection system and fault injection method based on JTAG | |
| CN204789908U (en) | Circuit board automatic test system based on labVIEW | |
| CN101419582B (en) | MVB/USB adapter based on SOPC technology and communication method thereof | |
| CN106649021A (en) | Testing device for PCIe slave device | |
| TW201514708A (en) | I2C bus monitoring device | |
| CN101114249A (en) | I2C bus testing apparatus of mainboard and method thereof | |
| CN202995708U (en) | Emulator with emulated data displaying and emulated data storing function | |
| CN107331421A (en) | A kind of SD card test system and method based on FPGA | |
| CN104200846A (en) | Embedded-type PROM test system and achieving method | |
| CN106709120A (en) | PCIE (peripheral component interface express) verification method | |
| CN103853680A (en) | Bus-signal monitoring device and method | |
| CN108153624B (en) | Test circuit board suitable for NGFF slot | |
| CN105094886A (en) | Device and method for burning serial number to lower computer containing RS (Recommended Standard) 485 bus from PC (Personal Computer) machine | |
| CN104572515B (en) | Tracking module, method, system and on-chip system chip | |
| CN103164313A (en) | Debugging system and debugging method | |
| CN103164308A (en) | Debugging system and debugging method | |
| CN201707664U (en) | ARINC429 testing equipment |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| CX01 | Expiry of patent term | ||
| CX01 | Expiry of patent term |
Granted publication date: 20131030 |