CN101114249A - I2C bus testing apparatus of mainboard and method thereof - Google Patents
I2C bus testing apparatus of mainboard and method thereof Download PDFInfo
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- CN101114249A CN101114249A CNA2006100367961A CN200610036796A CN101114249A CN 101114249 A CN101114249 A CN 101114249A CN A2006100367961 A CNA2006100367961 A CN A2006100367961A CN 200610036796 A CN200610036796 A CN 200610036796A CN 101114249 A CN101114249 A CN 101114249A
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Abstract
The invention discloses a detecting equipment and a detecting method of a main-board I2C bus, being applied in the main-board with I2C bus, which is mainly used for capturing the main-board signals sent by the I2C bus in the error erasing cycle and then to analyze and process to display the signals, so as to enable the users to clearly know the problems of the main-board.
Description
Technical field
The present invention is about the I2C bus testing apparatus and the method thereof of a kind of pick-up unit and method thereof, particularly a kind of mainboard.
Background technology
Conventional computer system mainly is by ROM-BIOS (Basic Input Output System, BIOS) carry out error eliminating function, the content of its debug generally includes the capacity check of internal memory, replacement detection, keyboard detection, interruption (Interrupt) detection, sequential detection and display detection etc.
When each parts that detects had fault to take place, the work of BIOS can stop, and sent the wrong serge sound of detecting sign indicating number, and showed type of error with different length, sound numerical table, with the type of informing that to the user problem takes place.Yet too Fu Za serge sound can allow the user be difficult for distinguishing, therefore, and the mistake place that in prior art, provides Debug Card to show computer system.
Existing Debug Card mainly be at connect with pci bus peripheral chip computer motherboard carry out error eliminating function.Yet computing machine has moved towards compact trend now, and (Integrated Circuit IC) must communicate with each other, even links up with the external world also to increase more peripheral chips in the computer motherboard.In order to allow hardware optimizing effect and simplify circuit design, all adopt the I2C bus to be connected now on the mainboard with peripheral chip, therefore, traditional PCI Debug Card just can't directly be applied to having in the debug operation of computer motherboard of I2C bus, and real be lacking now.
Moreover, if when research staff or maintenance personal's desire are carried out debug or maintenance to the computer motherboard with I2C bus, need to see through the signal that is transmitted on the electronic measurement I2C bus, carry out debug by the mode of manual type comparison signal again.Yet, see through manual type and carry out error eliminating function, easily look into the problem points of can not find on the mainboard because of the human negligence factor.
Summary of the invention
In view of above problem, the present invention mainly is to provide a kind of I2C bus testing apparatus and method thereof of mainboard, to solve the existing in prior technology problem.
The I2C bus testing apparatus of the disclosed a kind of mainboard of the present invention, the I2C bus is in order to transmit the signal of mainboard in the debug cycle, and the I2C bus testing apparatus of this mainboard includes: signal acquisition module, signal processing module and signal display module.
Behind the signal that the signal acquisition module is transmitted in order to acquisition I2C bus, signal processing module is deciphered the signal that has captured and analyze, and produces result.At last, the signal display module result that sends of received signal processing module and being shown then.
In addition, the I2C bus testing apparatus of mainboard provided by the invention more includes interface connected in series and internal memory test module.
Interface connected in series connects signal processing module, in order to link remote display or long-distance monitorng device, result is shown on display or the supervising device; And internal memory test module is in order to carry out the memory test program that is stored in advance in the start internal memory (Boot ROM), with the internal memory on the testing host.
In addition, the present invention more provides the I2C of mainboard total line detecting method, and the I2C bus is in order to transmit the signal of mainboard in the debug cycle, and the method includes the following step: at first, set up the signal condition table; After the signal that acquisition I2C bus is transmitted, the signal that decoding has captured, and the signal deciphered of basis signal state table analysis comparison, and produce result.At last, display process result.
In addition, detection method provided by the invention more includes provides interface connected in series, being linked to remote-control device, and result is shown on the remote-control device.Moreover, before the step of the signal that acquisition I2C bus is transmitted, need set up the memory test program in advance, and carry out the memory test program in the start internal memory, with the internal memory on the testing host in start internal memory (Boot ROM).
Below in embodiment, be described in detail detailed features of the present invention and advantage.
Description of drawings
Fig. 1 is the calcspar of the I2C bus testing apparatus of mainboard provided by the invention
Fig. 2 is the calcspar of memory detection module provided by the invention
Fig. 3 is the process flow diagram of the total line detecting method of I2C of mainboard provided by the invention
Embodiment
The I2C bus testing apparatus of mainboard provided by the invention can be used the mainboard of any I2C of having bus.Configuration on the mainboard can include electronic packages such as central processing unit (CPU), internal memory, South Bridge chip, north bridge chips, PS2 interface, USB interface and PCI slot, and the electronic package on the mainboard all is connected through the I2C bus, so that the signal between electronic package can transmit via the I2C bus.
Using pick-up unit of the present invention that mainboard is removed when desire staggers the time, then need provide power supply unit with the required power supply of supply mainboard normal operation, and with in the PCI slot on the pick-up unit insertion mainboard provided by the invention, so that pick-up unit of the present invention can see through PCI slot on the mainboard capture the signal that is transmitted in the I2C bus after, and handled and show, to allow the user can learn problem place on the mainboard clear and accurately.
See also Fig. 1 and Fig. 2 and be the calcspar of the I2C bus testing apparatus 20 of mainboard provided by the invention and the calcspar of internal memory test module 90.The I2C bus testing apparatus 20 of mainboard provided by the invention includes internal memory test module 90, signal acquisition module 100, signal processing module 110 and display module 120; And internal memory test module 90 includes start internal memory 91, setup unit 92 and network chip 93.Wherein, start internal memory 91 and setup unit 92 are linked to network chip 93.
Inserted the PCI slot (not shown) of mainboard 10 when the I2C of mainboard of the present invention bus testing apparatus 20, and supplied mainboard 10 normal operations required power supply, so that being removed, mainboard 10 staggers the time, after internal memory test module 90 reads storage data in start internal memory 91 and the setup unit 92, see through network chip 93 according to the data that read and be linked to remote server, after the startup flow process of carrying out mainboard 10, see through again and carry out the memory test program that is stored in advance in the start internal memory 91 (Boot ROM), with the internal memory on the testing host 10.
100 of signal acquisition modules see through the PCI slot and capture mainboard 10 in the debug signal that the I2C bus is transmitted during the cycle.Signal processing module 110, for example complicated formula programmable logic device (ComplexProgrammable Logic Device, CPLD) or imitate programmable gate array device (Field-Programmable Gate Array, FPGA), it connects signal acquisition module 100, after receiving the signal that received signal acquisition module 100 captured, the action of deciphering and analyzing, and produce corresponding result.
Signal processing module 110 includes decoding unit 111 and analytic unit 112, and wherein decoding unit 111 can be deciphered the information that is received, and analytic unit 112 is used to store the signal condition table of setting up in advance.In other words, after the signal that signal processing module 110 is captured through 111 pairs of signal acquisition modules 100 of decoding unit is deciphered action, compare by signal condition tables that store in the analytic unit 112 and the signal of having deciphered again, and produce result.Wherein, the signal that should transmit during the cycle in debug for the I2C bus that stores mainboard in advance in the aforesaid signal condition table.
At last, signal display module 120, for example LED or seven-segment display connect signal processing module 110, in order to receive and the display process result.
In addition, the I2C bus testing apparatus 20 of mainboard provided by the invention more includes interface 130 connected in series.Interface 130 connected in series, RS-232 interface for example, link signal processing module 110 can be for linking long-range displaying device or supervising device, so that result is shown on display device or the long-distance monitorng device.When result was shown in long-range supervising device, the processor in the supervising device that can be long-range thoroughly or other software presented result in different conditions and show, for example Graphic State, literal state or other show state.
Seeing also Fig. 3 is the total line detecting method of I2C that the invention provides mainboard, the I2C bus is in order to transmit the signal of mainboard in the debug cycle, the method includes the following step: at first, set up signal condition table (step 200), then, behind the signal (step 210) that acquisition I2C bus is transmitted, the signal that has captured is deciphered (step 220), and the signal deciphered of basis signal state table analysis comparison, and produce result (step 230).At last, display process result (step 240).
Wherein, the signal that signal condition table in the step 200 should transmit during the cycle in debug for the I2C bus that stores mainboard in advance, and step 220 and step 230 see through complicated formula programmable logic device (ComplexProgrammable Logic Device, CPLD) or imitate a programmable gate array device (Field-Programmable Gate Array, the action that the hardware program of being write in FPGA) is carried out decoding and analyzed.At last, step 240 is come the display process result through light emitting diode or seven-segment display.
Yet before the execution in step 210, detection method provided by the invention can be set up the memory test program in advance in start internal memory (Boot ROM) (step 201), and carries out the memory test program in the start internal memory, with the internal memory (step 202) on the testing host.
In addition, detection method provided by the invention is after step 240, and more including provides interface connected in series, being linked to remote-control device (step 250), and result is shown on the remote-control device.Wherein, interface connected in series such as RS-232 interface or other can be linked to the interface of remote-control device, and remote-control device comprises on display or the supervising device.
Via aforementioned, the I2C bus testing apparatus of mainboard provided by the invention, mainly be the signal that transmitted of the acquisition I2C bus of mainboard in the debug cycle after, in addition analyzing and processing and shows signal again are to make the user clear and understand the problem points of learning mainboard.
Though the present invention discloses as above with aforesaid embodiment, so it is not in order to limit the present invention.Without departing from the spirit and scope of the present invention, change of doing and retouching all belong to scope of patent protection of the present invention.Please refer to appended claim about the protection domain that the present invention defined.
Claims (18)
1. the I2C bus testing apparatus of a mainboard, this I2C bus is characterized in that in order to transmit the signal of this mainboard in the debug cycle I2C bus testing apparatus of this mainboard includes:
One signal acquisition module is in order to capture this signal that this I2C bus is transmitted;
One signal processing module connects this signal acquisition module, in order to this signal of deciphering and analysis has captured, and produces a result; And
One signal display module connects this signal processing module, in order to show this result.
2. the I2C bus testing apparatus of mainboard according to claim 1 is characterized in that, this device more includes a serial connecting interface, connects this signal processing module, in order to connect a remote-control device, so that this result is shown on this remote-control device.
3. the I2C bus testing apparatus of mainboard according to claim 2 is characterized in that, this interface connected in series is a RS-232 interface.
4. the I2C bus testing apparatus of mainboard according to claim 2 is characterized in that, this remote-control device is selected from the group that a display device and a supervising device are formed.
5. the I2C bus testing apparatus of mainboard according to claim 1 is characterized in that, this signal processing module includes:
One decoding unit is in order to decipher this signal that has captured; And
One analytic unit stores a signal condition table, compares in order to this signal and this signal condition table that will decipher, to produce this result.
6. the I2C bus testing apparatus of mainboard according to claim 5 is characterized in that, this signal condition table is this signal that the I2C bus of this mainboard should transmit during the cycle in debug that prestores.
7. the I2C bus testing apparatus of mainboard according to claim 1 is characterized in that, more includes an internal memory test module, in order to carry out a memory test program, to test the internal memory on this mainboard.
8. the I2C bus testing apparatus of mainboard according to claim 7 is characterized in that, this memory test program is stored in the start internal memory (Boot ROM).
9. the I2C bus testing apparatus of mainboard according to claim 1, it is characterized in that, this signal processing module is a complicated formula programmable logic device (Complex Programmable Logic Device, CPLD) or be one imitate the programmable gate array device (Field-Programmable Gate Array, FPGA).
10. the I2C bus testing apparatus of mainboard according to claim 1 is characterized in that, this signal display module is formed at least one light emitting diode.
11. the total line detecting method of the I2C of a mainboard, this I2C bus is characterized in that in order to transmit the signal of this mainboard in the debug cycle the total line detecting method of the I2C of this mainboard includes the following step:
Set up a signal condition table;
Capture this signal that this I2C bus is transmitted;
This signal that decoding has captured;
Compare this signal of having deciphered according to this signal condition table analysis, and produce a result; And
Show this result.
12. the total line detecting method of the I2C of mainboard according to claim 11 is characterized in that, captures before the step of this signal, more comprises the following steps:
The memory test program of setting up is in a start internal memory (Boot ROM); And
Carry out this memory test program in this start internal memory, to test the internal memory on this mainboard.
13. the total line detecting method of the I2C of mainboard according to claim 11 is characterized in that, more including provides a serial connecting interface, to connect the step of a remote-control device, so that this result is shown on this remote-control device.
14. the total line detecting method of the I2C of mainboard according to claim 13 is characterized in that, this interface connected in series is a RS-232 interface.
15. the total line detecting method of the I2C of mainboard according to claim 13 is characterized in that, this remote-control device includes a display device or a supervising device.
16. the total line detecting method of the I2C of mainboard according to claim 11 is characterized in that, this signal condition table is this signal that the I2C bus of this mainboard should transmit during the cycle in debug that prestores.
17. the total line detecting method of the I2C of mainboard according to claim 11, the step that it is characterized in that this signal of Gai Xie Code of and this analysis, see through a complicated formula programmable logic device (ComplexProgrammable Logic Device, CPLD) or see through one imitate the programmable gate array device (Field-Programmable Gate Array, FPGA).
18. the total line detecting method of the I2C of mainboard according to claim 11 is characterized in that, shows the step of this result, sees through at least one light emitting diode.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
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| CNA2006100367961A CN101114249A (en) | 2006-07-28 | 2006-07-28 | I2C bus testing apparatus of mainboard and method thereof |
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| CNA2006100367961A CN101114249A (en) | 2006-07-28 | 2006-07-28 | I2C bus testing apparatus of mainboard and method thereof |
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| CN101114249A true CN101114249A (en) | 2008-01-30 |
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| CNA2006100367961A Pending CN101114249A (en) | 2006-07-28 | 2006-07-28 | I2C bus testing apparatus of mainboard and method thereof |
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Cited By (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101887407A (en) * | 2010-07-16 | 2010-11-17 | 哈尔滨工业大学 | Hilbert-Huang transform-based equipment or system built-in test signal characteristic extraction method |
| CN102063358A (en) * | 2009-11-17 | 2011-05-18 | 鸿富锦精密工业（深圳）有限公司 | I2C (inter-integrated circuit) bus detection device |
| CN102479141A (en) * | 2010-11-30 | 2012-05-30 | 英业达股份有限公司 | Processing system for monitoring power-on self-test information |
| CN102479148A (en) * | 2010-11-30 | 2012-05-30 | 英业达股份有限公司 | System and method for monitoring input/output port state of peripheral element |
| CN103995762A (en) * | 2014-06-06 | 2014-08-20 | 山东超越数控电子有限公司 | Method for diagnosing board card fault |
| CN104572361A (en) * | 2013-10-11 | 2015-04-29 | 神讯电脑(昆山)有限公司 | Device detecting method during starting-up and computer unit thereof |
| CN107451028A (en) * | 2016-05-31 | 2017-12-08 | 佛山市顺德区顺达电脑厂有限公司 | Error condition storage method and server |
| CN110261761A (en) * | 2019-06-06 | 2019-09-20 | 福建星网智慧科技股份有限公司 | A kind of mainboard self-checking unit and method based on the detection of FPGA electric signal |
| CN113032190A (en) * | 2019-12-09 | 2021-06-25 | 圣邦微电子（北京）股份有限公司 | IIC interface time sequence parameter testing method and IIC interface time sequence parameter testing device |
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- 2006-07-28 CN CNA2006100367961A patent/CN101114249A/en active Pending
Cited By (13)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102063358A (en) * | 2009-11-17 | 2011-05-18 | 鸿富锦精密工业（深圳）有限公司 | I2C (inter-integrated circuit) bus detection device |
| CN102063358B (en) * | 2009-11-17 | 2014-08-20 | 鸿富锦精密工业（深圳）有限公司 | I2C (inter-integrated circuit) bus detection device |
| CN101887407B (en) * | 2010-07-16 | 2012-12-12 | 哈尔滨工业大学 | Hilbert-Huang transform-based equipment or system built-in test signal characteristic extraction method |
| CN101887407A (en) * | 2010-07-16 | 2010-11-17 | 哈尔滨工业大学 | Hilbert-Huang transform-based equipment or system built-in test signal characteristic extraction method |
| CN102479148A (en) * | 2010-11-30 | 2012-05-30 | 英业达股份有限公司 | System and method for monitoring input/output port state of peripheral element |
| CN102479141A (en) * | 2010-11-30 | 2012-05-30 | 英业达股份有限公司 | Processing system for monitoring power-on self-test information |
| CN104572361A (en) * | 2013-10-11 | 2015-04-29 | 神讯电脑(昆山)有限公司 | Device detecting method during starting-up and computer unit thereof |
| CN104572361B (en) * | 2013-10-11 | 2018-04-17 | 神讯电脑(昆山)有限公司 | Device method for detecting and its calculator device during start |
| CN103995762A (en) * | 2014-06-06 | 2014-08-20 | 山东超越数控电子有限公司 | Method for diagnosing board card fault |
| CN107451028A (en) * | 2016-05-31 | 2017-12-08 | 佛山市顺德区顺达电脑厂有限公司 | Error condition storage method and server |
| CN110261761A (en) * | 2019-06-06 | 2019-09-20 | 福建星网智慧科技股份有限公司 | A kind of mainboard self-checking unit and method based on the detection of FPGA electric signal |
| CN110261761B (en) * | 2019-06-06 | 2024-02-06 | 福建星网智慧科技有限公司 | Mainboard self-checking device and method based on FPGA (field programmable Gate array) electrical signal detection |
| CN113032190A (en) * | 2019-12-09 | 2021-06-25 | 圣邦微电子（北京）股份有限公司 | IIC interface time sequence parameter testing method and IIC interface time sequence parameter testing device |
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