CN102063358B - I2C (inter-integrated circuit) bus detection device - Google Patents
I2C (inter-integrated circuit) bus detection device Download PDFInfo
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- CN102063358B CN102063358B CN200910309841.XA CN200910309841A CN102063358B CN 102063358 B CN102063358 B CN 102063358B CN 200910309841 A CN200910309841 A CN 200910309841A CN 102063358 B CN102063358 B CN 102063358B
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Abstract
The invention provides an I2C (inter-integrated circuit) bus detection device. The device comprises a first trigger, an inverter, a second trigger, a microcontroller, a memory and a display interface, wherein a clear pin of the first trigger receives the clock signals output by clock lines of an I2C bus; a clock pin of the first trigger receives the data signals output by data lines of the I2C bus and outputs the first trigger signals; the input terminal of the inverter receives the data signals output by the data lines of the I2C bus and inverts the data signals; a clear pin of the second trigger receives the clock signals of the I2C bus; a clock pin of the second trigger is connected with the output terminal of the inverter to receive the inverted data signals and outputs the second trigger signals; a first interrupt pin of the microcontroller receives the first trigger signals, a second interrupt pin is connected with the second trigger signals and a third interrupt pin receives the clock signals of the I2C bus; an input pin of the microcontroller receives the data signals of the I2C bus; the memory is connected with an input/output pin of the microcontroller and is used for memorizing the data captured by the microcontroller; and the display interface is connected with an input/output pin of the microcontroller and is used for displaying the signals memorized in the memory.
Description
Technical field
The present invention relates to a kind of pick-up unit, particularly a kind of I2C bus testing apparatus.
Background technology
I2C bus is a kind of twin wire universal serial bus of being developed by PHILIPS company (comprising clock cable and data signal line), for connecting microcontroller and peripherals thereof.I2C bus resulted from the eighties, was initially audio and video equipment exploitation, nowadays mainly in server admin, used, comprising the communication of single component state.For example keeper can inquire about each assembly, with the configuration of management system or the functional status of grasp assembly, as power supply and system fan.Can monitor at any time multiple parameters such as internal memory, hard disk, network, system temperature, increase the security of system, facilitate management.
But; in I2C bus being designed or use, often can use I2C bus checkout equipment with the data-signal in testbus and clock signal; so that electronic equipment is debugged and debug according to the clock in I2C bus and data-signal; but; common I2C bus checkout equipment mostly is the design of waveform storage playback formula; need to use multi-disc storage chip and corresponding coding and decoding circuit, circuit structure complexity, cost is high.
Summary of the invention
In view of foregoing, the invention provides the I2C bus testing apparatus that a kind of circuit structure is simple, cost is low, so that the signal of I2C bus transmission is detected.
A kind of I2C bus testing apparatus, for the signal on clock cable and the data signal line of an I2C bus is detected, described I2C bus testing apparatus comprises:
One first trigger, the removing pin of described the first trigger receives the clock signal of the clock line output of described I2C bus, the clock pin of described the first trigger receives the data-signal of the data line output of described I2C bus, and according to described clock signal and data-signal output one first trigger pip;
One phase inverter, the input end of described phase inverter receives the data-signal of the data line output of described I2C bus, and by described data-signal upset;
One second trigger, the removing pin of described the second trigger receives the clock signal of the clock line output of described I2C bus, the clock pin of described the second trigger connects the output terminal of described phase inverter to receive the data-signal of described phase inverter upset, and described the second trigger is according to data-signal output one second trigger pip of described clock signal and the upset of described phase inverter;
One microcontroller, the first interrupt pin of described microcontroller connects the output terminal of described the first trigger to receive described the first trigger pip, the second interrupt pin of described microcontroller connects the output terminal of described the second trigger to receive described the second trigger pip, the 3rd interrupt pin of described microcontroller receives the clock signal of the clock line output of described I2C bus, and an input pin of described microcontroller receives the data-signal of the data line output of described I2C bus;
One connects the storer of an input and output pin of described microcontroller, the data-signal of catching for storing described microcontroller; And
One connects the display interface of an input and output pin of described microcontroller, for connecting the signal of a display device to show that described storer is stored;
Described first, second trigger receives clock signal and the data-signal of I2C bus output to be measured, and give described microcontroller according to described clock signal and the corresponding output of data-signal trigger pip, so that described microcontroller enables corresponding interruption and catch clock signal and the data-signal in I2C bus, and described clock signal and data-signal are stored in described storer and are presented on the display device being connected with described display interface.
Compare prior art, described I2C bus testing apparatus receives clock signal and the data-signal of I2C bus output to be measured by described first, second trigger, and give described microcontroller according to described clock signal and the corresponding output of data-signal trigger pip, so that described microcontroller enables corresponding interruption and catch clock signal and the data-signal in I2C bus, and described clock signal and data-signal are stored in described storer and are presented on the display device being connected with described display interface.Described I2C bus testing apparatus circuit structure is simple, cost is low.
Brief description of the drawings
In conjunction with embodiment, the invention will be further described with reference to the accompanying drawings.
Fig. 1 is the schematic diagram of the preferred embodiments of I2C bus testing apparatus of the present invention.
Fig. 2 is the schematic block circuit diagram of the preferred embodiments of I2C bus testing apparatus of the present invention.
Embodiment
Please jointly with reference to Fig. 1 and Fig. 2, the preferred embodiments of I2C bus testing apparatus of the present invention comprise a housing 10, a connector being connected with described housing 10 20, be arranged at display interface 30 on described housing 10 as VGA interface and be arranged at as described in housing 10 inner and with as described in the testing circuit 40 that is connected of connector 20 and display interface 30.Described connector 20 is for connecting the connector of I2C bus to be detected on an electronic equipment mainboard, described connector 20 comprises clock pin SCL and data pin SDA, be respectively used to connect clock cable in described I2C bus and data signal line to receive clock signal and the data-signal on it, described display interface 30 is for connecting a display device, showing through described testing circuit 40 testing result after treatment, so that testing staff can learn the problem existing on electronic equipment mainboard accurately.
In other embodiments, described housing 10 can be also the carrier that a circuit board or other can arrange circuit, described connector 20 also can for other can collection signal structure as probe structure, when collection signal as long as two probes are contacted with clock cable and data signal line in described I2C bus.Described display interface 30 can be the interface of other types, and above-mentioned design all can be adjusted as required, is not limited to present embodiment.
Described testing circuit 40 comprises two d type flip flops 41 and 42, a phase inverter 43, a microcontroller 44 and a storer 45.Described trigger 41,42 receives respectively the clock signal of clock pin SCL output and the data-signal of described data pin SDA output of described connector 20, and give described microcontroller 44 according to described clock signal and the corresponding output of data-signal trigger pip, so that described microcontroller 44 enables corresponding interruption and catch clock signal and the data-signal in I2C bus, and described clock signal and data-signal are stored in described storer 45 and by described display interface 30 and are presented on described display device.
The clock pin SCL of described connector 20 connects respectively trigger 41, the 3rd interrupt pin INT3 of 42 removing pin CLR and described microcontroller 44, the data pin SDA of described connector 20 connects respectively the clock pin CLK of trigger 41, the input pin INPUT of described microcontroller 44 and the input end of described phase inverter 43, the output terminal of described phase inverter 43 connects the clock pin CLK of described trigger 42, the output terminal Q of described trigger 41 connects the first interrupt pin INT1 of described microcontroller 44, the output terminal Q of described trigger 42 connects the second interrupt pin INT2 of described microcontroller 44, two input and output pin I/O of described microcontroller 44 are connected respectively described storer 45 and described display interface 30.
When work, described connector 20 is connected with the corresponding connector of I2C bus to be collected, described microcontroller 44 is connected with described display device by described display interface 30.When the clock signal of the clock pin SCL of described connector 20 output is high level, and when the data-signal of the data pin SDA of described connector 20 output does not change, described trigger 41,42 is not worked, the 3rd interrupt pin INT3 of described microcontroller 44 receives described high level signal and enables to interrupt, and now described microcontroller 44 is caught the data-signal in I2C bus by described input pin INPUT and is stored in described storer 45 and is presented on described display device by described display interface 30, when the data-signal of the data pin SDA output of described connector 20 is during in negative edge, the clock pin CLK of described trigger 41 receives described negative edge signal and does not work, described phase inverter 43 by the upset of described negative edge signal for rising edge signal and offer described trigger 42 clock pin CLK so that described trigger 42 work, the second interrupt pin INT2 of described microcontroller 44 receive described trigger 42 output terminal Q output rising edge signal and enable to interrupt, now described microcontroller 44 is caught in I2C bus the start status signal in data-signal and is stored in described storer 45 and is presented on described display device by described display interface 30, when the data-signal of the data pin SDA output of described connector 20 is during in rising edge, described phase inverter 43 is negative edge signal the clock pin CLK that offers described trigger 42 by described rising edge signal upset, the clock pin CLK of described trigger 42 receives described negative edge signal and does not work, the clock pin CLK of described trigger 41 receives the work of described rising edge signal, the first interrupt pin INT1 of described microcontroller 44 receive described trigger 41 output terminal Q output rising edge signal and enable to interrupt, now described microcontroller 44 is caught in I2C bus the stop status signal in data-signal and is stored in described storer 45 and is presented on described display device by described display interface 30.Tester can learn according to the testing result showing on described display device the problem existing on electronic equipment mainboard accurately, thereby completes fast and accurately debugging or the debug of electronic equipment.
I2C bus testing apparatus of the present invention receives clock signal and the data-signal of I2C bus output to be measured by described first, second trigger 41,42, and give described microcontroller 44 according to described clock signal and the corresponding output of data-signal trigger pip, so that described microcontroller 44 enables corresponding interruption and catch clock signal and the data-signal in I2C bus, and described clock signal and data-signal are stored in described storer 43 and are presented on the display device being connected with described display interface 30.Described I2C bus testing apparatus can detect the I2C bus on electronic equipment mainboard automatically, and testing result is shown to tester by described display device, thereby the debugging or the debug mistake that in measurement signal process, cause due to human negligence factor are avoided.Described I2C bus testing apparatus circuit structure is simple, cost is low.
Claims (4)
1. an I2C bus testing apparatus, for the signal on clock cable and the data signal line of an I2C bus is detected, described I2C bus testing apparatus comprises:
One first trigger, the removing pin of described the first trigger receives the clock signal of the clock line output of described I2C bus, the clock pin of described the first trigger receives the data-signal of the data line output of described I2C bus, and according to described clock signal and data-signal output one first trigger pip;
One phase inverter, the input end of described phase inverter receives the data-signal of the data line output of described I2C bus, and by described data-signal upset;
One second trigger, the removing pin of described the second trigger receives the clock signal of the clock line output of described I2C bus, the clock pin of described the second trigger connects the output terminal of described phase inverter to receive the data-signal of described phase inverter upset, and described the second trigger is according to data-signal output one second trigger pip of described clock signal and the upset of described phase inverter;
One microcontroller, the first interrupt pin of described microcontroller connects the output terminal of described the first trigger to receive described the first trigger pip, the second interrupt pin of described microcontroller connects the output terminal of described the second trigger to receive described the second trigger pip, the 3rd interrupt pin of described microcontroller receives the clock signal of the clock line output of described I2C bus, and an input pin of described microcontroller receives the data-signal of the data line output of described I2C bus;
One connects the storer of an input and output pin of described microcontroller, the data-signal of catching for storing described microcontroller; And
One connects the display interface of an input and output pin of described microcontroller, for connecting the signal of a display device to show that described storer is stored;
Described first, second trigger receives clock signal and the data-signal of I2C bus output to be measured, and give described microcontroller according to described clock signal and the corresponding output of data-signal trigger pip, so that described microcontroller enables corresponding interruption and catch clock signal and the data-signal in I2C bus, and described clock signal and data-signal are stored in described storer and are presented on the display device being connected with described display interface.
2. I2C bus testing apparatus as claimed in claim 1, it is characterized in that: the clock signal that receives the clock line output of described I2C bus when the removing pin of described the first trigger is high level signal, and when the data-signal that the clock pin of described the first trigger receives the data line output of described I2C bus does not change, described first and second trigger is not worked, the 3rd interrupt pin of described microcontroller receives described high level signal and enables to interrupt, now described microcontroller is caught the data-signal in I2C bus and is stored in described storer and by described display interface by described input pin and is presented on described display device, the data-signal of data line output that receives described I2C bus when the clock pin of described the first trigger is during in negative edge, the clock pin of described the first trigger receives described negative edge signal and does not work, described phase inverter by the upset of described negative edge signal for rising edge signal the clock pin that offers described the second trigger are so that described the second flip-flop operation, the second interrupt pin of described microcontroller receives the second trigger pip of described the second trigger output and enables to interrupt, now described microcontroller is caught in I2C bus the start status signal in data-signal and is stored in described storer and by described display interface and is presented on described display device, the data-signal of data line output that receives described I2C bus when the clock pin of described the first trigger is during in rising edge, described phase inverter is negative edge signal the clock pin that offers described the second trigger by described rising edge signal upset, the clock pin of described the second trigger receives described negative edge signal and does not work, the clock pin of described the first trigger receives the work of described rising edge signal, the first interrupt pin of described microcontroller receives first of described the first trigger output and triggers trigger pip and enable to interrupt, now described microcontroller is caught in I2C bus the stop status signal in data-signal and is stored in described storer and by described display interface and is presented on described display device.
3. I2C bus testing apparatus as claimed in claim 1, is characterized in that: it is to be connected on the connector of described I2C bus and to be realized by a connector that described the first trigger and the second trigger receive signal on clock cable and the data signal line of described I2C bus.
4. I2C bus testing apparatus as claimed in claim 1, is characterized in that: described first and second trigger is d type flip flop.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN200910309841.XA CN102063358B (en) | 2009-11-17 | 2009-11-17 | I2C (inter-integrated circuit) bus detection device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN200910309841.XA CN102063358B (en) | 2009-11-17 | 2009-11-17 | I2C (inter-integrated circuit) bus detection device |
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| Publication Number | Publication Date |
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| CN102063358A CN102063358A (en) | 2011-05-18 |
| CN102063358B true CN102063358B (en) | 2014-08-20 |
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| CN200910309841.XA Expired - Fee Related CN102063358B (en) | 2009-11-17 | 2009-11-17 | I2C (inter-integrated circuit) bus detection device |
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Families Citing this family (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102841838B (en) * | 2011-06-21 | 2015-07-22 | 英业达股份有限公司 | Device, system and method for automatically detecting inter-integrated circuit (I2C) and SGPIO (serious general-purpose input/output) |
| CN102314403B (en) * | 2011-08-26 | 2013-12-11 | 苏州佳世达电通有限公司 | Device and method for identifying I2C (Inter-Integrated Circuit) bus signal by taking MCU (Micro Control Unit) as slave device |
| CN110971219A (en) * | 2019-12-31 | 2020-04-07 | 歌尔微电子有限公司 | Pressure sensor, switch circuit thereof, clock control method and clock control device |
| CN112710917A (en) * | 2021-01-04 | 2021-04-27 | 中车青岛四方车辆研究所有限公司 | Debugging system and debugging method for rail vehicle electronic equipment |
| CN115100996B (en) * | 2022-07-21 | 2022-12-13 | 北京数字光芯集成电路设计有限公司 | Display configuration circuit, method, micro display panel and electronic device |
| CN114996196B (en) * | 2022-08-04 | 2022-10-21 | 北京数字光芯集成电路设计有限公司 | I2C communication drive circuit, micro display chip and electronic equipment |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1991783A (en) * | 2005-12-29 | 2007-07-04 | 国际商业机器公司 | 12c bus monitor and method for detecting and correcting hanged 12c bus |
| CN101114249A (en) * | 2006-07-28 | 2008-01-30 | 佛山市顺德区顺达电脑厂有限公司 | I2C bus testing apparatus of mainboard and method thereof |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7721155B2 (en) * | 2007-06-27 | 2010-05-18 | International Business Machines Corporation | I2C failure detection, correction, and masking |
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Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1991783A (en) * | 2005-12-29 | 2007-07-04 | 国际商业机器公司 | 12c bus monitor and method for detecting and correcting hanged 12c bus |
| CN101114249A (en) * | 2006-07-28 | 2008-01-30 | 佛山市顺德区顺达电脑厂有限公司 | I2C bus testing apparatus of mainboard and method thereof |
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