201107770 六、發明說明： 【發明所屬之技術領域】 [0001] 本發明涉及一種連接器測試裝置’尤指一種貼裝記情體 連接器測試裝置。 [先前技術]201107770 VI. Description of the Invention: [Technical Field of the Invention] [0001] The present invention relates to a connector testing device, particularly a mounting device connector test device. [Prior technology]
[0002] 隨著主機板架構及技術之發展，主機板上之記憶體連接 器逐漸由過去之插件記憶體連接器發展為貼裝記憶體連 接器。現今’越來越多之高端電子產品開始使用貼装記 憶體連接器。對應地’電子產品上之記憶體插槽亦逐漸 由插件記憶體槽發展為貼裝記憶體槽V由於記憶體連接 器針腳數量多、封裝精密、體積大，因％給生產制程與 測試帶來了較大之困難。尤指於對連接器針腳焊點之開 路以及短路測試時’傳統之ICT (In Current Test) 測試由於沒有測試點因此測試不了該種貼裝連接器而 飛針測試由於容易造成連接器針腳之損壞，因而亦無法 對貼裝記憶體連接器進行測試，業养暫時沒有這類連接 器之測試設備。[0002] With the development of motherboard architecture and technology, the memory connector on the motherboard has gradually evolved from the past plug-in memory connector to the placement memory connector. Today, more and more high-end electronic products are beginning to use placement memory connectors. Correspondingly, the memory slot on the electronic product has gradually evolved from the plug-in memory slot to the mounted memory slot. V. Due to the large number of memory connector pins, the package is precise and bulky, due to the production process and testing. A big difficulty. Especially in the open circuit and short circuit test of the connector pin solder joints, the traditional ICT (In Current Test) test can not test the mount connector because there is no test point, and the flying probe test is easy to cause damage to the connector pins. Therefore, it is impossible to test the mounted memory connector, and there is no test equipment for such a connector.
. . ：. . 【發明内容】 _]鑒於以上内容，有必要提供-種貼裝記憶體連接器測試 裝置。 _4]-種貼裝—體連接H測試裝置，用於對—待測主機板 上之貼裝記憶體連接H進行測試，包括—主控電路、分 別與該主控電路電性相連之至少—資料獲取電路、及一 顯示單元’該主控電路中存儲有正常之貼裝記憶體連接 器之針聊資m，該至少一資料獲取電路與該至少—貼裝 098128333 表單編號A0101 第4頁/共20頁 0982048660-0 201107770 記憶體連接崎應連接以採集賴裝記憶體連接器之針 腳資訊’該主控電路藉由該資料獲取電路控制該貼裝記 憶體連接器之針腳接收來自該資料獲取電路之資料該 資料獲取電路採集該貼裝記憶體連接器針腳接收之資料 並傳送給該主控電路，該主控電路將採集到之資料與正 常之針腳資訊進行比較，並將比較結果顯示於該顯示單 元上提示待測主機板上之陣列型連接器之針腳是否正常 〇 〇 [0005]優選地，該資料獲取電路向該貼裝記憶體連接器之對應 針腳發送兩次相反之資料，如果該記憶體連接器之針腳 兩次接收到之資料均與資料獲取電路發送之資料—致， 則該記憶體連接器之針腳正常，如果兩次接收之資料與 資料獲取電路發送之資料不同，則該針腳異常。 [0006] 優選地，該資料獲取電路包括一複雜可编程邏輯器件， 該複雜可編程邏輯器件包括複數資料獲取引腳、一資料 傳送引腳及至少一時鐘引腳，該資料獲取引腳分別電性 〇 連接待測主機板上之貼裝記憶體連接器針聊並採集針聊 資訊，該複雜可編程邏輯器件對採集到之針腳資訊進行 處理後由資料傳送輸出至該主控電路。 [0007] 優選地’該資料獲取電路還包括一與該複雜可編程邏輯 器件及該主控電路連接之電壓信號採集單元，該電壓俨 號採集單元採集該貼裝記憶體連接器針腳之電壓作號並 發送至該k控電路。 [0008] 優選地，該電壓信號採集單元包括複數電壓信號採集引 098128333 表單編號A0101 第5頁/共頁 0982048660-0 201107770 腳、一第一資料傳送引腳、一第二資料傳送引腳、一第 一時鐘引腳、一第二時鐘引腳，該第一資料傳送引腳與 該複雜可編程邏輯器件之資料傳送引腳相連，該第一時 鐘引腳與該複雜可編程邏輯器件之時鐘引腳相連，該電 壓信號採集引腳分別電性連接待測主機板上之貼裝記憶 體連接器針腳以採集電壓資訊，該複雜可編程邏輯器件 對採集到之針腳資訊進行處理後由該第二資料傳送引腳 輸出至該主控電路。 [0009] 優選地，該電壓信號採集單元還包括一第三資料傳送引 腳及一第三時鐘引腳，該存儲單元包括一電可擦可編程 唯讀記憶體，該電可擦可編程唯讀記憶體包括一串列資 料引腳、一串列時鐘引腳及一防寫引腳，該第三資料傳 送引腳與第三時鐘引腳分別連接該串列資料引腳與串列 時鐘引腳，該防寫引腳經由一跳帽接地。 [0010] 優選地，該主控電路包括一微控制器，該微控制器包括 一資料傳送引腳及一時鐘引腳，該微控制器之資料傳送 引腳與時鐘引腳分別連接該電壓信號採集單元之第二資 料傳送引腳與第二時鐘引腳，該微控制器藉由該資料傳 送引腳及時鐘引腳控制該電壓信號採集單元採集電壓信 號。 [0011] 優選地，該微控制器具有複數並行資料傳送引腳，該主 控電路還包括一與該微控制器連接之通用串列介面解析 電路及與該通用串列介面解析電路電性連接之通用串列 介面，該通用串列介面解析電路具有複數並行資料引腳 ，該通用串列介面解析電路之並行資料引腳分別與該微 098128333 表單編號 A0101 第 6 頁/共 20 頁 0982048660-0 201107770 [0012] 控制器之並行資料傳送⑽對應連接⑼ 該通用串列介面與微控制器之間之串並/並串轉換貝。，於 優選地’該顯示單元藉由該相_ 實現資料傳輪。 …亥微控制器 [0013] 優選地’每-信號採集電路之第二資料傳㈤丨腳 _對應連接至該微控制器之f料傳送引腳及： [0014] Ο 相較於習知技術，本發明貼裝記憶體連接器㈣ 由該主控電路控制資料獲取電路對該賴記憶體連接^ 之各個針腳進行測試，避免了傳統測試治具對 體連接器針腳之損壞。 ' ^己憶 [0015] 【實施方式】 請參閱圖卜本發明貼裝記憶體連接器測試裝置較佳實施 方式包括-待測主機板10、-資料獲取電路3〇、—主控 電路5〇、及—_單元6Q :該細主_ig上設定碰 Ο 個貼裝記憶鱧連接器20。該記憶體連接器2〇具有複數個 針腳B卜Bn及IHn (見圖4)。該資料獲取電路3〇與該 貼裝記憶體連接器20電性連接以採集該貼裝記憶體連接 器20之針腳資訊’並將採制之針腳資訊傳送給該主控 電路50。該主控f：路50中存儲有正常之針腳資訊。該顯 示單元60與該主控電路50相連。該主控電路5〇將採集到 針腳資訊進行比較處理後得出測試結果，並將該測試結 果發送至顯示單元60顯示。 [0016] 請參閱圖2及圖3，該主控電路5〇包括一通用串列（USB) 098128333 表單舰A0101 第7頁/共20頁 098204删0-0 201107770 介面J1、一 USB解析電路U1、及一微控制器U3。 [0017] [0018] 請參閱圖2，該USB解析電路U1具有複數並行資料引腳 E0〜En，複數控制引腳R、W、TXE、RXF，複數電源引腳 VCC、AVCC ’接地引腳GND，振盪信號輸入端x〇1、XI1 。該USB介面J1具有電源端VCC，接地端GND，及兩個信 號傳輸端DN、DP。該USB介面J1之電源端藉由一電感[與 該USB解析電路U1之其中兩個電源引腳vcc、AVCC相連， 並經由一跳帽J2連接至顯示單元6〇提供之一USB電源us_ BV1。該USB解析電路U1之另一電源引腳vcc連接至一 3. 3V工作電源。該振'盡信號輸入:端、m經由一gw之 晶振J3接地。該USB介面J1之兩個信號傳輸端]、⑽分 別與該USB解析電路U1之信號傳輸引腳此、USBp及一 復位引腳RSTO連接。該顯示單元6〇藉由該USB介面；1與 該USB解析電路U1連接並實現資料傳輸。該USB解析電路 U1還具有一時鐘引腳ESK、一資料傳輸引_DATA、及一 片選端ECS。該USB解析電路U1藉由該時鐘引腳esk、資 料引腳DATA、及片選端ECS與一第一存儲單元μ連接。 s亥資料引腳DATA藉由兩個電阻連接至該usb電源usbvi。 該第一存儲單元U2用以存儲該USB模組之1〇等相關資訊。 請參閱圖3，該微控制器U3具有與該USB解析電路U1對應 之複數並行資料引腳DO~Dn及控制引腳r、w、TXE、RXF ，s^USB解析電路U1藉由該並行資料引腳D〇 I)n及控制引 腳R、W、TXE、RXF與該微控制器U3連接，從而將，介 面J1傳送之串列資料轉換為並行資料傳送給該微控制器 U3，並將微控制器U3傳送之並行資料轉換為串列資料傳 098128333 表單編號A0101 第8頁/共20頁 0982048660-0 201107770 送至USB介面ji。該USB介面j丨再將資料傳送至顯示單元 6〇顯示。該微控制器U3還具有複數程式燒錄引腳MCLR、 PGD、PGC ’振盧信號輸入引腳0SC1、0SC2，電源引腳 VDD，接地引腳vss，一時鐘引腳C1，一資料傳輸引腳匸2 。該振盪信號輸入引腳0CS1、0CS2經由一 ι2Μ之晶振J4 及兩個電容接地。該時鐘引腳Cl及資料傳輸引腳C2分別 與一資料傳輸連接器J8之時鐘信號端CLK及資料信號端 DATA連接，並分別藉由一電阻連接至3. ”電源。。 〇 [0019]請參閱圖4及圖5，該資料獲取電路3〇包括一複雜可編程 邏輯器件U5、一電壓信號採集單元ϋ6，及一與該電壓信 號採集單元U6電性連接之第二存儲單元训。 [0020]請參閱圖4，該複雜可編程邏輯器件[|5包括複數資料獲取 引腳Α卜An、Bn、複數振盪信號輸入引腳CLK〇~CLK3、 一時鐘引腳S1、一資料傳送引腳S2、複數程式燒入引腳 TD0 ' m、TMS、TCK、複數控制引腳G卜Gn、複數電源 引腳VCC1〜VCCn及複數接地引腳GN]M〜GNDn。該複數資 〇 料獲取引腳Al~An分別連接至該貼裝記憶體連接器2〇之針 腳Bl〜Bn。該振盪信號輸入引腳CLK〇〜CLK3連接至一個 25M之晶振J5。該複數電源引腳vcci〜vccn連接該& 3V 電源，該複數接地引腳GNDl~GNDn接地。 [0021]. . . . . . . . . . . . . _] In view of the above, it is necessary to provide a mounting memory connector test device. _4]--mounting-body connection H test device for testing the mounting memory connection H on the motherboard to be tested, including - the main control circuit, respectively electrically connected to the main control circuit - a data acquisition circuit, and a display unit, wherein the main control circuit stores a normal placement memory connector, the at least one data acquisition circuit and the at least-mounting 098128333 form number A0101, page 4/ A total of 20 pages 0982048660-0 201107770 Memory connection should be connected to collect the pin information of the attached memory connector. The main control circuit controls the pin of the mounted memory connector to receive the data from the data acquisition circuit. The data acquisition circuit collects the data received by the pin of the mounted memory connector and transmits the data to the main control circuit, and the main control circuit compares the collected data with the normal pin information, and displays the comparison result on The display unit indicates whether the stitch of the array type connector on the motherboard to be tested is normal. [0005] Preferably, the data acquisition circuit connects to the mounting memory. The corresponding pin of the device sends the opposite data twice. If the data received by the pin of the memory connector is the same as the data sent by the data acquisition circuit, the pin of the memory connector is normal, if it is received twice The data is different from the data sent by the data acquisition circuit. [0006] Preferably, the data acquisition circuit comprises a complex programmable logic device comprising a plurality of data acquisition pins, a data transmission pin and at least one clock pin, wherein the data acquisition pins are respectively powered The 〇 connects to the mounted memory connector on the motherboard to be tested and collects the pin chat information. The complex programmable logic device processes the collected pin information and outputs the data to the main control circuit. [0007] Preferably, the data acquisition circuit further includes a voltage signal acquisition unit connected to the complex programmable logic device and the main control circuit, and the voltage reference acquisition unit collects the voltage of the pin of the mounted memory connector. The number is sent to the k control circuit. [0008] Preferably, the voltage signal acquisition unit includes a plurality of voltage signal acquisition instructions 098128333 Form No. A0101 Page 5 / Total Page 0982048660-0 201107770 Foot, a first data transmission pin, a second data transmission pin, a a first clock pin, a second clock pin, the first data transfer pin is connected to a data transfer pin of the complex programmable logic device, and the first clock pin and the clock of the complex programmable logic device The voltage signal acquisition pins are electrically connected to the mounting memory connector pins of the motherboard to be tested to collect voltage information, and the complex programmable logic device processes the collected pin information by the second The data transfer pin is output to the main control circuit. [0009] Preferably, the voltage signal acquisition unit further includes a third data transmission pin and a third clock pin, the storage unit includes an electrically erasable programmable read only memory, the electrically erasable programmable only The read memory includes a serial data pin, a serial clock pin and an anti-write pin, and the third data transfer pin and the third clock pin are respectively connected to the serial data pin and the serial clock reference The pin, the anti-write pin is grounded via a jump cap. [0010] Preferably, the main control circuit includes a microcontroller, the micro controller includes a data transmission pin and a clock pin, and the data transmission pin and the clock pin of the microcontroller are respectively connected to the voltage signal. The second data transmission pin of the acquisition unit and the second clock pin, the microcontroller controls the voltage signal acquisition unit to collect the voltage signal by using the data transmission pin and the clock pin. [0011] Preferably, the microcontroller has a plurality of parallel data transfer pins, and the main control circuit further includes a universal serial interface analysis circuit connected to the microcontroller and electrically connected to the universal serial interface analysis circuit. The universal serial interface, the universal serial interface analysis circuit has a plurality of parallel data pins, and the parallel data pins of the universal serial interface analysis circuit are respectively associated with the micro 098128333 form number A0101 page 6 / 20 pages 0982048660-0 201107770 [0012] Parallel data transfer (10) of the controller corresponds to the connection (9) serial/parallel conversion between the universal serial interface and the microcontroller. Preferably, the display unit implements data transfer by the phase. ...Hui Microcontroller [0013] Preferably, the second data transmission of each signal acquisition circuit (five) is corresponding to the f material transfer pin of the microcontroller and: [0014] Ο compared to the prior art The mounting memory connector of the present invention (4) is controlled by the main control circuit to control the data acquisition circuit to test the respective pins of the memory connection, thereby avoiding the damage of the traditional test fixture to the body connector pins. [Comprehensive] Please refer to FIG. 2 for a preferred embodiment of the present invention. The preferred embodiment of the device for mounting a memory connector includes a motherboard to be tested 10, a data acquisition circuit 3, and a master control circuit. , and -_ unit 6Q: The thin master _ig is set to touch the placement memory 鳢 connector 20. The memory connector 2 has a plurality of pins Bb and IHn (see Fig. 4). The data acquisition circuit 3 is electrically connected to the mounted memory connector 20 to collect the pin information of the mounted memory connector 20 and transmits the acquired pin information to the main control circuit 50. The master f: the path 50 stores normal pin information. The display unit 60 is connected to the main control circuit 50. The main control circuit 5 〇 collects the pin information for comparison processing to obtain a test result, and sends the test result to the display unit 60 for display. [0016] Please refer to FIG. 2 and FIG. 3, the main control circuit 5 includes a universal serial (USB) 098128333 form ship A0101 page 7 / total 20 pages 098204 delete 0-0 201107770 interface J1, a USB analysis circuit U1 And a microcontroller U3. [0018] Referring to FIG. 2, the USB analysis circuit U1 has a plurality of parallel data pins E0 to En, a plurality of control pins R, W, TXE, RXF, a plurality of power supply pins VCC, and an AVCC 'ground pin GND. , the oscillating signal input terminals x 〇 1, XI1. The USB interface J1 has a power supply terminal VCC, a ground terminal GND, and two signal transmission terminals DN and DP. The power supply terminal of the USB interface J1 is connected to one of the two power supply pins vcc and AVCC of the USB analysis circuit U1, and is connected to the display unit 6 via a jump cap J2 to provide a USB power supply us_BV1. The other power supply pin vcc of the USB analysis circuit U1 is connected to a 3. 3V working power supply. The vibration 'output signal: the end, m is grounded via a gw crystal oscillator J3. The two signal transmission terminals of the USB interface J1 and (10) are respectively connected to the signal transmission pins of the USB analysis circuit U1, the USBp and a reset pin RSTO. The display unit 6 is connected to the USB resolution circuit U1 by the USB interface; and realizes data transmission. The USB parsing circuit U1 also has a clock pin ESK, a data transfer pin DATA, and a chip select terminal ECS. The USB analysis circuit U1 is connected to a first memory unit μ by the clock pin esk, the data pin DATA, and the chip select terminal ECS. The s-data pin DATA is connected to the usb power usbvi by two resistors. The first storage unit U2 is configured to store related information such as the USB module. Referring to FIG. 3, the microcontroller U3 has a plurality of parallel data pins DO~Dn and control pins r, w, TXE, RXF corresponding to the USB analysis circuit U1, and the USB analysis circuit U1 uses the parallel data. The pin D〇I)n and the control pins R, W, TXE, RXF are connected to the microcontroller U3, thereby converting the serial data transmitted by the interface J1 into parallel data and transmitting to the microcontroller U3, and The parallel data transmitted by the microcontroller U3 is converted into serial data transmission 098128333 Form No. A0101 Page 8 / Total 20 pages 0982048660-0 201107770 Send to the USB interface ji. The USB interface then transfers the data to the display unit 6〇. The microcontroller U3 also has a plurality of program programming pins MCLR, PGD, PGC 'Amp signal input pins 0SC1, 0SC2, power pin VDD, ground pin vss, a clock pin C1, a data transmission pin匸2. The oscillation signal input pins 0CS1 and 0CS2 are grounded via a crystal oscillator J4 and two capacitors. The clock pin C1 and the data transmission pin C2 are respectively connected to the clock signal terminal CLK and the data signal terminal DATA of a data transmission connector J8, and are respectively connected to the 3." power supply by a resistor. 〇[0019] Referring to FIG. 4 and FIG. 5, the data acquisition circuit 3 includes a complex programmable logic device U5, a voltage signal acquisition unit ϋ6, and a second storage unit that is electrically connected to the voltage signal acquisition unit U6. [0020 Please refer to FIG. 4, the complex programmable logic device [|5 includes a plurality of data acquisition pins, An, Bn, a plurality of oscillation signal input pins CLK〇~CLK3, a clock pin S1, and a data transfer pin S2. The plurality of programs are burned into the pins TD0 'm, TMS, TCK, the complex control pins Gb Gn, the plurality of power supply pins VCC1 to VCCn, and the plurality of ground pins GN]M~GNDn. The plurality of materials are obtained by the pin Al. ~An is respectively connected to the pins B1 to Bn of the mounting memory connector 2. The oscillation signal input pins CLK〇~CLK3 are connected to a 25M crystal oscillator J5. The complex power supply pins vcci~vccn are connected to the & 3V power supply, the complex ground pin GNDl~GNDn is grounded. 0021]
請參閱圖5，該電壓信號採集單元U6包括複數電壓採集引 腳F1〜Fn，複數控制引腳H1〜Hn，複數程式燒入引腳PGD 、PGC、MCLF，兩個振盪信號輸入引腳〇scl、〇SC2。一 第一時鐘引腳Ml，一第一資料傳送引腳M2，一第二時鐘 098128333 引腳SCL，一第二資料傳送弓丨腳SDA，電源引腳VDD 表單編號A0101 第9頁/共2〇頁 ，接 0982048660-0 201107770 地弓丨腳VSS。該電壓採集引分別連接至該貼裝記 憶體連接器20之針腳IWn。該兩個錢信號輪入引腳 0SC1、0SC2連接至-12M之晶振j10。該第一時鐘引腳 Ml連接至該複雜可編程邏輯器件仍之時鐘弓_卜該第 一資料傳送引腳M2連接至該複雜可編程邏輯器件卯^資 料傳送引腳。該第二時鐘引腳SCL連接至該資料傳輪連接 器J8之時鐘信號端CLK，言玄第二時鐘引腳SM連接至該資 料傳輸連接器J8之資料信號端data。如此，該電齡號 採集單搞即可藉由該資料傳輸連接㈣連接至該微控 ^ 制器U3。 / ..： .... ....Referring to FIG. 5, the voltage signal acquisition unit U6 includes a plurality of voltage acquisition pins F1 to Fn, a plurality of control pins H1 to Hn, a plurality of program burn-in pins PGD, PGC, MCLF, and two oscillation signal input pins 〇scl 〇SC2. A first clock pin M1, a first data transfer pin M2, a second clock 098128333 pin SCL, a second data transfer pin SDA, a power pin VDD form number A0101 page 9 / 2 Page, pick up 0982048660-0 201107770. The voltage acquisition leads are respectively connected to the pins IWn of the placement memory connector 20. The two money signals are clocked into pins 0SC1, 0SC2 and connected to -12M crystal oscillator j10. The first clock pin M1 is connected to the complex programmable logic device. The first data transfer pin M2 is connected to the complex programmable logic device. The second clock pin SCL is connected to the clock signal terminal CLK of the data transmission wheel connector J8, and the second clock pin SM is connected to the data signal terminal data of the data transmission connector J8. In this way, the electric meter number acquisition unit can be connected to the micro controller U3 through the data transmission connection (4). / ..: .... ....
[_該第二存儲單满為-電可擦可編程唯讀記憶體。該電 可擦可編程唯讀記憶麵包括一串列時鐘引腳似、一串 列資料引腳SDA及-防寫引腳wp。該串列時鐘_cl與 串列資料引腳SM連接至該電壓信號採集單元％，該防寫 引腳WP經由一跳帽J9接地。當短接該跳帽j9時可對電可 擦可編程唯讀記憶體U8進_入資訊之操作，而♦斷開 該跳㈣時禁止對電可擦可缚程唯讀記憶_進:擦除 資訊之操作。 _㈣時，按照圖卜5麻連接該貼裝記憶體連接器測試裝 置，該複雜可編程邏輯器件仍之資料獲取引㈣，分別 採集待測主機板1〇上之貼裝記憶體連接器20之針腳資訊 ，並將採集到之針㈣訊進行處理後^資料發送引腳S1 經由«㈣㈣單元之第—資料發送引腳_送給該 電壓信號採集單元U6。同時，該電壓信號採集單元⑽之 電壓信號採集引腳F1〜Fn採集待測主機板1〇上之貼裝記憶 098128333 表單編號A0101 第1〇頁/共2〇頁 201107770 體連接器20之電壓信號資訊。該電壓信號採集單元嶋 電壓信號資訊及複雜可編程邏輯器件卯採集到之針腳資 訊發送至該第二存儲單元_。該微控制_從該第二 存铸單it财讀取該針腳資訊及錢電_訊並與正常 之針聊資訊進行比較，然後將比較結果發送至該顯示單 心〇上以㈣❹】域㈣上之貼裝記㈣連接器之 針聊是否正常。 [_該多個資料獲取電路3〇之電㈣號採集單元⑽之時鐘引 〇 腳SCL及資料傳輸引腳SI)A均藉由該資料傳輸連接器_ 接至該微控制器U3之時鐘引腳C1及資料傳送引腳以。該 微控制器U3與該資料獲取電賴之間，該f料獲取電路 3〇與該貼裝記憶體連接器2〇之間藉由雙向資料傳送之方 式進行通訊。測試時，該微控制器U3藉由該多個資料獲 取電路3D分別控制對應之貼裝記憶體連接㈣之針腳從 該資料獲取電路30接收資料。„料獲取電賴分別發 送兩次相反之資料至該貼裝記憶體連接器20之對應針腳 〇 。如果該貼裝記憶體速接器20之針腳兩次接收到之資料 均與該資料獲取電路3〇發送之f料—致，則貼裝記憶體 連接器20之針腳jLf ;㈣，貼裝記㈣連接㈣之針 腳異常。該資料獲取電路30採集該貼震記憶體連接器2〇 各個針腳之資訊發送給該微控制器U3。該微控制器旧將 該資料與正常之針腳資訊進行比較，並將比較結果藉由 該USB解析電路U1轉換為串列資料，經由該腿介面川务 送至顯示單元6G。該顯示單元6Q比對較結果進行進一步 處理，將該貼裝記憶體連接器2〇針腳之具體資訊顯示出 098128333 表單編號A0101 0982048660-0 201107770 來。 [0025] [0026] [0027] [0028] [0029] 综上所述，本發明確已符合發明專利要求，爰依法提出 專利申請。惟，以上所述者僅為本發明之較佳實施方式 ，舉凡熟悉本發明技藝之人士，爰依本發明之精神所作 之等效修飾或變化，皆應涵蓋於以下之申請專利範圍内 〇 【圖式簡單說明】 圖1係本發明較佳實施方式貼裝記憶體連接器測試裝置之 組成框圖，該陣列型連接器測試裝置包括一待測主機板 ❹ 、一資料獲取電路、一主控電路、及一顯示單元。 圖2及圖3係圖1中主控電路之元件電路圖。 圖4及圖5係圖1中資料獲取電路之元件電路圖。 【主要元件符號說明】 待測主板 10 貝占裝記憶體連 接器 20 資料獲取電路 30 主控電路 50 顯示單元 60 098128333 表單編號A0101 第12頁/共20頁 0982048660-0[_This second memory list is full - electrically erasable programmable read-only memory. The electrically erasable programmable read only memory surface includes a serial clock pin, a serial data pin SDA and an anti-write pin wp. The serial clock _cl and the serial data pin SM are connected to the voltage signal collecting unit %, and the write-protecting pin WP is grounded via a jump cap J9. When the jump cap j9 is shorted, the operation of the electric erasable programmable read-only memory U8 can be entered, and when the jump (four) is disconnected, the eraser can be locked for the read only memory. In addition to the operation of the information. _ (d), according to the Figure 5 5 to connect the mounting memory connector test device, the complex programmable logic device still obtains the data acquisition guide (4), respectively, to collect the mounted memory connector 20 on the motherboard 1 to be tested The pin information is sent to the voltage signal acquisition unit U6 via the data transmission pin S1 of the «(4)(4) unit. At the same time, the voltage signal acquisition pin F1~Fn of the voltage signal acquisition unit (10) collects the mounting memory on the motherboard 1 to be tested 098128333 Form No. A0101 Page 1 / Total 2 page 201107770 Voltage signal of the body connector 20 News. The voltage signal acquisition unit 电压 voltage signal information and the complex programmable logic device 卯 the collected pin information are sent to the second storage unit _. The micro control _ reading the pin information and the money and electricity information from the second deposit list and comparing it with the normal pin chat information, and then sending the comparison result to the display single heart to (4) 域 domain (4) On the top of the tape (four) connector is a normal chat. [_The plurality of data acquisition circuits 3's electric (four) number acquisition unit (10) clock pin SCL and data transfer pin SI) A are connected to the clock of the microcontroller U3 by the data transmission connector _ Pin C1 and data transfer pin are used. Between the microcontroller U3 and the data acquisition circuit, the f material acquisition circuit 3 is communicated with the placement memory connector 2 by means of bidirectional data transmission. During the test, the microcontroller U3 receives the data from the data acquisition circuit 30 by the plurality of data acquisition circuits 3D respectively controlling the pins of the corresponding placement memory connection (4). The material acquisition circuit transmits the opposite data twice to the corresponding pin 该 of the mounted memory connector 20. If the data received by the pin of the mounted memory quick connector 20 is received twice, the data acquisition circuit is used. 3〇 The f material is sent, so that the pin jLf of the memory connector 20 is mounted; (4), the pin of the mounting (4) is connected (4) is abnormal. The data acquisition circuit 30 collects the pin of the attached memory connector 2 The information is sent to the microcontroller U3. The microcontroller compares the data with the normal pin information, and converts the comparison result into the serial data by the USB analysis circuit U1, and sends the data through the leg interface. To the display unit 6G, the display unit 6Q performs further processing on the comparison result, and the specific information of the mounted memory connector 2 pin is displayed as 098128333 Form No. A0101 0982048660-0 201107770. [0025] [0026] [0029] In summary, the present invention has indeed met the requirements of the invention patent, and the patent application is filed according to law. However, the above is only a preferred embodiment of the present invention, and is familiar with the present invention. The equivalent modifications or variations of the skilled person in the spirit of the present invention are intended to be included in the following claims. FIG. 1 is a preferred embodiment of the present invention. The block diagram of the test device includes a host board to be tested, a data acquisition circuit, a main control circuit, and a display unit. Fig. 2 and Fig. 3 are the main control circuit of Fig. 1. Figure 4 and Figure 5 are the circuit diagrams of the components of the data acquisition circuit in Figure 1. [Main component symbol description] Motherboard to be tested 10 Bay memory module 20 Data acquisition circuit 30 Main control circuit 50 Display unit 60 098128333 Form No. A0101 Page 12 / Total 20 pages 0982048660-0