CN102567156A - Test set for server hard disk backplane - Google Patents

Test set for server hard disk backplane Download PDF

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Publication number
CN102567156A
CN102567156A CN2010106173006A CN201010617300A CN102567156A CN 102567156 A CN102567156 A CN 102567156A CN 2010106173006 A CN2010106173006 A CN 2010106173006A CN 201010617300 A CN201010617300 A CN 201010617300A CN 102567156 A CN102567156 A CN 102567156A
Authority
CN
China
Prior art keywords
server hard
hard disc
pin
sgpio
cpld chip
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN2010106173006A
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Chinese (zh)
Inventor
朱鸿儒
张万宏
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hongfujin Precision Industry Shenzhen Co Ltd
Hon Hai Precision Industry Co Ltd
Original Assignee
Hongfujin Precision Industry Shenzhen Co Ltd
Hon Hai Precision Industry Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hongfujin Precision Industry Shenzhen Co Ltd, Hon Hai Precision Industry Co Ltd filed Critical Hongfujin Precision Industry Shenzhen Co Ltd
Priority to CN2010106173006A priority Critical patent/CN102567156A/en
Publication of CN102567156A publication Critical patent/CN102567156A/en
Pending legal-status Critical Current

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Abstract

A test set for a server hard disk backplane comprises a complex programmable logic devices (CPLD) chip, and a hard disk fault location index system (SGPIO) bus interface, an inter-integrated circuit (I2C) bus interface and a serial interface which are connected onto the CPLD chip, wherein the serial interface is used for being connected with a personal computer, the SGPIO bus interface and the I2C bus interface are used for being respectively connected with corresponding interfaces on a server hard disk backplane to be tested, the personal computer can send the test program to the CPLD chip through the serial interface, the CPLD chip is used for correspondingly converting the received test program into an SGPIO bus data format and an I2C bus data format, and sending the two formats to the server hard disk backplane, so the SGPIO bus and the I2C bus of the server hard disk backplane to be tested are tested. The personal computer can be applied to testing the server hard disk back plane through the test set.

Description

Server hard disc back plate testing device
Technical field
The present invention relates to a kind of server hard disc back plate testing device.
Background technology
At present, common server inside all can be provided with a hard disk backboard, to make things convenient for the grafting external hard drive; In manufacturing or R&D process; Often need test this hard disk backboard, common method of testing need be installed in hard disk backboard to be measured on the server, tests through the testing software on the server again; But application server is tested hard disk backboard has increased testing cost beyond doubt greatly.
Summary of the invention
In view of foregoing, the present invention provides a kind of PC that uses to replace server to come the proving installation that the server hard disc backboard is tested.
A kind of server hard disc back plate testing device; Be used for a server hard disc backboard to be measured is tested; This server hard disc back plate testing device comprises a CPLD chip and is connected to a SGPIO EBI, an I2C EBI and the serial line interface on this CPLD chip; This serial line interface is used for linking to each other with a PC; This SGPIO EBI and I2C EBI are used for being connected to respectively the corresponding interface on this server hard disc backboard to be measured; This PC can send test procedure through this serial line interface and give this CPLD chip; This CPLD chip is used for the test procedure corresponding conversion that receives is become SGPIO bus data form and sends to this server hard disc backboard to be measured through this SGPIO EBI; So that this server hard disc backboard to be measured is carried out the test of SGPIO bus aspect, this CPLD chip also is used for the test procedure corresponding conversion that receives is become I2C bus data form and sends to this server hard disc backboard to be measured through this I2C EBI, so that this server hard disc backboard to be measured is carried out the test of I2C bus aspect.
Compared to prior art; Can make between PC and the server hard disc backboard to be measured through this server hard disc back plate testing device and to communicate; And convert the test procedure that PC sends to the required SGPIO bus data form of server hard disc back plate testing to be measured and I2C bus data form through this CPLD chip; Thereby need not this server hard disc backboard to be measured is installed on the server, provide cost savings greatly.
Description of drawings
Combine preferred embodiments that the present invention is described in further detail with reference to the accompanying drawings:
Fig. 1-Fig. 6 is the circuit diagram of server hard disc back plate testing device preferred embodiments of the present invention.
The main element symbol description
CPLD chip U1
Crystal oscillator chip U2
SGPIO EBI U3
I2C bus interface U4
Relay control interface U5
Electric pressure converter U6
Serial line interface U7
Serial line interface chip for driving U8
The CPLD programming meets U9
Power connector U10
Relay J
NMOS FET Q
Diode D
Resistance R 1-R9
Capacitor C 1-C13
Embodiment
Please refer to Fig. 1 to Fig. 6; Server hard disc back plate testing device of the present invention is used for a server hard disc backboard is tested; The preferred embodiments of this server hard disc back plate testing device comprises a CPLD (Complex Programable Logic Device; CPLD) chip U1, a crystal oscillator chip U2, a SGPIO (Serial General Purpose Input/Output; The general I/O of serial) EBI U3, an I2C (Inter-Integrated Circuit, built-in integrated circuit) EBI U4, a relay J, a NMOS FET Q, a diode D, a relay control interface U5, an electric pressure converter U6, a serial line interface U7, a serial line interface chip for driving U8 and a CPLD DLL U9, a power connector U10, nine resistance R 1-R9 and 13 capacitor C 1-C13.
In this embodiment; The model of this CPLD chip U1 is EPM570T100C5N; The model of this SGPIO EBI U3 and I2C EBI U4 is Molex-70555-0074, and the model of this relay control interface U5 is Molex-70555-0038, and the model of this electric pressure converter U6 is LD1117AS33TR; The model of this serial line interface U7 is COM-MALE-9P; The model of this serial line interface chip for driving U8 is MAX3232CUE+T, and the model of this CPLD DLL U9 is HC1105V, and the model of this power connector U10 is JPD103N-008-7F.In other embodiments, above-mentioned each element also can be selected other models that is fit to as required, is not limited to the model that this embodiment provides.
This power connector U10 is used to connect external power source (not shown) corresponding connector, to receive an external power source signal, like 5V power supply signal VDD P5V.The power pins 1 of this power connector U10 is connected to the input pin IN of this electric pressure converter U6, in addition two pins 2 and 3 ground connection.The output pin OUT of this electric pressure converter U6 exports a signal conversion voltage; Like 3.3V power supply signal VDD P3V3; So that other element work to be provided; The grounding pin ground connection of this electric pressure converter U6, the input pin IN of this electric pressure converter U6 is also through capacitor C 7 ground connection, and the output pin OUT of this electric pressure converter U6 is also through capacitor C 8 ground connection.In other embodiments,, then can this electric pressure converter U6 be deleted if the voltage signal that power connector U10 receives just is 3.3V.
Power pins VCCINT_13, VCCINT_39, VCCINT_63, VCCINT_88, VCCIO1_9, VCCIO1_31, VCCIO1_45, VCCIO2_59, VCCIO2_80, the VCCIO2_94 of this CPLD chip U1 all is connected to the output pin OUT of this electric pressure converter U6, and respectively through capacitor C 2-C6 ground connection.The equal ground connection of grounding pin GNDIO_10, GNDIO_32, GNDIO_46, GNDIO_60, GNDIO_79, GNDIO_93, GNDINT_11, GNDINT_37, GNDINT_65, GNDINT_90 of this CPLD chip U1.Test data input pin 9, test pattern that the test data input pin TDI of this CPLD chip U1, test pattern select pin TMS, test clock input pin TCK and test data output pin TDO to be connected to this CPLD DLL U9 are respectively selected pin 5, test clock input pin 1 and test data output pin 3; Grounding pin 2 and 10 ground connection of this CPLD DLL U9; Test clock input pin 1 is through resistance R 9 ground connection; The test data input pin 9 of this CPLD DLL U9 and test pattern select pin 5 to be connected to the output pin OUT of this electric pressure converter U6 respectively through resistance R 7 and R8; The power pins 4 of this CPLD DLL U9 is connected to the output pin OUT of this electric pressure converter U6, and 6-8 is vacant for other pins.
Data input and output pin IO2, IO6, IO7 and the IO8 of this CPLD chip U1 is connected to clock pin 1, load prongs 2, data output pin 3 and the data input pin 4 of this SGPIO EBI U3 respectively, grounding pin 5 ground connection of this SGPIO EBI U3.The data input and output pin IO17 of this CPLD chip U1 is connected to the grid of this FET Q through resistance R 5.Data input and output pin IO28, IO29, IO33 and the IO34 of this CPLD chip U1 is connected to first of this serial line interface chip for driving U8 respectively and receives output pin R1OUT, the first transmission input pin T1IN, the second transmission input pin T2IN and the second reception output pin R2OUT.The data input and output pin IO38 of this CPLD chip U1 and IO42 are connected to data pin 4 and the clock pin 5 of this I2C EBI U4 respectively; The power pins 1 of this I2C EBI U4 is connected to the output pin OUT of this electric pressure converter U6; Grounding pin 2 ground connection; Pin 3 is vacant, and this CPLD chip U1 data input and output pin IO38 and IO42 also are connected to the output pin OUT of this electric pressure converter U6 respectively through resistance R 1 and R2.
The clock pin GCLK0 of this CPLD chip U1 is connected to the output pin OUT of this crystal oscillator chip U2 through resistance R 4; The power pins VDD of this crystal oscillator chip U2 is connected to the output pin OUT of this electric pressure converter U6; Also through capacitor C 1 ground connection; The enable OE of this crystal oscillator chip U2 is connected to the output pin OUT of this electric pressure converter U6, the grounding pin GND ground connection of this crystal oscillator chip U2 through resistance R 3.Other pins of this CPLD chip U1 are owing to be vacant state, so not shown among Fig. 1, the connected mode of other embodiments is not limited to the scheme that this embodiment provides, and specifically can adjust according to the model of selected element and the mode of programming.
This relay J comprises a line chart L and a K switch, and the pin 1 and 2 of this relay control interface U5 is connected to first end of this K switch, and the pin 1 and 2 of this relay control interface U5 is connected to second end of this K switch.First end of this coil L is connected to the output pin OUT of this electric pressure converter U6 and the negative electrode of this diode D; Second end of this coil L is connected to the drain electrode of anode and this FET Q of this diode D; The source ground of this FET Q, grid is through resistance R 6 ground connection.
Grounding pin 5 ground connection of this serial line interface U7; The second reception input pin R2IN, the first transmission output pin T1OUT, second that the transmission pin 8 of this serial line interface U7, reception pin 3, reception pin 7 and transmission pin 2 are connected to this serial line interface chip for driving U8 respectively transmit the output pin T2OUT and the first reception input pin R1IN, and other pins 1,4,6,9 are vacant.The power pins VCC of this serial line interface U7 is connected to the output pin OUT of this electric pressure converter U6 and passes through capacitor C 13 ground connection; The grounding pin GND ground connection of this serial line interface U7; Power pins C1+ connects power pins C1-through capacitor C 9; Power pins V+ is through capacitor C 12 ground connection, and power pins C2+ connects power pins C2-through capacitor C 9, and power pins V-is through capacitor C 11 ground connection.
When using this server hard disc back plate testing device one server hard disc backboard (not shown) to be measured being tested; The serial line interface of one PC (not shown) is corresponding continuous with the serial line interface U7 of this server hard disc back plate testing device; The SGPIO EBI of this server hard disc backboard to be measured is corresponding continuous with the SGPIO EBI U3 of this server hard disc back plate testing device; The I2C EBI of server hard disc backboard to be measured is corresponding continuous with the I2C EBI U4 of this server hard disc back plate testing device; The power interface of one external power source (not shown) is corresponding continuous with the power connector U10 of this server hard disc back plate testing device; The pin 1 and 2 of the relay control interface U5 of this server hard disc back plate testing device is connected to the power pins of this external power source, and the pin 3 of this relay control interface U5 and 4 connects the power pins of this server hard disc backboard to be measured.The CPLD chip U1 of this server hard disc back plate testing device connects a programmable device (not shown) so that this CPLD chip U1 is programmed through this CPLD DLL U9; Because the CPLD chip is programmed for prior art, locate not specifically at the explanation programming process.
When beginning to test; This external power source becomes 3.3V voltage to offer each element the 5V voltage transitions through this electric pressure converter U6; The data input and output pin IO17 of this CPLD chip U1 exports a high level signal; Thereby make this FET Q conducting, so the coil L of this relay J powers on and CS K conducting, so make this external power source provide voltage to this server hard disc backboard to be measured so that its work.This PC sends test procedure through this serial line interface U7 and gives this CPLD chip U1 then; This CPLD chip U1 becomes the test procedure corresponding conversion that receives SGPIO bus data form and sends to this server hard disc backboard to be measured through this SGPIO EBI U3; So that this server hard disc backboard to be measured is carried out the test of SGPIO bus aspect; This CPLD chip U1 also becomes the test procedure corresponding conversion that receives I2C bus data form and sends to this server hard disc backboard to be measured through this I2C EBI U4 in addition; So that this server hard disc backboard to be measured is carried out the test of I2C bus aspect; Because this test process need not this server hard disc backboard to be measured is installed on the server; Communicate and get final product and only need to survey server hard disc backboard and this PC, so provide cost savings greatly by this server hard disc back plate testing device.

Claims (4)

1. server hard disc back plate testing device; Be used for a server hard disc backboard to be measured is tested; This server hard disc back plate testing device comprises a CPLD chip and is connected to a SGPIO EBI, an I2C EBI and the serial line interface on this CPLD chip; This serial line interface is used for linking to each other with a PC; This SGPIO EBI and I2C EBI are used for being connected to respectively the corresponding interface on this server hard disc backboard to be measured; This PC can send test procedure through this serial line interface and give this CPLD chip; This CPLD chip is used for the test procedure corresponding conversion that receives is become SGPIO bus data form and sends to this server hard disc backboard to be measured through this SGPIO EBI; So that this server hard disc backboard to be measured is carried out the test of SGPIO bus aspect, this CPLD chip also is used for the test procedure corresponding conversion that receives is become I2C bus data form and sends to this server hard disc backboard to be measured through this I2C EBI, so that this server hard disc backboard to be measured is carried out the test of I2C bus aspect.
2. server hard disc back plate testing device as claimed in claim 1 is characterized in that: this CPLD chip also connects one and is used for CPLD DLL that this CPLD chip is programmed.
3. server hard disc back plate testing device as claimed in claim 1 is characterized in that: also be connected between this CPLD chip and this serial line interface one be used to drive this serial line interface the serial line interface chip for driving.
4. server hard disc back plate testing device as claimed in claim 1; It is characterized in that: this server hard disc back plate testing device also comprises a relay, a NMOS FET, a diode, a relay control interface, first and second resistance; This relay comprises a line chart and a switch; First and second pin of this relay control interface is connected to first end of this switch; The the 3rd and the 4th pin of this relay control interface is connected to second end of this switch, and first end of this coil is connected to the negative electrode of a voltage pin and this diode, and second end of this coil is connected to the drain electrode of anode and this FET of this diode; The source ground of this FET; Grid is connected to this CPLD chip also through second resistance eutral grounding through first resistance, and first and second pin of this relay control interface is used to connect the power pins of an external power source, and the 3rd and the 4th pin of this relay control interface is used to connect the power pins of this server hard disc backboard to be measured.
CN2010106173006A 2010-12-31 2010-12-31 Test set for server hard disk backplane Pending CN102567156A (en)

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Application Number Priority Date Filing Date Title
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Cited By (5)

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Publication number Priority date Publication date Assignee Title
CN103984620A (en) * 2014-05-30 2014-08-13 浪潮电子信息产业股份有限公司 Backboard hardware power-on indication lamp lighting circuit dynamic implementation method
CN104391766A (en) * 2014-11-24 2015-03-04 英业达科技有限公司 Simulation device and hard disk drive backboard test system
CN107066746A (en) * 2017-04-21 2017-08-18 深圳市同泰怡信息技术有限公司 The method for realizing PCA9555 functions by CPLD based on I2C interfaces
CN108021481A (en) * 2017-12-21 2018-05-11 曙光信息产业(北京)有限公司 The detection device and its automatic testing method of a kind of hard disk backboard
CN105204967B (en) * 2015-09-21 2019-05-14 浪潮电子信息产业股份有限公司 A kind of method and device detecting hard disk

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103984620A (en) * 2014-05-30 2014-08-13 浪潮电子信息产业股份有限公司 Backboard hardware power-on indication lamp lighting circuit dynamic implementation method
CN103984620B (en) * 2014-05-30 2017-07-14 浪潮电子信息产业股份有限公司 The circuit dynamic realizing method of electric indicator lamp bright light on a kind of backboard hard disk
CN104391766A (en) * 2014-11-24 2015-03-04 英业达科技有限公司 Simulation device and hard disk drive backboard test system
CN105204967B (en) * 2015-09-21 2019-05-14 浪潮电子信息产业股份有限公司 A kind of method and device detecting hard disk
CN107066746A (en) * 2017-04-21 2017-08-18 深圳市同泰怡信息技术有限公司 The method for realizing PCA9555 functions by CPLD based on I2C interfaces
CN107066746B (en) * 2017-04-21 2020-09-25 深圳市同泰怡信息技术有限公司 Method for realizing PCA9555 function through CPLD based on I2C interface
CN108021481A (en) * 2017-12-21 2018-05-11 曙光信息产业(北京)有限公司 The detection device and its automatic testing method of a kind of hard disk backboard

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