CN107066746A - The method for realizing PCA9555 functions by CPLD based on I2C interfaces - Google Patents
The method for realizing PCA9555 functions by CPLD based on I2C interfaces Download PDFInfo
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- CN107066746A CN107066746A CN201710267050.XA CN201710267050A CN107066746A CN 107066746 A CN107066746 A CN 107066746A CN 201710267050 A CN201710267050 A CN 201710267050A CN 107066746 A CN107066746 A CN 107066746A
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
- G06F13/4282—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F30/00—Computer-aided design [CAD]
- G06F30/30—Circuit design
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2117/00—Details relating to the type or aim of the circuit design
- G06F2117/08—HW-SW co-design, e.g. HW-SW partitioning
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2213/00—Indexing scheme relating to interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F2213/0016—Inter-integrated circuit (I2C)
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Abstract
The invention belongs to server design field, especially a kind of method for realizing PCA9555 functions by CPLD based on I2C interfaces；This programme provide realized based on I2C interfaces by CPLD the method for PCA9555 functions script is integrated into above CPLD using the PCA9555 functions of realizing go realize, the function of I2C interfaces is realized with CPLD GPIO interface, its interface function uses VHDL language, and the mechanism of utilization state machine is realized.CPLD expansible GPIO quantity is more more than PCA9555 simultaneously, and PCA9555 at most only has 16 GPIO, and CPLD can be arbitrarily extended as needed, and this scheme is saved greatly cost.Simultaneously because being realized using CPLD, brought great convenience to hardware debugging, only need to go modification and then burning CPLD firmwares just easily can debug and change required design on software, greatly improve flexibility and the scalability of hardware debugging.
Description
Technical field
PCA9555 work(is realized by CPLD based on I2C interfaces the invention belongs to server design field, especially one kind
The method of energy.
Background technology
The backboard of current server or memory is used to be communicatively connected to above backboard by the I2C of mainboard
PCA9555 chips are written and read operation to GPIO, and PCA9555 chips use I2C interface communications, can at most be used for extending 16
Individual GPIO, this 16 GPIO can be used for being written and read operation by I2C.Using PCA9555 chips can greatly reduce mainboard with
The signal pin quantity connected between backboard, if not using PCA9555, it is necessary to which all GPIO signals are all connected into master
Plate gets on（For example there are 16 GPIO signals, it is necessary to which 16 pin or cable are connected on mainboard）, and use PCA9555's
Two pin pin that scheme only needs to I2C interfaces can just be realized.
But server or the connected mode of the backboard of memory at this stage is as shown in figure 1, can typically use CPLD
To be decoded the indicator lamp for carrying out some each hard disks to SGPIO, therefore existing server or memory backboard typically can be same
When there is CPLD and PCA9555 chips.
The backboard of existing server or memory, which using I2C and PCA9555 communicate, carries out IO extension, but
One PCA9555 at most only 16 GPIO are used, and these GPIO quantity is very limited amount of, if to realize a lot
GPIO has to increase PCA9555 number of chips.This can greatly increase cost, while increasing the complexity of plank placement-and-routing
Degree.
And the backboard of existing server or memory inherently make use of CPLD to decode SGPIO characteristic, therefore
Since having many logic chips of this GPIOI interfaces of CPLD, but still also need to the design using PCA9555 chips,
There is the use value for weakening this CPLDs of CPLD significantly.If PCA9555 function can be added to be put into CPLD
Go to realize above, while mainboard accesses CPLD communication mode and access instruction and I2C addresses access with PCA9555 I2C and referred to
With order is address as, and so original I2C communication protocols of mainboard need not make any change it is achieved that while also just can be with
Greatly save cost, can CPLD be no I2C interfaces in itself, therefore need it is a kind of can be realized using CPLD I/O interface
I2C access and also mainboard I2C communications access the constant method of mode.
The content of the invention
The main object of the present invention is to provide a kind of method for realizing PCA9555 functions by CPLD based on I2C interfaces,
For overcoming existing backboard to need connection PCA9555 chips so that the problem of structure is excessively complicated.
The present invention is achieved in that a kind of method for realizing PCA9555 functions by CPLD based on I2C interfaces, bag
Include following steps：
Step A：CPLD is configured to I2C Slave equipment by initialization step, the initialization step system；
Step B：The I2C communication interfaces of mainboard are connected to CPLD GPIO interface by operating procedure, the operating procedure system.
General Purpose Input Output （Universal input/output）Referred to as GPIO, or bus extender,
People simplify I/O mouthfuls of extension using industrial standard I2C, SMBus or SPI interface.When microcontroller or chipset are without foot
Enough I/O ports, or when system need using distal end serial communication or control when, GPIO products can provide extra control and
Function for monitoring.
The present invention further technical scheme be：Realize that CPLD is configured to I2C by state machine mechanism in the step A
Slave。
I2C（Inter-Integrated Circuit）Bus is that the twin wire developed by PHILIPS companies is serially total
Line, for connecting microcontroller and its ancillary equipment.It is a kind of widely used bus standard in microelectronics Control on Communication field.It
A kind of special shape of synchronous communication, few with interface line, control mode is simple, and device packing forms are small, traffic rate compared with
High the advantages of.I2C buses support any IC production technologies (CMOS, ambipolar）.Pass through serial data（SDA）Line and it is serial when
Clock（SCL）Line transmission information between the device of bus is connected to.Each device has a unique Address Recognition（Either
Microcontroller --- MCU, LCD driver, memory or keyboard interface）, and can serve as a transmitter or receiver
（Determined by the function of device）.LCD drivers can only be as receiver, and memory then can both be received can send number
According to.In addition to transmitters and receivers, device can also be counted as main frame or slave when performing data transfer（It is shown in Table 1）.
Main frame is the data transfer of initialization bus and generation allow transmission clock signal device.Now, any device being addressed
Part is considered as slave.
CPLD (Complex Programmable Logic Device) CPLD, be from PAL and
The device that GAL device developments come out, comparatively scale is big, complicated, belongs to large scale integrated circuit scope.It is a kind of use
Family voluntarily digital integrated electronic circuit of constitutive logic function according to respective need.Its basic design method is soft by Integrated Development
Part platform, with methods such as schematic diagram, hardware description languages, generates corresponding file destination, passes through download cable（" in system " is compiled
Journey）Code is sent in objective chip, the digital display circuit of design is realized.
The present invention further technical scheme be：The state machine mechanism is realized by VHDL language.
The full name Very-High-Speed Integrated Circuit Hardware Description of VHDL
Language, is born in nineteen eighty-two.The end of the year 1987, VHDL confirms as standard hardware description language by IEEE and U.S. Department of Defense.
From IEEE-1076（Referred to as 87 editions）Afterwards, each EDA companies release one after another the VHDL design environments of oneself, or announce setting for oneself
Meter instrument can be with VHDL interfaces.1993, IEEE was revised to VHDL, from higher abstraction hierarchy and System describe energy
VHDL content is extended in power, the 1076-1993 versions of the VHDL of redaction, i.e. ieee standard, referred to as 93 editions is disclosed.VHDL
With industry standard hardware description languages of the Verilog as IEEE, obtain numerous EDA companies and support, in electronic engineering field,
Common hardware description language on coming true.
This programme further improvement is that：The step A include it is following step by step：
Step A1：I2C is resolved into some states；
Step A2：Mainboard BMC determines CPLD device addresses；
Step A3：Mainboard BMC determines the CPLD equipment operations；
Step A4：CPLD is parsed and is performed operation.
This programme further improvement is that：The step A2 include it is following step by step：
Step A21：Mainboard BMC sends address signal；
Step A22：CPLD reads the address signal, corresponding signal is sent if address signal address is identical with itself, if seeking
Location Signal Message Address is different from itself, does not process.
This programme further improvement is that：The CPLD is by last interpretation of address signal progress read operation or writes
Operation.
This programme further improvement is that：Mainboard BMC described in the step A3 sends the analysable tools of CPLD
Body operation signal.
This programme further improvement is that：The step A also includes step A5：End signal is sent to stop operation；Institute
Step A5 is stated to perform after step A4.
This programme further improvement is that：The data manipulation be CPLD read operations, then step A5 be the CPLD to
The BMC sends end signal；If the data manipulation is CPLD write operations, step A5 is that the BMC is sent out to the CPLD
Send end signal.
This programme further improvement is that：I2C is resolved into Idle states, Read Address shapes in the step A1
State, Send_ACK2 states, Write_CMD_IO0 states, Write_CMD_IO1 states, Read_CMD_IO0 states, Read_
CMD_IO1 states, Read_CMD_IO9 states, Send_ACK_1 states, BMC_COMMAND states, Wait_ACK_1 states,
Wait_ACK_2 states.
The beneficial effects of the invention are as follows：What this programme was provided realizes PCA9555 functions by CPLD based on I2C interfaces
Script is integrated into above CPLD by method using the PCA9555 functions of realizing to be gone to realize, realizes that I2C connects with CPLD GPIO interface
Mouthful function, its interface function uses VHDL language, and the mechanism of utilization state machine is realized.While CPLD expansible GPIO numbers
Amount is more more than PCA9555, and PCA9555 at most only has 16 GPIO, and CPLD can be arbitrarily extended as needed, this
The scheme of kind is saved greatly cost.Simultaneously because being realized using CPLD, bring great convenience, only need to hardware debugging
To go modification and then burning CPLD firmwares just easily can debug and change required design, pole on software
The big flexibility for improving hardware debugging and scalability.Other CPLD I2C interfaces still use PCA9555 instruction side
Case, i.e., directly change the backboard using new CPLD schemes in the case where mainboard need not make any change, and mainboard is not required to
Carrying out any software debugging can normally use.Therefore the present invention has cost low, the high advantage of debugging flexibility.
Brief description of the drawings
, below will be to embodiment or existing in order to illustrate more clearly of the embodiment of the present application or technical scheme of the prior art
There is the accompanying drawing used required in technology description to be briefly described, it should be apparent that, drawings in the following description are only this
Some embodiments described in application, for those of ordinary skill in the art, on the premise of not paying creative work,
Other accompanying drawings can also be obtained according to these accompanying drawings.
Fig. 1 is mainboard and the schematic diagram of backboard connected mode in the prior art.
Fig. 2 is mainboard and the schematic diagram of backboard annexation in the embodiment of the present invention.
Fig. 3 is the shape of the method provided in an embodiment of the present invention for realizing PCA9555 functions by CPLD based on I2C interfaces
State machine schematic diagram.
Fig. 4 is the hard of the method provided in an embodiment of the present invention for realizing PCA9555 functions by CPLD based on I2C interfaces
Disk writes analog result figure.
Fig. 5 is the hard of the method provided in an embodiment of the present invention for realizing PCA9555 functions by CPLD based on I2C interfaces
Disk reads analog result figure.
Embodiment
The present invention provides a kind of method for realizing PCA9555 functions by CPLD based on I2C interfaces.Below in conjunction with accompanying drawing
And the present invention is described in detail for embodiment.
A kind of method for being realized PCA9555 functions by CPLD based on I2C interfaces, is comprised the following steps：
Step A：CPLD is configured to I2C Slave equipment by initialization step, the initialization step system；
Step B：The I2C communication interfaces of mainboard are connected to CPLD GPIO interface by operating procedure, the operating procedure system.
Further：Realize that CPLD is configured to I2C Slave by state machine mechanism in the step A.
Further：The state machine mechanism is realized by VHDL language.
The GPIO interface of the invention that I2C is directly connected to CPLD, is directly to eliminate PCA9555 from hardware point of view
Chip, while CPLD IO quantity is very big, multiple GPIO pin can realize that this is just in cost using a CPLD
On greatly improved.Figure two is the annexation schematic diagram for the scheme that the present invention is realized.
Further, the step A include it is following step by step：
Step A1：I2C is resolved into some states；
Step A2：Mainboard BMC determines CPLD device addresses；
Step A3：Mainboard BMC determines the CPLD equipment operations；
Step A4：CPLD is parsed and is performed operation.
Further, the step A2 include it is following step by step：
Step A21：Mainboard BMC sends address signal；
Step A22：CPLD reads the address signal, corresponding signal is sent if address signal address is identical with itself, if seeking
Location Signal Message Address is different from itself, does not process.
Further, by address signal, last interpretation carries out read operation or write operation to the CPLD.
Further, mainboard BMC described in the step A3 sends the analysable concrete operations signals of CPLD.
Further, the step A also includes step A5：End signal is sent to stop operation；The step A5 is in step
Performed after A4.
Further, the data manipulation is CPLD read operations, then step A5 is that the CPLD terminates to BMC transmissions
Signal；If the data manipulation is CPLD write operations, step A5 is that the BMC sends end signal to the CPLD.
Further, I2C is resolved into Idle states, Read Address states, Send_ACK2 shapes in the step A1
State, Write_CMD_IO0 states, Write_CMD_IO1 states, Read_CMD_IO0 states, Read_CMD_IO1 states,
Read_CMD_IO9 states, Send_ACK_1 states, BMC_COMMAND states, Wait_ACK_1 states, Wait_ACK_2 shapes
State.
Realize that this scheme of the invention needs the technical barrier solved to be if realized by CPLD common GPIO interface
Communicated with the I2C of mainboard.CPLD is not define I2C communication interfaces, to realize the I2C interface communications with mainboard, it is necessary to will
CPLD is as I2C Slave equipment, and we use VHDL language, and the mechanism of utilization state machine solves this technical barrier,
I2C by being resolved into Idle states, Read Address states, Send_ACK2 states, Write_CMD_IO0 shapes by state machine
State, Write_CMD_IO1 states, Read_CMD_IO0 states, Read_CMD_IO1 states, Read_CMD_IO9 states, Send_
ACK_1 states, BMC_COMMAND states, Wait_ACK_1 states, Wait_ACK_2 states, utilize the effective handle of these states
I2C communication protocol resolves into similar little module one by one, can be jumped to after these little module inter-process are complete next
Module is handled, if processing, which is completed, will jump to Idel states.Redirecting between these modules mainly follow with
Lower principle, first Master equipment send the address of CPLD equipment, the address set when the CPLD address values read with itself
Ack signal, which will be sent, when the same gives Master equipment, if the different CPLD in address is without subsequent treatment, then base area
Last position of location value is high level or low level to judge this order be read operation or write operation, reads for high level, to write
For low level, the next step of this operation is that Master sends Command data, and Command data are used for judging it is to IO0/
IO1/IO9 read operation, or IO0/IO1 write operation, CPLD can parse the corresponding operation of execution to this data, work as number
Send_ACK signals are sent according to the signals or CPLD that Maseter equipment can be waited to send Wait_ACk of CPLD after the completion of operation to come
Indicate the reception of data or send whether completed.
In this example, Master is mainboard BMC, and IO0, IO1, IO9, IO0, IO1 and other operational orders are referred to
Various operations, can be self-defined as needed, so as to realize PA9555 function.
Figure three is the state machine diagram run out after being realized using VHDL language.
The realization of CPLD I2C interface functions is realized by state machine, while the simulation software pair carried using CPLD
The logical language write is emulated, and obtained simulation result is as shown in Figure 4,5.Wherein, figure four is the emulation that I2C writes action
As a result, figure five is the simulation result of I2C readings action.
The result produced using this state machine carries out signal authentication on actual backboard, the waveform obtained with oscillograph
Waveform with being produced with PCA9555 is consistent.
The present invention realizes that the scheme of PCA9555 functions saves cost well by CPLD based on I2C interfaces, and
By verifying its function and performance and its reliable.I2C communication reading manner is with PCA9555 modes simultaneously, so in clothes
Device mainboard be engaged in not can directly not realized easily with this scheme in the case of changing.In addition using CPLD scheme in follow-up maintenance
Easily, can easily it be realized if additional function to be increased only needs to change CPLD FW.Specific cost is low, practicality
By force, safeguard convenient, debug flexible superiority.
The foregoing is merely illustrative of the preferred embodiments of the present invention, is not intended to limit the invention, all essences in the present invention
Any modifications, equivalent substitutions and improvements made within refreshing and principle etc., should be included in the scope of the protection.
Claims (10)
1. a kind of method for realizing PCA9555 functions by CPLD based on I2C interfaces, it is characterised in that comprise the following steps：
Step A：CPLD is configured to I2C Slave equipment by initialization step, the initialization step system；
Step B：The I2C communication interfaces of mainboard are connected to CPLD GPIO interface by operating procedure, the operating procedure system.
2. the method according to claim 1 for being realized PCA9555 functions by CPLD based on I2C interfaces, its feature is existed
In：Realize that CPLD is configured to I2C Slave by state machine mechanism in the step A.
3. the method according to claim 2 for being realized PCA9555 functions by CPLD based on I2C interfaces, its feature is existed
In：The state machine mechanism is realized by VHDL language.
4. the method according to claim 3 for being realized PCA9555 functions by CPLD based on I2C interfaces, its feature is existed
In, the step A include it is following step by step：
Step A1：I2C is resolved into some states；
Step A2：Mainboard BMC determines CPLD device addresses；
Step A3：Mainboard BMC determines the CPLD equipment operations；
Step A4：CPLD is parsed and is performed operation.
5. the method according to claim 4 for being realized PCA9555 functions by CPLD based on I2C interfaces, its feature is existed
In, the step A2 include it is following step by step：
Step A21：Mainboard BMC sends address signal；
Step A22：CPLD reads the address signal, corresponding signal is sent if address signal address is identical with itself, if seeking
Location Signal Message Address is different from itself, does not process.
6. the method according to claim 5 for being realized PCA9555 functions by CPLD based on I2C interfaces, its feature is existed
In by address signal, last interpretation carries out read operation or write operation to the CPLD.
7. the method according to claim 6 for being realized PCA9555 functions by CPLD based on I2C interfaces, its feature is existed
In mainboard BMC described in the step A3 sends the analysable concrete operations signals of CPLD.
8. the method according to claim 7 for being realized PCA9555 functions by CPLD based on I2C interfaces, its feature is existed
In the step A also includes step A5：End signal is sent to stop operation；The step A5 is performed after step A4.
9. the method according to claim 8 for being realized PCA9555 functions by CPLD based on I2C interfaces, its feature is existed
In：The data manipulation is CPLD read operations, then step A5 is that the CPLD sends end signal to the BMC；If the number
It is CPLD write operations according to operation, then step A5 is that the BMC sends end signal to the CPLD.
10. according to any described method for realizing PCA9555 functions by CPLD based on I2C interfaces in claim 4-9,
It is characterized in that：In the step A1 by I2C resolve into Idle states, Read Address states, Send_ACK2 states,
Write_CMD_IO0 states, Write_CMD_IO1 states, Read_CMD_IO0 states, Read_CMD_IO1 states, Read_
CMD_IO9 states, Send_ACK_1 states, BMC_COMMAND states, Wait_ACK_1 states, Wait_ACK_2 states.
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Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107577624A (en) * | 2017-09-15 | 2018-01-12 | 联想(北京)有限公司 | A kind of data processing method and electronic equipment |
| CN107783862A (en) * | 2017-09-27 | 2018-03-09 | 郑州云海信息技术有限公司 | A kind of 8 road server principal and subordinate BMC based on PCA9555 reset control method |
| CN108170245A (en) * | 2018-01-25 | 2018-06-15 | 郑州云海信息技术有限公司 | Control system, method and the server management system of server physical button operation |
| CN109117347A (en) * | 2018-07-10 | 2019-01-01 | 深圳市同泰怡信息技术有限公司 | The method of BMC control hard disk indication lamp state |
| CN109947453A (en) * | 2019-03-29 | 2019-06-28 | 浪潮商用机器有限公司 | A kind of CPLD upgrade method, device, system, controller and storage medium |
| TWI687816B (en) * | 2018-12-18 | 2020-03-11 | 英業達股份有限公司 | Hard disk back board and control board |
| CN114691573A (en) * | 2020-12-31 | 2022-07-01 | 北京配天技术有限公司 | Hardware identification circuit, method and related equipment |
| CN117057286A (en) * | 2023-10-11 | 2023-11-14 | 成都电科星拓科技有限公司 | SMBus module level verification system based on UVM and VIP |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102567156A (en) * | 2010-12-31 | 2012-07-11 | 鸿富锦精密工业（深圳）有限公司 | Test set for server hard disk backplane |
| TW201539319A (en) * | 2014-02-14 | 2015-10-16 | Hon Hai Prec Ind Co Ltd | Data transporting method of electronic device system and electronic device system |
| CN105302484A (en) * | 2015-10-19 | 2016-02-03 | 上海斐讯数据通信技术有限公司 | Apparatus and method for batch reading of digital diagnosis information in optical modules of Ethernet card |
| US20160118121A1 (en) * | 2014-10-24 | 2016-04-28 | Microsoft Technology Licensing, Llc | Configurable Volatile Memory Data Save Triggers |
| CN105955898A (en) * | 2016-05-25 | 2016-09-21 | 浪潮电子信息产业股份有限公司 | Hard disk backboard compatible with SAS hard disk and NVMe hard disk |
-
2017
- 2017-04-21 CN CN201710267050.XA patent/CN107066746B/en active Active
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102567156A (en) * | 2010-12-31 | 2012-07-11 | 鸿富锦精密工业（深圳）有限公司 | Test set for server hard disk backplane |
| TW201539319A (en) * | 2014-02-14 | 2015-10-16 | Hon Hai Prec Ind Co Ltd | Data transporting method of electronic device system and electronic device system |
| US20160118121A1 (en) * | 2014-10-24 | 2016-04-28 | Microsoft Technology Licensing, Llc | Configurable Volatile Memory Data Save Triggers |
| CN105302484A (en) * | 2015-10-19 | 2016-02-03 | 上海斐讯数据通信技术有限公司 | Apparatus and method for batch reading of digital diagnosis information in optical modules of Ethernet card |
| CN105955898A (en) * | 2016-05-25 | 2016-09-21 | 浪潮电子信息产业股份有限公司 | Hard disk backboard compatible with SAS hard disk and NVMe hard disk |
Non-Patent Citations (1)
| Title |
|---|
| XUEMEI GUO等: "Application of FPGA in high-speed CMOS digital image acquisition and color recognition system", 《JOURNAL OF CHEMICAL AND PHARMACEUTICAL RESEARCH》 * |
Cited By (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107577624A (en) * | 2017-09-15 | 2018-01-12 | 联想(北京)有限公司 | A kind of data processing method and electronic equipment |
| CN107783862A (en) * | 2017-09-27 | 2018-03-09 | 郑州云海信息技术有限公司 | A kind of 8 road server principal and subordinate BMC based on PCA9555 reset control method |
| CN107783862B (en) * | 2017-09-27 | 2021-07-20 | 郑州云海信息技术有限公司 | PCA 9555-based master-slave BMC reset control method for 8-path server |
| CN108170245A (en) * | 2018-01-25 | 2018-06-15 | 郑州云海信息技术有限公司 | Control system, method and the server management system of server physical button operation |
| CN109117347A (en) * | 2018-07-10 | 2019-01-01 | 深圳市同泰怡信息技术有限公司 | The method of BMC control hard disk indication lamp state |
| TWI687816B (en) * | 2018-12-18 | 2020-03-11 | 英業達股份有限公司 | Hard disk back board and control board |
| CN109947453A (en) * | 2019-03-29 | 2019-06-28 | 浪潮商用机器有限公司 | A kind of CPLD upgrade method, device, system, controller and storage medium |
| CN114691573A (en) * | 2020-12-31 | 2022-07-01 | 北京配天技术有限公司 | Hardware identification circuit, method and related equipment |
| CN117057286A (en) * | 2023-10-11 | 2023-11-14 | 成都电科星拓科技有限公司 | SMBus module level verification system based on UVM and VIP |
| CN117057286B (en) * | 2023-10-11 | 2024-01-30 | 成都电科星拓科技有限公司 | SMBus module level verification system based on UVM and VIP |
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