CN218886572U - Simple peripheral bus system - Google Patents

Abstract

The utility model discloses a simple peripheral hardware bus system. The system comprises a central processing unit, a PCH chip and a complex programmable logic chip; the complex programmable logic chip comprises a simple peripheral bus controller; the output end of the central processing unit is connected with the input end of the PCH chip; and the output end of the PCH chip is connected with the input end of the complex programmable logic chip so as to drive the simple peripheral bus controller to answer the access of the central processing unit. According to the technical scheme, the expansion mode of the simple peripheral bus controller is more universal, the transportability of the simple peripheral bus controller is improved on the premise of not increasing the hardware cost, and the workload of adapting the simple peripheral bus controller with other devices is reduced.

Description

Simple peripheral bus system

Technical Field

The utility model relates to a simple peripheral hardware bus extension technical field especially relates to a simple peripheral hardware bus system.

Background

The Simple Peripheral Bus (SPB) is a generic term of a Simple Bus, and may include a Universal Asynchronous Receiver/Transmitter (UART), an Integrated Circuit Bus (IIC), a Serial Peripheral Interface (SPI), and the like, and is used to implement a debug Serial port, a sensor extension, a board specific information storage device extension, and the like.

In the server field, the Intel scheme still occupies a high market share, the SPB bus is implemented in a PCH (Platform Controller Hub) chip, and is matched with the PCH chip, and an operating system running on a Central Processing Unit (CPU) needs to include a corresponding bus Controller driver and correctly load the driver, so that the peripheral device mounted on the operating system can be accessed, and a product reservation function is completed.

The SPB driver and the PCH chip have a binding relationship, and once a hardware platform of a CPU or a PCH needs to be upgraded or replaced for various reasons in hardware design and development, the SPB driver needs to be transplanted or the version of the entire operating system needs to be upgraded, which causes a large extra workload.

SUMMERY OF THE UTILITY MODEL

The utility model provides a simple peripheral hardware bus system, the extension mode of simple peripheral hardware bus controller is more general, has promoted the portability of simple peripheral hardware bus controller under the prerequisite that does not increase the hardware cost, has reduced the work load of simple peripheral hardware bus controller with other device adaptations.

According to an aspect of the present invention, there is provided a simple peripheral bus system, said system comprising a central processing unit, a PCH chip and a complex programmable logic chip; the complex programmable logic chip comprises a simple peripheral bus controller;

the output end of the central processing unit is connected with the input end of the PCH chip; and the output end of the PCH chip is connected with the input end of the complex programmable logic chip so as to drive the simple peripheral bus controller to respond the access of the central processing unit.

According to the technical scheme of the embodiment of the utility model, the system comprises a central processing unit, a PCH chip and a complex programmable logic chip; the complex programmable logic chip comprises a simple peripheral bus controller; the output end of the central processing unit is connected with the input end of the PCH chip; the output end of the PCH chip is connected with the input end of the complex programmable logic chip so as to drive the simple peripheral bus controller to answer the access of the central processing unit. According to the technical scheme, the expansion mode of the simple peripheral bus controller is more universal, the transportability of the simple peripheral bus controller is improved on the premise of not increasing the hardware cost, and the workload of adapting the simple peripheral bus controller with other devices is reduced.

It should be understood that the statements herein are not intended to identify key or critical features of any embodiment of the present invention, nor are they intended to limit the scope of the invention. Other features of the present invention will become apparent from the following description.

Drawings

In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings needed to be used in the description of the embodiments will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art to obtain other drawings without creative efforts.

FIG. 1 is a schematic diagram of a simple peripheral bus system according to an embodiment of the present invention;

FIG. 2 is a schematic diagram of another simple peripheral bus system provided in accordance with an embodiment of the present invention;

FIG. 3 is a diagram of a simple peripheral bus controller provided by an embodiment of the present application.

Detailed Description

In order to make the technical solutions of the present invention better understood, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only some embodiments of the present invention, not all embodiments. Based on the embodiments in the present invention, all other embodiments obtained by a person skilled in the art without creative efforts shall belong to the protection scope of the present invention.

It should be noted that the terms "first," "second," and the like in the description and claims of the present invention and in the drawings described above are used for distinguishing between similar elements and not necessarily for describing a particular sequential or chronological order. It is to be understood that the data so used is interchangeable under appropriate circumstances such that the embodiments of the invention described herein are capable of operation in sequences other than those illustrated or otherwise described herein. Moreover, the terms "comprises," "comprising," and "having," and any variations thereof, are intended to cover a non-exclusive inclusion, such that a process, method, system, article, or apparatus that comprises a list of steps or elements is not necessarily limited to those steps or elements expressly listed, but may include other steps or elements not expressly listed or inherent to such process, method, article, or apparatus.

Fig. 1 is a schematic diagram of a simple peripheral bus system according to an embodiment of the present invention, as shown in fig. 1, the simple peripheral bus system includes a central processing unit 110, a PCH chip 120 and a complex programmable logic chip 130. The PCH chip 120 includes a simple peripheral bus controller 140. Simple peripheral bus controller 140 includes a universal asynchronous receiver/transmitter 141 and an integrated circuit bus controller 142. The central processing unit 110 accesses the PCH chip 120 through a DMI (Direct Media Interface) bus, and accesses the simple peripheral bus controller 140 through a PCIe (peripheral component interconnect express) bus inside the PCH chip 120.

In this embodiment, the simple peripheral bus controller 140 and the PCH chip 120 have a binding relationship, and in a hardware development design, when a hardware platform of the central processing unit 110 or the PCH chip 120 needs to be upgraded or replaced for various reasons, it is likely that a related driver of the simple peripheral bus is not included in an old operating system, and it is impossible to control a device hung on the simple peripheral bus, and a driver of the simple peripheral bus needs to be transplanted or a version of the entire system needs to be upgraded, which results in a large extra workload. Therefore, it is necessary to extend the simple peripheral bus controller 140, to avoid the problems of stability and performance test caused by simple peripheral bus driver migration adaptation or kernel version upgrade due to the cpu 110 or the PCH chip 120, and to shorten the time for product to market.

Fig. 2 is a schematic diagram of another simple peripheral bus system provided according to an embodiment of the present invention, as shown in fig. 2, the system includes a central processing unit 110, a PCH chip 120 and a complex programmable logic chip 130; the complex programmable logic chip 130 includes a simple peripheral bus controller 140;

the output end of the central processing unit 110 is connected with the input end of the PCH chip 120; the output of the PCH chip 120 is connected to the input of the complex programmable logic chip 130 to drive the simple peripheral bus controller 140 to respond to the access of the central processor 110.

The cpu 110 is a core hardware unit that controls and allocates all hardware resources of the computer and executes general operations.

In the present embodiment, the PCH chip 120 is an integrated south bridge of intel corporation, and has all functions of an ICH (I/o controller hub) and a management engine function of an MCH (memory controller hub). The MCH is equivalent to a north bridge chip and is responsible for connecting a CPU, an AGP (Accelerated Graphics Port) bus, and a memory bus. The ICH is responsible for connecting PCI (Peripheral Component Interconnect) buses, IDE (Integrated Drive Electronics) devices, I/O devices, etc.

In this embodiment, the Complex Programmable Logic Device (CPLD) 130 is mainly composed of Programmable Logic Macro cells (MC, macro Cell) surrounding a central Programmable interconnect matrix Cell. The MC structure is complex and has a complex I/O unit interconnection structure, and a specific circuit structure can be generated as required to complete a certain function.

Wherein any control unit can be implemented in the complex programmable logic chip 130 by logic programming. Preferably, the simple peripheral bus controller 140 can be implemented in the complex programmable logic chip 130 by programming using HDL (Hardware Description Language).

In this technical solution, optionally, the system includes:

the central processing unit 110 generates a first signal according to the received instruction, and transmits the first signal to the input end of the PCH chip 120 through the output end;

the PCH chip 120 receives the first signal through an input terminal, generates a second signal according to the first signal, and transmits the second signal to an input terminal of the simple peripheral bus controller 140 through an output terminal;

the simple peripheral bus controller 140 responds to the second signal after receiving the second signal. The first signal and the second signal may be simple peripheral bus controller 140 control signals. For example, the first signal and the second signal may be a data reception signal, a data transmission signal, or the like.

In this embodiment, a simple peripheral bus controller 140 is built in the complex programmable logic chip 130, and the central processing unit 110 accesses the PCH chip 120 and then accesses the complex programmable logic chip 130, thereby controlling the simple peripheral bus controller 140. Specifically, the central processor 110 may generate a first signal according to the received instruction, and transmit the first signal to the input end of the PCH chip 120 through the output end; the PCH chip 120 receives a first signal through an input terminal, generates a second signal according to the first signal, and transmits the second signal to an input terminal of the simple peripheral bus controller 140 through an output terminal; the simple peripheral bus controller 140 responds to the second signal after receiving the second signal, thereby realizing the access of the central processing unit 110 to the simple peripheral bus controller 140.

In this embodiment, the central processor 110 and the PCH chip 120 may be connected via a bus; the PCH chip 120 and the simple peripheral bus controller 140 may also be connected by a bus. The bus is a public communication trunk line for transmitting information among various functional components of the computer, and is a transmission line bundle consisting of wires, and the bus of the computer can be divided into a data bus, an address bus and a control bus according to the type of information transmitted by the computer, and is used for transmitting data, data addresses and control signals respectively.

In this embodiment, the simple peripheral bus controller 140 optionally includes a universal asynchronous receiver/transmitter 141 and an integrated circuit bus controller 142.

The universal asynchronous receiver/transmitter 141 is an asynchronous receiver/transmitter, and operates by transmitting each binary bit of the transmission data bit by bit. In the communication protocol, a state on the signal line represents 1 when it is high, and represents 0 when it is low. For example, when the universal asynchronous receiver/transmitter 141 is used to transmit one byte of data, a combination of eight high and low levels is generated on the signal line.

In the present embodiment, the integrated circuit bus controller 142 is a Serial bus composed of a data line SDA (Serial data) and a clock line SCL (Serial clock line). The data line SDA is used for transmitting data of one bit; the clock line SCL plays a controlling role in the communication process. When SCL is high, the SDA line is not allowed to change while transmitting or receiving data; the SDA line may vary arbitrarily by 0, 1 when the SCL line is low. In other phases, the integrated circuit bus circuit only records the level (0 or 1) on the SDA line when the SCL is high, and does not sample the SDA when the SCL line is low, whether SDA is high or low.

In this embodiment, the universal asynchronous receiver-transmitter 141 and the integrated circuit bus controller 142 may be implemented in the complex programmable logic chip 130 by logic programming.

The simple peripheral bus controller 140 may further include a serial peripheral interface controller, that is, the serial peripheral interface controller may also be implemented in the complex programmable logic chip 130 through logic programming.

By realizing the universal asynchronous receiver-transmitter and the integrated circuit bus controller in the complex programmable logic chip, the extension mode of the simple peripheral bus controller is more universal, and the portability of the simple peripheral bus controller is improved on the premise of not increasing the hardware cost.

In this technical solution, optionally, the complex programmable logic chip 130 further includes an LPC transceiver 150;

the input terminal of the LPC transceiver 150 is connected to the output terminal of the PCH chip 120;

the output of LPC transceiver 150 is connected to the inputs of the uart 141 and the ic bus controller 142.

The transceiver is a device for signal conversion, and can convert an electric signal and an optical signal into each other, thereby ensuring smooth transmission of a data packet between two networks.

In this embodiment, LPC transceiver 150 and PCH chip 120 may be connected via a bus; LPC transceiver 150, uart 141, and ic bus controller 142 may be connected via a bus or may be directly connected via digital circuitry.

In this embodiment, LPC transceiver 150 is configured to receive the second signal transmitted by the output terminal of PCH chip 120, analyze the second signal, and transmit the analyzed second signal to uart 141 and/or ic bus controller 142.

By realizing the universal asynchronous transceiver and the integrated circuit bus controller in the complex programmable logic chip, the extension mode of the simple peripheral bus controller is more universal, and the portability of the simple peripheral bus controller is improved on the premise of not increasing the hardware cost.

In this embodiment, optionally, an input terminal of the LPC transceiver 150 is connected to an output terminal of the PCH chip 120 through an LPC bus.

The LPC bus is 33MHz 4bit parallel bus protocol based on Intel standard and can support various transaction types. For example, IO read/write, memory read/write, and DMA (Direct Memory Access) read/write, etc.

The LPC transceiver is connected with the PCH chip through the LPC bus, and the signal transmission efficiency between the LPC transceiver and the PCH chip can be improved.

In this embodiment, optionally, the output terminal of the LPC transceiver 150 is connected to the input terminals of the universal asynchronous receiver/transmitter 141 and the integrated circuit bus controller 142 through a digital circuit.

The digital circuit is a complex circuit composed of a plurality of logic gates and mainly processes digital signals.

In this embodiment, the second signal of LPC transceiver 150 may be transmitted by circuitry to both universal asynchronous receiver/transmitter 141 and integrated circuit bus controller 142.

The LPC transceiver is connected with the universal asynchronous transceiver and the integrated circuit bus controller through the digital circuit, and the signal transmission efficiency between the LPC transceiver and the universal asynchronous transceiver and the integrated circuit bus controller can be improved.

In this embodiment, optionally, the universal asynchronous receiver/transmitter 141 includes a control register, a data register, and a status register; the integrated circuit bus controller 142 includes a control register, a data register, and a status register.

In this embodiment, fig. 3 is a schematic diagram of a simple peripheral bus controller provided in this embodiment of the present application. RX denotes transmission data, and TX denotes reception data. As shown in fig. 3, the universal asynchronous receiver/transmitter 141 includes a control register, a data register, and a status register; integrated circuit bus controller 142 includes control registers, data registers, and status registers. The control register, the data register and the status register are used for being accessed by a driver through the LPC bus to drive the universal asynchronous receiver/transmitter 141 and the integrated circuit bus controller 142 to complete the operations of receiving and transmitting data and the like.

In this technical solution, optionally, the system includes:

the control register is used for driving the simple peripheral bus controller 140 to perform enabling, resetting and/or baud rate control according to the received control instruction;

the data register is used for driving the simple peripheral bus controller 140 to output first data to a first pin according to a preset baud rate and bus specification according to a received data sending instruction; the simple peripheral bus controller is also used for driving a second pin of the simple peripheral bus controller 140 to receive second data according to the received data receiving instruction;

the status register is used for driving the simple peripheral bus controller 140 to perform status setting, status anomaly detection and/or interrupt setting according to the received status instruction.

The first pin and the second pin may refer to a connection wire led out from an internal circuit of the simple peripheral bus controller 140 to a peripheral circuit, and all the pins form an interface of the simple peripheral bus controller 140.

The control register is used for realizing functions of enabling, resetting, baud rate control and the like; the data register is used for receiving and transmitting data, writing operation is initiated to the sending register through the LPC bus to trigger sending action of the simple peripheral bus, and the data are shifted and output to relevant pins according to preset baud rate and bus specifications. When in inputting, data is also transferred into the shift register under the control of baud rate processing logic through the receiving pin, the data with the appointed length is written into the data receiving register from the shift register after being received, and at the moment, a driving program can read the data receiving register through the LPC bus to complete the final data receiving; the status register is used for assisting the simple peripheral bus to realize the receiving and sending completion status setting, the simple peripheral bus abnormity detection, the generation and the report of related interrupt and the like.

Specifically, assuming that the simple peripheral bus system is implemented based on the Linux system, and the simple peripheral bus controller 140 implements access based on the LPC bus, the corresponding address of the simple peripheral bus controller 140 can be directly read and written through the IO space access instructions IN and OUT. The Linux kernel provides some common driver middleware of the simple peripheral bus, so that the driver design of the simple peripheral bus controller is relatively simple and universal.

In this embodiment, the universal asynchronous receiver/transmitter 141 may be registered with the Linux kernel as a tty (TeleTYpe) device, and the integrated circuit bus controller 142 may be registered with the kernel as i2c _ adapter. Wherein, i2c _ adapter encapsulates the struct device, so that the device can be registered in the kernel as a device. Then, the Linux system can access various peripherals mounted on the Linux system through various software tools through the bus, thereby realizing the replacement of the simple peripheral bus controller 140 in the PCH chip 120.

By setting the control register, the data register and the status register, the data receiving and transmitting operation of the simple peripheral bus controller can be realized.

In this technical solution, optionally, the output end of the central processing unit 110 is connected to the input end of the PCH chip 120 through a direct media interface bus.

Wherein, a Direct Media Interface (DMI) adopts a point-to-point connection mode, and the clock frequency is 100MHz.

In this embodiment, since there is no need to exchange too much data between the central processor 110 and the PCH chip 120, the central processor 110 and the PCH chip 120 can be connected by a direct media interface bus.

The central processing unit is connected with the PCH chip through the direct media interface bus, so that the signal transmission efficiency between the central processing unit and the PCH chip can be improved.

In this embodiment, a simple peripheral bus controller 140 is built on the complex programmable logic chip 130. The central processing unit 110 accesses the PCH chip 120 through a direct media interface bus, and accesses the complex programmable logic chip 130 through an LPC bus, thereby controlling the simple peripheral bus controller 140 in the complex programmable logic chip 130. The complex programmable logic chip 130 has an LPC transceiver, and the LPC transceiver can directly control the simple peripheral bus controller 140 after analyzing an LPC protocol, thereby realizing that the central processing unit 110 controls the simple peripheral bus controller 140.

According to the technical scheme of the embodiment of the utility model, the system comprises a central processing unit, a PCH chip and a complex programmable logic chip; the complex programmable logic chip comprises a simple peripheral bus controller; the output end of the central processing unit is connected with the input end of the PCH chip; the output end of the PCH chip is connected with the input end of the simple peripheral bus controller. By executing the technical scheme, the expansion mode of the simple peripheral bus controller is more universal, the transportability of the simple peripheral bus controller is improved on the premise of not increasing the hardware cost, the workload of the simple peripheral bus controller in adaptation with other devices is reduced, and the time to market of related products can be prolonged.

It should be understood that various forms of the flows shown above, reordering, adding or deleting steps, may be used. For example, the steps described in the present invention may be executed in parallel, may be executed sequentially, or may be executed in different orders, as long as the desired result of the technical solution of the present invention can be achieved, and the present invention is not limited thereto.

The above detailed description does not limit the scope of the present invention. It should be understood by those skilled in the art that various modifications, combinations, sub-combinations and substitutions may be made, depending on design requirements and other factors. Any modification, equivalent replacement, and improvement made within the spirit and principle of the present invention should be included in the protection scope of the present invention.

Claims (9)

1. A simple peripheral bus system is characterized in that the system comprises a central processing unit, a PCH chip and a complex programmable logic chip; the complex programmable logic chip comprises a simple peripheral bus controller;

the output end of the central processing unit is connected with the input end of the PCH chip; and the output end of the PCH chip is connected with the input end of the complex programmable logic chip so as to drive the simple peripheral bus controller to respond the access of the central processing unit.

2. The system of claim 1, wherein the simple peripheral bus controller comprises a universal asynchronous receiver transmitter and an integrated circuit bus controller.

3. The system of claim 2, wherein the complex programmable logic chip further comprises an LPC transceiver;

the input end of the LPC transceiver is connected with the output end of the PCH chip;

and the output end of the LPC transceiver is connected with the input ends of the universal asynchronous transceiver and the integrated circuit bus controller.

4. The system of claim 3, wherein the input of the LPC transceiver is coupled to the output of the PCH chip via an LPC bus.

5. The system of claim 3, wherein the output of the LPC transceiver is coupled to the input of the UART and the IC bus controller via digital circuitry.

6. The system of claim 2, wherein the universal asynchronous receiver/transmitter comprises a control register, a data register, and a status register; the integrated circuit bus controller includes a control register, a data register, and a status register.

7. The system of claim 1, wherein the output of the central processor and the input of the PCH chip are connected via a direct media interface bus.

8. The system of claim 6, wherein the system comprises:

the control register is used for driving the simple peripheral bus controller to carry out enabling, resetting and/or baud rate control according to the received control instruction;

the data register is used for driving the simple peripheral bus controller to output first data to the first pin according to a preset baud rate and bus specification according to a received data sending instruction; the simple peripheral bus controller is also used for driving a second pin of the simple peripheral bus controller to receive second data according to the received data receiving instruction;

and the state register is used for driving the simple peripheral bus controller to carry out state setting, state abnormity detection and/or interrupt setting according to the received state instruction.

9. The system of claim 1, wherein the system comprises:

the central processing unit generates a first signal according to the received instruction, and transmits the first signal to the input end of the PCH chip through the output end;

the PCH chip receives the first signal through an input end, generates a second signal according to the first signal, and transmits the second signal to an input end of the simple peripheral bus controller through an output end;

and the simple peripheral bus controller responds to the second signal after receiving the second signal.

Images