CN107066746B - Method for realizing PCA9555 function through CPLD based on I2C interface - Google Patents
Method for realizing PCA9555 function through CPLD based on I2C interface Download PDFInfo
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Abstract
The invention belongs to the field of server design, in particular to a method for realizing PCA9555 function through CPLD based on I2C interface; the method for realizing the PCA9555 function through the CPLD based on the I2C interface integrates the function originally realized by the PCA9555 on the CPLD, realizes the function of the I2C interface by the GPIO interface of the CPLD, and realizes the interface function by adopting VHDL language and utilizing the mechanism of a state machine. Meanwhile, the quantity of extensible GPIOs of the CPLD is far more than that of the PCA9555, the PCA9555 only has 16 GPIOs at most, and the CPLD can be arbitrarily extended according to the requirement, so that the scheme greatly saves the cost. Meanwhile, the CPLD is adopted for realizing, great convenience is brought to hardware debugging, the needed design scheme can be easily debugged and changed only by modifying and then burning the CPLD firmware on software, and the flexibility and the expandability of hardware debugging are greatly improved.
Description
Technical Field
The invention belongs to the field of server design, and particularly relates to a method for realizing PCA9555 function through a CPLD based on an I2C interface.
Background
At present, a backplane of a server or a memory adopts a PCA9555 chip connected to the backplane through I2C communication of a motherboard to perform read-write operation on GPIOs, the PCA9555 chip adopts I2C interface communication and can be used to expand at most 16 GPIOs, and the 16 GPIOs can be used by I2C to perform read-write operation. The PCA9555 chip can greatly reduce the number of signal pins connected between the main board and the back board, if the PCA9555 is not adopted, all GPIO signals are required to be connected to the main board (for example, 16 GPIO signals are required, and 16 pins or a cable is required to be connected to the main board), and the scheme adopting the PCA9555 can be realized only by two pin pins of an I2C interface.
However, in the current connection mode of the backplane of the server or the memory, as shown in fig. 1, a CPLD is generally adopted to decode the SGPIO to click the indicator lights of each hard disk, so that the existing backplane of the server or the memory generally has CPLD and PCA9555 chips at the same time.
The existing backplane of the server or the memory adopts I2C to communicate with PCA9555 for IO expansion, and one PCA9555 can only use 16 GPIOs at most, the number of the GPIOs is very limited, and if a plurality of GPIOs are realized, the number of chips of the PCA9555 must be increased. This can greatly increase the cost while increasing the complexity of board placement and routing.
However, the existing backplane of the server or the memory utilizes the CPLD to decode the SGPIO, so that the backplane still needs to adopt the design of the PCA9555 chip since it has many logic chips of the CPLD, which are GPIOI interfaces, and the use value of the CPLD, which is a complex programmable logic device, is greatly reduced. If the function of adding the PCA9555 is put on a CPLD for realization, and meanwhile, the communication mode and the access instruction and the I2C address of the CPLD accessed by the mainboard are the same as the I2C access instruction and the address of the PCA9555, so that the original I2C communication protocol of the mainboard can be realized without any modification, and simultaneously, the cost can be greatly saved, and the CPLD does not have an I2C interface, so that a method which can realize the I2C access by using the IO interface of the CPLD and does not change the communication access mode of the mainboard I2C is urgently needed.
Disclosure of Invention
The invention mainly aims to provide a method for realizing PCA9555 function through a CPLD based on an I2C interface, which is used for overcoming the problem that the structure of the existing backboard is too complicated due to the need of connecting a PCA9555 chip.
The invention is realized in such a way that a method for realizing PCA9555 function through CPLD based on I2C interface includes the following steps:
step A: an initialization step, wherein the initialization step is to configure a CPLD into an I2C Slave device;
and B: and an operation step, wherein the operation step is to connect the I2C communication interface of the mainboard to the GPIO interface of the CPLD.
General Purpose Input/Output (GPIO), or bus extender, has been used to simplify the expansion of I/O ports using industry standard I2C, SMBus, or SPI interfaces. GPIO products can provide additional control and monitoring functions when the microcontroller or chipset does not have sufficient I/O ports, or when the system needs to employ far-end serial communication or control.
The further technical scheme of the invention is as follows: and in the step A, the CPLD is prepared into the I2CSlave through a state machine mechanism.
The I2C (Inter-Integrated Circuit) bus is a two-wire serial bus developed by PHILIPS for connecting microcontrollers and their peripherals. Is a bus standard widely adopted in the field of microelectronic communication control. The synchronous communication method is a special form of synchronous communication, and has the advantages of few interface lines, simple control mode, small device packaging form, high communication speed and the like. The I2C bus supports any IC manufacturing process (CMOS, bipolar). Information is transferred between devices connected to the bus through a Serial Data (SDA) line and a Serial Clock (SCL) line. Each device has a unique address identification (whether a microcontroller-MCU, LCD driver, memory or keyboard interface) and can act as a transmitter or receiver (determined by the function of the device). The LCD driver can only act as a receiver and the memory can both receive and transmit data. In addition to the transmitter and receiver, the device may also be considered a master or a slave when performing data transmission (see table 1). The host is a device that initiates data transfers of the bus and generates a clock signal that allows the transfers. At this point, any addressed device is considered a slave.
The Complex Programmable Logic Device (CPLD) is developed from PAL and GAL devices, and is relatively large in scale and complex in structure, belonging to the field of large scale integrated circuit. The digital integrated circuit is a digital integrated circuit which is used by a user to construct logic functions according to respective needs. The basic design method is to generate corresponding target files by means of an integrated development software platform and methods such as schematic diagrams, hardware description languages and the like, and to transmit codes to a target chip through a download cable (programming in the system) so as to realize the designed digital system.
The further technical scheme of the invention is as follows: the state machine mechanism is implemented in VHDL language.
VHDL full name Very-High-Speed Integrated Circuit Hardware descriptionLanguage, born in 1982. VHDL was identified by IEEE and the United states department of defense as a standard hardware description language by the end of 1987. Since IEEE-1076 (87 edition for short), each EDA company successively introduced its VHDL design environment or announced that its design tool can interface with VHDL. In 1993, the IEEE revised VHDL, extended the content of VHDL from higher abstraction level and system description capability, and published a new version of VHDL, namely 1076 + 1993 version of IEEE standard, 93 for short. VHDL and Verilog are supported by numerous EDA companies as IEEE industry standard hardware description languages, and have become a de facto general hardware description language in the field of electronic engineering.
The scheme is further improved in that: the step A comprises the following sub-steps:
step A1: decomposing I2C into states;
step A2: the mainboard BMC determines the address of the CPLD device;
step A3: the mainboard BMC determines the operation of the CPLD equipment;
step A4: the CPLD parses and performs operations.
The scheme is further improved in that: the step A2 comprises the following sub-steps:
step A21: the mainboard BMC sends an addressing signal;
step A22: and the CPLD reads the addressing signal, sends a corresponding signal if the address of the addressing signal is the same as the address of the CPLD, and does not process the addressing signal if the address of the addressing signal is different from the address of the CPLD.
The scheme is further improved in that: and the CPLD reads the last bit of the addressing signal to carry out reading operation or writing operation.
The scheme is further improved in that: in the step a3, the motherboard BMC sends a specific operation signal that the CPLD can resolve.
The scheme is further improved in that: the step A also comprises a step A5: sending an end signal to stop operation; the step A5 is performed after the step A4.
The scheme is further improved in that: if the data operation is a CPLD read operation, step a5 is that the CPLD sends an end signal to the BMC; if the data operation is a CPLD write operation, step a5 is that the BMC sends an end signal to the CPLD.
The scheme is further improved in that: in the step a1, I2C is decomposed into an Idle state, a Read Address state, a Send _ ACK2 state, a Write _ CMD _ IO0 state, a Write _ CMD _ IO1 state, a Read _ CMD _ IO0 state, a Read _ CMD _ IO1 state, a Read _ CMD _ IO9 state, a Send _ ACK _1 state, a BMC _ COMMAND state, a Wait _ ACK _1 state, and a Wait _ ACK _2 state.
The invention has the beneficial effects that: the method for realizing the PCA9555 function through the CPLD based on the I2C interface integrates the function originally realized by the PCA9555 on the CPLD, realizes the function of the I2C interface by the GPIO interface of the CPLD, and realizes the interface function by adopting VHDL language and utilizing the mechanism of a state machine. Meanwhile, the quantity of extensible GPIOs of the CPLD is far more than that of the PCA9555, the PCA9555 only has 16 GPIOs at most, and the CPLD can be arbitrarily extended according to the requirement, so that the scheme greatly saves the cost. Meanwhile, the CPLD is adopted for realizing, great convenience is brought to hardware debugging, the needed design scheme can be easily debugged and changed only by modifying and then burning the CPLD firmware on software, and the flexibility and the expandability of hardware debugging are greatly improved. In addition, the I2C interface of the CPLD still adopts the command scheme of PCA9555, namely, the back board adopting a new CPLD scheme is directly replaced under the condition that the main board does not need to be changed, and the main board can be normally used without any software debugging. Therefore, the invention has the advantages of low cost and high debugging flexibility.
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In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings needed to be used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only some embodiments described in the present application, and other drawings can be obtained by those skilled in the art without creative efforts.
Fig. 1 is a schematic diagram of a connection manner between a motherboard and a backplane in the prior art.
FIG. 2 is a schematic diagram of a connection relationship between a motherboard and a backplane according to an embodiment of the present invention.
Fig. 3 is a schematic state machine diagram of a method for implementing the PCA9555 function through a CPLD based on an I2C interface according to an embodiment of the present invention.
Fig. 4 is a diagram of a hard disk write simulation result of a method for implementing the PCA9555 function through a CPLD based on an I2C interface according to an embodiment of the present invention.
Fig. 5 is a diagram of a hard disk reading simulation result of a method for implementing the PCA9555 function through a CPLD based on an I2C interface according to an embodiment of the present invention.
Detailed Description
The invention provides a method for realizing PCA9555 function through a CPLD based on an I2C interface. The present invention will be described in detail below with reference to the accompanying drawings and examples.
A method for realizing PCA9555 function through a CPLD based on an I2C interface comprises the following steps:
step A: an initialization step, wherein the initialization step is to configure a CPLD into an I2C Slave device;
and B: and an operation step, wherein the operation step is to connect the I2C communication interface of the mainboard to the GPIO interface of the CPLD.
Further: in the step A, the CPLD is configured into an I2C Slave through a state machine mechanism.
Further: the state machine mechanism is implemented in VHDL language.
In the invention, I2C is directly connected to the GPIO interface of the CPLD, a PCA9555 chip is directly saved from the hardware perspective, meanwhile, the IO number of the CPLD is very large, and a plurality of GPIO pins can be realized by one CPLD, thereby greatly improving the cost. The second diagram is a schematic diagram of the connection relationship of the scheme realized by the invention.
Further, the step A comprises the following sub-steps:
step A1: decomposing I2C into states;
step A2: the mainboard BMC determines the address of the CPLD device;
step A3: the mainboard BMC determines the operation of the CPLD equipment;
step A4: the CPLD parses and performs operations.
Further, the step a2 includes the following sub-steps:
step A21: the mainboard BMC sends an addressing signal;
step A22: and the CPLD reads the addressing signal, sends a corresponding signal if the address of the addressing signal is the same as the address of the CPLD, and does not process the addressing signal if the address of the addressing signal is different from the address of the CPLD.
Furthermore, the CPLD reads the last bit of the addressing signal to carry out reading operation or writing operation.
Further, in the step a3, the motherboard BMC sends a specific operation signal that the CPLD can resolve.
Further, the step a further includes a step a 5: sending an end signal to stop operation; the step A5 is performed after the step A4.
Further, if the data operation is a CPLD read operation, step a5 is that the CPLD sends an end signal to the BMC; if the data operation is a CPLD write operation, step a5 is that the BMC sends an end signal to the CPLD.
Further, in the step a1, I2C is decomposed into an Idle state, a Read Address state, a Send _ ACK2 state, a Write _ CMD _ IO0 state, a Write _ CMD _ IO1 state, a Read _ CMD _ IO0 state, a Read _ CMD _ IO1 state, a Read _ CMD _ IO9 state, a Send _ ACK _1 state, a BMC _ COMMAND state, a Wait _ ACK _1 state, and a Wait _ ACK _2 state.
The technical problem to be solved for realizing the scheme of the invention is that if the I2C communication with the mainboard is realized through the ordinary GPIO interface of the CPLD. The CPLD is not defined with an I2C communication interface, and to realize the I2C interface communication with the mainboard, the CPLD needs to be regarded as an I2C Slave device, VHDL language is adopted, the technical problem is solved by using a mechanism of a state machine, the state machine decomposes I2C into an Idle state, a Read Address state, a Send _ ACK2 state, a Write _ CMD _ IO0 state, a Write _ CMD _ IO1 state, a Read _ CMD _ IO0 state, a Read _ CMD _ IO1 state, a Read _ CMD _ IO9 state, a Send _ ACK _1 state, a BMC _ COMMAND state, a Wait _ ACK _1 state and a Wait _ ACK _2 state, the communication protocol of I2C is effectively decomposed into small modules similar to one by using the states, and the small modules jump to the next module for processing after the internal processing, and jump to an Idel state if the processing is completed. The jumping among the modules mainly follows the following principle, firstly, the Master device sends the address of the CPLD device, when the address value read by the CPLD device is the same as the self-set address, an ACK signal is sent to the Master device, if the address is different, the CPLD does not perform subsequent processing, then whether the Command is a read operation or a write operation is judged according to whether the last bit of the address value is high level or low level, the read operation is high level and the write operation is low level, the Master device sends Command data in the next step of the operation, the Command data is used for judging whether the read operation is performed on IO0/IO1/IO9 or the write operation is performed on IO0/IO1, the CPLD performs corresponding operation on the data, and after the data operation is completed, the CPLD waits for the Master device to Send a water _ ACK signal or sends a Send a Send _ ACK signal to indicate whether the data receiving or sending is completed.
In this example, the Master is a motherboard BMC, and the IO0, the IO1, the IO9, the IO0, the IO1, and other operation commands refer to various operations, which can be customized as needed, thereby implementing the function of the PA 9555.
And the third diagram is a state machine diagram which runs out after being realized by using the VHDL language.
The realization of the I2C interface function of the CPLD is realized through the state machine, and the written logic language is simulated by using the simulation software of the CPLD itself, and the obtained simulation result is shown in fig. 4 and 5. Wherein, the fourth diagram is the simulation result of the I2C write action, and the fifth diagram is the simulation result of the I2C read action.
The signal verification was performed on the actual backplane using the results of the state machine roll-out, and the oscillometric waveform was consistent with the roll-out waveform using PCA 9555.
The scheme of the invention based on the I2C interface to realize the PCA9555 function through the CPLD has the advantages of good cost saving and verified function and performance and reliability. Meanwhile, the communication reading mode of the I2C is the same as the PCA9555 mode, so that the communication reading mode can be easily realized by directly using the scheme under the condition that the mainboard of the server is not changed. In addition, the scheme of adopting the CPLD is easier to maintain later, and only the CPLD FW is required to be changed to easily realize the additional function. The device has the advantages of low specific cost, strong practicability, convenience in maintenance and flexibility in debugging.
The above description is only for the purpose of illustrating the preferred embodiments of the present invention and is not to be construed as limiting the invention, and any modifications, equivalents and improvements made within the spirit and principle of the present invention are intended to be included within the scope of the present invention.
Claims (6)
1. A method for realizing PCA9555 function through a CPLD based on an I2C interface is characterized by comprising the following steps:
step A: an initialization step, wherein the initialization step is to configure a CPLD into an I2C Slave device;
and B: the method comprises the following steps of (1) connecting an I2C communication interface of a mainboard to a GPIO interface of the CPLD;
wherein,
in the step A, CPLD is configured into an I2C Slave through a state machine mechanism;
the state machine mechanism is implemented in VHDL language;
the step A comprises the following sub-steps:
step A1: decomposing I2C into states;
step A2: the mainboard BMC determines the address of the CPLD device;
step A3: the mainboard BMC sends an operation signal to the CPLD equipment;
step A4: the CPLD analyzes and executes the operation signal;
the step A1 decomposes I2C into Idle state, Read Address state, Send _ ACK2 state, Write _ CMD _ IO0 state, Write _ CMD _ IO1 state, Read _ CMD _ IO0 state, Read _ CMD _ IO1 state, Read _ CMD _ IO9 state, Send _ ACK _1 state, BMC _ COMMAND state, WarwACK _1 state and WarwACK _2 state, and uses these states to effectively decompose the communication protocol of I2C into one-by-one modules, and these modules jump to the next module for processing after internal processing, and jump to the el state if processing is completed, and jump between these modules follows the following principle, firstly, the Master device sends the Address of CPLD device, when CPLD reads the same Address value as the Address set by itself, it will Send ACK signal to the Master device, if the Address is not the same, then the Master device will judge whether the last bit Address value is the last bit Read or Write operation level according to the last bit operation level, reading to be high level, writing to be low level, the next step of the operation is that the Master sends Command data, the Command data is used for judging whether the read operation is performed on IO0/IO1/IO9 or the write operation is performed on IO0/IO1, the CPLD analyzes the data to execute corresponding operation, and after the data operation is completed, the CPLD waits for the Master device to Send a signal of Wait _ ACk or sends a Send _ ACK signal to indicate whether the data receiving or sending is completed.
2. The method for implementing the PCA9555 function through a CPLD based on the I2C interface of claim 1, wherein the step A2 comprises the following substeps:
step A21: the mainboard BMC sends an addressing signal;
step A22: and the CPLD reads the addressing signal, sends a corresponding signal if the address of the addressing signal is the same as the address of the CPLD, and does not process the addressing signal if the address of the addressing signal is different from the address of the CPLD.
3. The method of claim 2 for implementing PCA9555 function via CPLD based on I2C interface, wherein the CPLD reads or writes by the last bit interpretation of addressing signal.
4. The method of claim 3, wherein the motherboard BMC in step A3 sends specific operation signals that can be resolved by CPLD based on I2C interface to realize PCA9555 function by CPLD.
5. The method for implementing the PCA9555 function through a CPLD based on the I2C interface of claim 4, wherein the step A further comprises the step A5: sending an end signal to stop operation; the step A5 is performed after the step A4.
6. The method of claim 5 for implementing PCA9555 function through CPLD based on I2C interface, wherein: if the operation is a CPLD reading operation, the step A5 is that the CPLD sends an end signal to the BMC; if the operation is a CPLD write operation, step a5 is that the BMC sends an end signal to the CPLD.
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| CN107783862B (en) * | 2017-09-27 | 2021-07-20 | 郑州云海信息技术有限公司 | An 8-way server master-slave BMC reset control method based on PCA9555 |
| CN108170245B (en) * | 2018-01-25 | 2022-04-29 | 郑州云海信息技术有限公司 | Control system and method for physical key operation of server and server management system |
| CN109117347A (en) * | 2018-07-10 | 2019-01-01 | 深圳市同泰怡信息技术有限公司 | The method of BMC control hard disk indication lamp state |
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| Application of FPGA in high-speed CMOS digital image acquisition and color recognition system;XUEMEI GUO等;《JOURNAL OF CHEMICAL AND PHARMACEUTICAL RESEARCH》;20141231;第791-798页 * |
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