CN216014148U - Server and server backboard - Google Patents

Abstract

The application discloses a server and a server backboard, which are used for improving the compatibility of a storage device supported by the server and reducing the complexity of a circuit of the server. The server comprises a server mainboard and a server backboard, wherein the server mainboard comprises a processor, the server backboard comprises a controller, the server backboard is used for connecting the first storage device, and the processor is connected with the controller; the processor is used for sending a first signal to the controller, and the controller is used for converting the first signal into a third signal and sending the third signal after receiving the first signal from the processor; the third signal is of a different signal type than the first signal; and/or the controller is used for converting a fourth signal into a second signal after receiving the fourth signal from the first storage device and sending the second signal to the processor; the processor is used for receiving a second signal from the controller; the second signal is of the same signal type as the first signal and the fourth signal is of a different signal type than the second signal.

Description

Server and server backboard

Technical Field

The present application relates to the field of communications technologies, and in particular, to a server and a server backplane.

Background

In the existing server, in order to support multiple types of storage devices, a corresponding circuit must be provided in a server motherboard of the server for each type of storage device.

For example, for a non-volatile memory (NVME), a circuit of a Peripheral Component Interconnect Express (PCIE) interface needs to be separately provided to support NVME type memory access to a server. For another example, for the SATA type memory, before connecting to the processor on the server motherboard of the server, when a circuit of a corresponding interface is separately set, a corresponding south bridge chip (PCH) needs to be additionally set, and in the X86 architecture server, a vendor removes an original PCH design, which results in that the Serial Advanced Technology Attachment (SATA) cannot access the processor by using the original circuit.

SUMMERY OF THE UTILITY MODEL

The application provides a server and a server backboard, which are used for improving the compatibility of a storage device supported by the server and reducing the complexity of a circuit of the server.

In a first aspect, the present application provides a server, where the server includes a server motherboard and a server backplane, the server motherboard includes a processor, the server backplane includes a controller, the server backplane is used to connect to a first storage device, and the processor is connected to the controller; the processor is used for sending a first signal to the controller, and the controller is used for converting the first signal into a third signal and sending the third signal after receiving the first signal from the processor; the third signal is of a different signal type than the first signal;

and/or the controller is used for converting a fourth signal into a second signal after receiving the fourth signal from the first storage device and sending the second signal to the processor; the processor is used for receiving a second signal from the controller; the second signal is of the same signal type as the first signal and the fourth signal is of a different signal type than the second signal.

The conversion of different types of signals is realized in the same circuit by the controller. The third signal is a signal received by the first storage device, the fourth signal is a signal sent by the first storage device, and the types of the third signal and the fourth signal correspond to the type of the first storage device, wherein the type of the first storage device may be an SAS type, an SATA type, an NVME type, and the like. When the type supported by the first memory device is a memory device type that does not support the first signal and the second signal, the controller may perform signal conversion, that is, convert the first signal into the third signal, so that the first memory device may recognize the third signal. And/or the first storage device may send a fourth signal to the controller, and the controller may convert the fourth signal into a second signal, so that the processor may recognize information in the fourth signal from the first storage device, so that the server supports different types of storage devices, compatibility of the storage devices supported by the server is improved, and complexity of a circuit of the server is reduced.

According to a possible implementation manner, the server motherboard further comprises a first interface, the processor is connected with the first interface, the server backplane further comprises a second interface and a third interface, the second interface is used for connecting the first interface and the controller, the third interface is used for being connected with the first storage device, and the controller is connected with the third interface.

A unified interface may be used between the controller and the processor when the first memory means are of different types, taking into account that no conversion of signal types is required between the controller and the processor. For example, signals between the controller and the processor are transmitted through the first interface and the second interface, that is, the second interface is connected with the controller, and the first interface is connected with the second interface and used for connecting the backplane and the motherboard.

For example, when the first storage device is an SAS memory or an SATA memory, the first interface and the second interface may both use a high speed signal connector (HSBP CONN), without providing different types of interfaces for different types of circuits provided for connecting different first storage devices, as in the prior art. For example, when the SATA signal sent by the PCH is transmitted, MINI SAS HD CONN interfaces need to be respectively set on the server motherboard and the server backplane on the corresponding circuits. When a PCIE signal sent by the processor is transmitted, on a corresponding circuit, the server motherboard and the server backplane need to be provided with an HSBP CONN interface respectively.

By adopting the scheme, the interfaces of the server main board and the server back board can be unified, the compatibility of the connectable or expandable storage device of the server is improved, and the complexity of the design and maintenance of the server is reduced.

In a possible implementation manner, the server motherboard further includes a first interface, the processor is connected with the first interface, the server backplane further includes a second interface and a fourth interface, the first interface is connected with the second interface, and the second interface is used for connecting the fourth interface; the fourth interface is used for connecting with the second storage device.

The second storage device can be an NVME type storage device, and by the method, the server can be compatible with the existing mode of accessing the second storage device, so that the flexibility of server design is improved. In addition, the controller does not need to process signals corresponding to the second storage device, and the complexity of the controller can be reduced.

In a possible implementation manner, the server motherboard further includes a first card slot; the first card slot is used for connecting the adapter card, the processor is connected with the first card slot, and the first card slot is connected with the first storage device;

the processor is used for sending a first signal to the adapter card, and the adapter card is used for converting the first signal into a third signal and sending the third signal after receiving the first signal from the processor;

and/or the adapter card is used for converting a fourth signal into a second signal after receiving the fourth signal from the first storage device and sending the second signal to the processor; the processor is used for receiving a second signal from the adapter card.

By the method, the first card slot on the server mainboard can be used for connecting the adapter card, the adapter card can convert the first signal from the processor into a third signal which can be identified by the first storage device, and the adapter card can also convert the fourth signal from the first storage device into a second signal which can be identified by the processor.

Optionally, the adapter card may further identify a type of the signal from the storage device, and determine a signal to be converted. By the method, the flexibility of server design is improved.

According to a possible implementation manner, the server motherboard further comprises a first interface, the first card slot is connected with the fifth interface, the server backboard further comprises a sixth interface, the fifth interface is connected with the sixth interface, and the sixth interface is used for connecting the first storage device.

For example, when the first storage device is an SAS-type storage device or an SATA-type storage device, the first interface and the second interface may use high-speed signal connectors without providing different types of interfaces for a plurality of types of circuits provided for connecting the first storage device, as in the related art. The compatibility of the server supporting the memory types is improved.

In a possible implementation manner, the first interface and the second interface are high-speed signal connectors HSBP CONN.

In one possible implementation, the controller is any one of: a control chip or a riser card.

In a second aspect, the present application provides a server backplane, where a server corresponding to the server backplane further includes a server motherboard, the server backplane includes a controller, the server backplane is used to connect to a first storage device, and the processor and the controller are used to connect to a processor on the server motherboard;

the controller is used for converting the first signal into a third signal after receiving the first signal from the processor and sending the third signal to the first storage device, wherein the signal type of the third signal is different from that of the first signal;

and the controller is used for receiving a fourth signal from the first storage device, converting the fourth signal into a second signal and sending the second signal to the processor, wherein the second signal is the same as the first signal in signal type, and the fourth signal is different from the second signal in signal type.

By the method, the configuration capability of the storage device of the server backboard is improved and the platform compatibility of the server backboard is improved on the premise of not changing the mainboard of the server.

In a possible implementation manner, the server backplane further includes a second interface and a third interface;

the second interface is used for connecting the processor and the controller, the third interface is used for connecting the first storage device, and the controller is connected with the third interface.

The second interface receives the first signal from the first interface and sends the first signal to the controller, and the controller converts the first signal into a third signal and sends the third signal to the third interface.

There is no need to provide different types of interfaces for different types of circuits provided for connecting the first storage device, as in the prior art. The complexity of server backplane design is reduced.

In a possible implementation manner, the server backplane further includes a second interface and a fourth interface;

the second interface is used for connecting the processor and the fourth interface; the fourth interface is used for connecting with the second storage device.

Through the mode, the server can be compatible with the existing mode of accessing the second storage device, and the flexibility of server design is improved. In addition, the controller does not need to process signals corresponding to the second storage device, and the complexity of the controller can be reduced. The flexibility of server backplane design is improved.

In one possible implementation, the second storage device is an NvMe type storage device, and the first storage device is any one of: storage devices of SAS, SATA, NvMe type.

In one possible implementation, the type of the first signal or the second signal is any one of the following: PCIE x1, PCIE x2, PCIE x4, PCIE x8, PCIE x16, where "x + number" represents different transmission speeds of PCIE signals.

The type of the third signal or the fourth signal is any one of:

the SAS type supporting the serial small computer system interface protocol and the SAS type supporting the small computer system interface management protocol;

a SATA type supporting a SATA1.0 interface, a SATA type supporting a SATA 2.0 interface, and a SATA type supporting a SATA 3.0 interface;

support PCIE x1, PCIE x2, PCIE x4, PCIE x8, PCIE x 16.

In a third aspect, the present application provides a server motherboard, where a server corresponding to the server motherboard further includes a server backplane, and the server backplane is used for connecting to a first storage device;

the server mainboard comprises a processor and a first card slot, wherein the first card slot is used for connecting a switching card, the processor is connected with the first card slot, and the first card slot is connected with the first storage device;

the processor is used for sending a first signal to the adapter card, and the adapter card is used for receiving the first signal from the processor, converting the first signal into a third signal and sending the third signal;

and/or the adapter card is used for converting a fourth signal into a second signal after receiving the fourth signal from the first storage device and sending the second signal to the processor; the processor is used for receiving the second signal from the adapter card.

The adapter card on the server mainboard can convert the types of the signals. The first signal is converted into a third signal. The third signal is a signal supporting the type of storage device connected to the server. In addition, the adapter card can also identify the signal type from the storage device and judge the signal needing conversion. By the method, the flexibility of the design of the server-to-main board is improved.

In a possible implementation manner, the server motherboard further includes a fifth interface, and the server backplane further includes a sixth interface, where the first card slot is connected to the fifth interface, and the sixth interface is used to connect to the first storage device.

The fifth interface is used for receiving the signal from the first card slot and sending the signal to the sixth interface.

There is no need to provide different types of interfaces for different types of circuits provided for connecting the first storage device, as in the prior art. The complexity of server mainboard design is reduced, and the compatibility of the server mainboard is improved.

In a possible implementation manner, the server motherboard further includes a first interface, the first card slot is connected to the first interface, the server backplane further includes a second interface and a fourth interface, the first interface is connected to the second interface, and the second interface is used to connect to the fourth interface; the fourth interface is used for connecting with a second storage device.

Drawings

FIG. 1 is a schematic diagram of a server according to an embodiment of the present application;

FIG. 2 is a schematic diagram of a server according to an embodiment of the present application;

FIG. 3 is a schematic diagram of a server according to an embodiment of the present application;

FIG. 4 is a schematic diagram of a server according to an embodiment of the present application;

FIG. 5 is a schematic diagram of a server according to an embodiment of the present application;

FIG. 6 is a schematic diagram of a server according to an embodiment of the present application;

FIG. 7 is a schematic diagram of a server according to an embodiment of the present application;

FIG. 8 is a schematic diagram of a server according to an embodiment of the present application;

FIG. 9 is a schematic diagram of a server according to an embodiment of the present application;

FIG. 10 is a schematic diagram of a server according to an embodiment of the present application;

FIG. 11 is a schematic diagram of a server according to an embodiment of the present application;

fig. 12 is a schematic diagram of a server according to an embodiment of the present application.

Detailed Description

In order to make the technical solutions of the present application better understood by those of ordinary skill in the art, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings.

Additional features and advantages of the application will be set forth in the description which follows, and in part will be obvious from the description, or may be learned by the practice of the application. The objectives and other advantages of the application may be realized and attained by the structure particularly pointed out in the written description and claims hereof as well as the appended drawings.

FIG. 1 is a schematic diagram of a server that may support SATA, NVME storage.

Wherein the first path as shown in fig. 1 may be used to access the memory of the NVME. In the first path, a processor on a server mainboard is used for sending a PCIE signal, after the HSBPCONN receives the PCIE signal, the PCIE signal is sent to a high-speed signal connector on a backboard through a high-speed cable connecting line, the high-speed signal connector on the backboard sends the PCIE signal to a memory connector, and an NVME memory connected to the memory connector receives the signal.

The second path shown in fig. 1 may be used to access SATA memory. In the second path, the chip PCH on the server motherboard is connected to the processor. The PCH chip is used for sending SATA signals, the MINISASHD connector sends the SATA signals to the high-speed signal connector on the backboard through the high-speed cable connecting line after receiving the SATA signals, the MINISASHD connector on the backboard sends the SATA signals to the hard disk connector, and the SATA storage connected to the hard disk connector receives the signals.

However, with the update of the server platform technology, in the x86 server platform, the vendor removes the PCH chip on the server motherboard, which results in that the server cannot support the SATA memory, which limits the configuration of the server backplane memory, cannot flexibly configure memories of various models according to the requirements, and reduces the platform compatibility of the server backplane.

FIG. 2 is a schematic diagram of a server that may support SAS, SATA, NVME storage.

Wherein the first path as shown in fig. 2 may be used to access the memory of the NVME. Taking the case that the processor sends a signal to the storage as an example, in the first path, the processor on the server motherboard sends a PCIE signal to the HSBPCONN, and after receiving the PCIE signal, the HSBPCONN sends the PCIE signal to the high-speed signal connector on the backplane through a high-speed cable (cable) connection line, and the high-speed signal connector on the backplane sends the PCIE signal to the hard disk connector, and the NVME memory connected to the hard disk connector receives the signal.

The second path shown in fig. 2 may be used to access memory of the SAS. Taking the example that the processor sends a signal to the storage, in the second path, the processor on the server motherboard may be connected to a Redundant Array of Independent Disks (RAID) card or a Host Bus Adapter (HBA), the RAID card or the HBA card may be configured to convert the signal sent by the processor into an SAS signal and send the SAS signal to an MINISASHD connector, after receiving the SAS signal, the MINISASHD connector sends the SAS signal to a high-speed signal connector on the backplane through a high-speed cable connection line, the MINISASHD connector on the backplane sends the SAS signal to a hard disk connector, and the SAS memory connected to the hard disk connector may obtain data sent by the processor to the SAS memory according to the SAS signal.

In this way, the server needs to connect to the SAS type memory, and a corresponding second path (for example, the second path shown in fig. 2) must be set for the memory, and in the second path, a RAID card or an HBA card needs to be additionally set, which occupies a space on a server motherboard, reduces flexibility of the server, and increases difficulty in designing the server.

The third path shown in fig. 2 can be used to access SATA type memory. Taking the case that the processor sends a signal to the storage, the processor on the server motherboard sends a PCIE signal to the RAID card or the HBA card, the RAID card or the HBA card may be configured to convert the signal sent by the processor into an SATA signal, and send the SATA signal to the MINISASHD connector, after receiving the SATA signal, the MINISASHD connector sends the SATA signal to the high-speed signal connector on the backplane through the high-speed cable connection line, the MINISASHD connector on the backplane sends the SATA signal to the hard disk connector, and the SAS memory connected to the hard disk connector may obtain data sent by the processor to the SATA memory according to the SATA signal.

In this way, the server needs to connect to the SATA memory, and a corresponding third path (for example, the third path shown in fig. 2) must be set for the memory, and in the third path, a RAID card or an HBA card needs to be additionally set, which results in occupying a space on a server motherboard, reducing flexibility of the server, and improving difficulty in designing the server.

Based on the above problems, the present application provides a server, a server motherboard, and a server backplane, which are used to improve the compatibility of a storage device supported by the server and reduce the complexity of a circuit of the server.

Fig. 3 is a schematic diagram of a server according to an embodiment of the present application, including a server motherboard and a server backplane, where the server motherboard includes a processor, and the server backplane includes a controller, and the controller is respectively connected to the processor and a storage device. The controller may be a conversion protocol type chip that may be used to convert the first signal to a third signal or to convert the fourth signal to the first signal.

The processor is used for sending a first signal to the controller, and the controller converts the first signal into a third signal and sends the third signal after receiving the first signal from the processor; the third signal is of a different signal type than the first signal;

and/or the controller is used for receiving a fourth signal from the first storage device, converting the fourth signal into a second signal and sending the second signal to the processor; the processor receives a second signal from the controller; the second signal is of the same signal type as the first signal and the fourth signal is of a different signal type than the second signal.

Wherein the server has access to different types of first storage means. The types of the first storage device include: SAS type storage devices, SATA type storage devices, NVME type storage devices.

The conversion of different types of signals is realized in the same circuit by the controller. The third signal is a signal received by the first storage device, the fourth signal is a signal sent by the first storage device, and the types of the third signal and the fourth signal correspond to the type of the first storage device, wherein the type of the first storage device may be an SAS type, an SATA type, an NVME type, and the like. When the type supported by the first storage device is a storage device type which does not support the first signal and the second signal, the controller may perform signal conversion, that is, convert the first signal into the third signal, or convert the second signal into the fourth signal, so that the first storage device may identify the third signal, or the first storage device may send the fourth signal to the controller, so that the processor may convert the fourth signal into the second signal through the controller, so as to identify information in the fourth signal from the first storage device, so that the server supports different types of storage devices, thereby improving the compatibility of the storage devices supported by the server and reducing the complexity of a circuit of the server.

For the plurality of types of first storage devices, examples one to three are illustrated below.

Example 1

Fig. 4 is a schematic diagram of a server according to an embodiment of the present application, including a server motherboard and a server backplane, where the server motherboard includes a processor, and the server backplane includes a controller, and the server backplane is connected to a first storage device. The processor is connected with the controller.

The server motherboard further comprises a first interface 411, the processor is connected with the first interface 411, the server backplane further comprises a second interface 421 and a third interface 431, the second interface 421 is used for connecting the first interface 411 and the controller, the third interface 431 is used for connecting the first storage device, and the controller is connected with the third interface 431. The type of the first storage device may be NVME type, SAS type, SATA type.

Taking the first storage device as an SATA type storage device as an example, when the SATA type storage device is inserted into the third interface of the server backplane, the SATA type storage device may send a connection request signal to the controller, where the connection request signal may be used for the processor in the server to identify the SATA type storage device. After the controller receives the SATA signal from the SATA type storage device, the controller may convert the SATA signal into a PCIE signal after recognizing the SATA signal. And then, the controller sends the PCIE signal to the processor, and the processor obtains a connection request signal sent by the SATA type storage device according to the PCIE signal. The processor may generate a connection request response signal when determining that the SATA type storage device can be connected according to the connection request signal, where the connection request response signal may be a PCIE signal. The processor sends the connection response signal to the controller, and after receiving the connection response signal, the controller can convert the connection response signal into a SATA signal and send the SATA signal to the SATA type storage device. So far, the access of the SATA type storage device is successful.

After the access is successful, signals can be transmitted between the processor and the first storage device through the controller.

In the process that the processor sends a signal to the first storage device, the processor sends a first signal to the controller, and after the controller receives the first signal from the processor, the controller converts the first signal into a third signal and sends the third signal; the third signal is of a different signal type than the first signal. The first signal may be a PCIE signal, for example, the first signal may be PCIE x1, PCIE x2, PCIE x4, PCIE x8, and PCIE x 16. The third signal may be a PCIE signal, a SAS signal, a SATA signal.

In some embodiments, the processor may send a PCIE signal to the first interface 411, the first interface 411 sends the received PCIE signal to the second interface 421 through a high-speed cable connection line, where the first interface 411 and the second interface 421 may be high-speed signal connectors, the second interface sends the PCIE signal to the controller, the controller converts the PCIE signal into a SATA signal and sends the SATA signal to the third interface 431, where the third interface 431 is a hard disk connector, and a SATA-type storage device connected to the hard disk connector receives the SATA signal.

In the process that the first storage device sends a signal to the processor, the first storage device sends a fourth signal to the controller, and the controller converts the fourth signal into a second signal and sends the second signal after receiving the fourth signal from the first storage device; the fourth signal is of a different signal type than the second signal. The second signal may be a PCIE signal, for example, the second signal may be PCIE x1, PCIE x2, PCIE x4, PCIE x8, and PCIE x 16. Where "x + number" indicates different transmission speeds of PCIE signals. The fourth signal may be a PCIE signal, a SAS signal, a SATA signal.

In some embodiments, the SATA type memory may send a SATA signal to the third interface 431, the third interface 431 then sends the received SATA signal to the controller, the controller converts the received SATA signal into a PCIE signal and sends the PCIE signal to the second interface 421, the second interface sends the PCIE signal to the first interface 411 through the high-speed cable connection line, the first interface sends the received PCIE signal to the processor, and the processor receives the PCIE signal.

A unified interface may be used between the controller and the processor when the first memory means are of different types, taking into account that no conversion of signal types is required between the controller and the processor. For example, signals between the controller and the processor are transmitted through the first interface and the second interface, that is, the second interface is connected with the controller, and the first interface is connected with the second interface and used for connecting the backplane and the motherboard.

By adopting the scheme of the application, when the storage devices of different models are connected, the unification of the interfaces can be realized. The method and the device improve the compatibility of the connectable or expandable storage device of the server and reduce the complexity of the design and maintenance of the server.

Example two

Fig. 5 is a schematic diagram of a server according to an embodiment of the present application, including a server motherboard and a server backplane, where the server motherboard includes a processor, and the server backplane includes a controller, and the server backplane is connected to a storage device. The processor is connected with the controller.

The server motherboard further comprises a first interface 411, the processor is connected with the first interface 411, the server backplane further comprises a second interface 421 and a third interface 431, the second interface 421 is used for connecting the first interface 411 and the controller, the third interface 431 is used for connecting the first storage device, and the controller is connected with the third interface 431.

When the first storage device accesses the third interface on the server backplane, the connection may be established with the processor through the controller, and the connection establishment process may refer to the connection process of the SATA type storage device in example one, which is not described herein again.

Taking a storage device of the SAS type as an example of the first storage device, when a signal is transmitted between the processor and the first storage device, in a process that the processor sends a signal to the first storage device, the processor may send a PCIE signal to the first interface 411, the first interface 411 sends the received PCIE signal to the second interface 421 through a high-speed cable connection line, where the first interface 411 and the second interface 421 may be high-speed signal connectors, the second interface sends the PCIE signal to the controller, the controller converts the PCIE signal into an SAS signal and sends the SAS signal to the third interface 431, and the third interface 431 is a hard disk connector, and the storage device of the SAS type connected to the hard disk connector receives the SAS signal.

In the process that the first storage device sends a signal to the processor, the SAS type memory sends an SAS signal to the third interface 431, the third interface 431 sends the received SAS signal to the controller, the controller converts the received SAS signal into a PCIE signal and sends the PCIE signal to the second interface 421, the second interface sends the PCIE signal to the first interface 411 through the high-speed cable connection line, the first interface sends the received PCIE signal to the processor, and the processor receives the PCIE signal.

A unified interface may be used between the controller and the processor when the first memory means are of different types, taking into account that no conversion of signal types is required between the controller and the processor. For example, signals between the controller and the processor are transmitted through the first interface and the second interface, that is, the second interface is connected with the controller, and the first interface is connected with the second interface and used for connecting the backplane and the motherboard.

By adopting the scheme of the application, when the storage devices of different models are connected, the unification of the interfaces can be realized. The method and the device improve the compatibility of the connectable or expandable storage device of the server and reduce the complexity of the design and maintenance of the server.

Example three

Fig. 6 is a schematic diagram of a server according to an embodiment of the present application, including a server motherboard and a server backplane, where the server motherboard includes a processor, and the server backplane includes a controller, and the server backplane is connected to a storage device. The processor is connected with the controller.

The server motherboard further comprises a first interface 411, the processor is connected with the first interface 411, the server backplane further comprises a second interface 421 and a third interface 431, the second interface 421 is used for connecting the first interface 411 and the controller, the third interface 431 is used for connecting the first storage device, and the controller is connected with the third interface 431.

Taking the first storage device as an NVME type storage device as an example, when the first storage device accesses the third interface on the server backplane, the connection may be established with the processor through the controller, and the connection establishment process may refer to the connection process of the SATA hard disk in example one, which is not described herein again.

In transmitting signals between the first memory device and the processor, during the process of the processor sending signals to the first memory device, the processor may send PCIE signals to the first interface 411, the first interface 411 sends the received PCIE signals to the second interface 421 through a high-speed cable connection, the first interface 411 and the second interface 421 here can be high-speed signal connectors, the second interface sends PCIE signals to the controller, the controller receives PCIE signals (first signals) from the second interface, the signal type of the first signals can be PCIE x1, PCIE x2, PCIE x4, PCIE x8, PCIE x16, and converts it to PCIE signals of a PCIE type other than the signal type of the first signal, and sends the signal to the third interface 431, where the third interface 431 may be a hard disk connector, and the NVME type storage device connected to the hard disk connector receives the PCIE signal.

In the process of sending a signal to the processor by the first storage device, the NVME-type memory sends a PCIE signal to the third interface 431, the third interface 431 then sends the received PCIE signal to the controller, the controller receives a PCIE signal (fourth signal) from the third interface, the signal type of the fourth signal may be PCIE x1, PCIE x2, PCIE x4, PCIE x8, and PCIE x16, converts the signal into a PCIE signal of a PCIE type other than the signal type of the fourth signal, and sends the PCIE signal to the second interface 411, the second interface sends the PCIE signal to the first interface 411 through a high-speed cable connection line, the first interface sends the received PCIE signal to the processor, and the processor receives the PCIE signal.

A unified interface may be used between the controller and the processor when the first memory means are of different types, taking into account that no conversion of signal types is required between the controller and the processor. For example, signals between the controller and the processor are transmitted through the first interface and the second interface, that is, the second interface is connected with the controller, and the first interface is connected with the second interface and used for connecting the backplane and the motherboard.

By adopting the scheme of the application, when the storage devices of different models are connected, the unification of the interfaces can be realized. The method and the device improve the compatibility of the connectable or expandable storage device of the server and reduce the complexity of the design and maintenance of the server.

Example four

With reference to examples one to three, as shown in fig. 7, the schematic diagram of another server provided in the embodiment of the present application includes a server motherboard and a server backplane, where the server motherboard includes a processor, the server backplane includes a controller, and the server backplane is connected to a storage device. The processor is connected with the controller.

The server motherboard further comprises a first interface 411, the processor is connected with the first interface 411, the server backplane further comprises a second interface 421 and a third interface 431, the second interface 421 is used for connecting the first interface 411 and the controller, the third interface 431 is used for connecting the first storage device, and the controller is connected with the third interface 431. Wherein the first storage device may be any one of a SAS type storage device or a SATA type storage device. For a specific implementation, reference may be made to examples one to three, which are not described herein again.

The server backplane further comprises a fourth interface 432, the second interface 422 is used for connecting the first interface 412 and the controller, the fourth interface 432 is used for connecting with the second storage device, and the controller is connected with the fourth interface 432.

Wherein the second storage device may be an NVME type storage device.

Taking the second storage device as an NVME type storage device as an example, when the second storage device accesses the fourth interface on the server backplane, the second storage device may establish a connection with the processor, and a connection establishment process is performed, which is not limited in this application.

Taking the second storage device as an NVME type storage device as an example, when signals are transmitted between the second storage device and the processor, in a process that the processor sends signals to the first storage device, the processor may send PCIE signals to the first interface 412, the first interface 412 sends received PCIE signals to the second interface 422 through a high-speed cable connection line, where the first interface 412 and the second interface 422 may be high-speed signal connectors, the second interface further sends PCIE signals to the third interface 432, where the third interface 432 may be a hard disk connector, and the NVME type storage device connected to the hard disk connector receives the PCIE signals.

In the process of sending a signal to the processor by the first storage device, the NVME-type storage device sends a PCIE signal to the third interface 432, the third interface 432 sends the received PCIE signal to the second interface 412, the second interface sends the PCIE signal to the first interface 412 through the high-speed cable connection line, the first interface sends the received PCIE signal to the processor, and the processor receives the PCIE signal.

Through the mode, the server can be compatible with the existing mode of accessing the second storage device, and the flexibility of server design is improved. In addition, the controller does not need to process signals corresponding to the second storage device, and the complexity of the controller can be reduced. The flexibility of server backplane design is improved.

Example five

As shown in fig. 8, another schematic diagram of a server provided in the embodiment of the present application includes a server motherboard and a server backplane, where the server motherboard includes a processor and a first card slot, and the server backplane is used to connect to a first storage device, and the processor is connected to the first card slot. The first card inserting opening is used for connecting the adapter card. The riser card may be a conversion protocol type chip that may be used to convert the first signal to the third signal and/or to convert the fourth signal to the first signal.

After the first storage device is connected to the server backboard, the first storage device can be connected with the processor through the adapter card connected to the first card slot. The first storage device may send a connection request signal to the riser card, which may be used for a processor in the server to identify the first storage device. After the adapter card receives the connection request signal from the first storage device, the adapter card can convert the signal into a PCIE signal after recognizing the signal. Then, the adapter card may send the PCIE signal to the processor, and the processor obtains the connection request signal sent by the first storage device according to the PCIE signal. The processor may generate a connection request response signal when determining that the first storage apparatus may be connected according to the connection request signal, where the connection request response signal may be a PCIE signal. The processor sends the connection response signal to the adapter card, and after receiving the connection response signal, the adapter card can convert the connection response signal into a signal supported by the first storage device and send the signal to the first storage device. So far, the first storage device is successfully accessed.

After the access is successful, signals can be transmitted between the processor and the first storage device through the adapter card.

In the process that the processor sends a signal to the first storage device, the processor sends a first signal to the adapter card, and the adapter card converts the first signal into a third signal and sends the third signal after receiving the first signal from the processor; the third signal is of a different signal type than the first signal. The first signal may be a PCIE signal, for example, the first signal may be PCIE x1, PCIE x2, PCIE x4, PCIE x8, and PCIE x 16. The third signal may be a PCIE signal, a SAS signal, a SATA signal of a different type than the first signal.

In the process that the first storage device sends a signal to the processor, the first storage device sends a fourth signal to the adapter card, and the adapter card converts the fourth signal into a second signal and sends the second signal after receiving the fourth signal from the first storage device; the fourth signal is of a different signal type than the second signal. The second signal may be a PCIE signal, for example, the second signal may be PCIE x1, PCIE x2, PCIE x4, PCIE x8, and PCIE x 16. The fourth signal may be a PCIE signal, a SAS signal, a SATA signal.

By the method, the first card slot on the server mainboard can be used for connecting the adapter card, the adapter card can convert the first signal from the processor into a third signal which can be identified by the first storage device, and the adapter card can also convert the fourth signal from the first storage device into a second signal which can be identified by the processor.

Optionally, the adapter card may further identify a type of the signal from the storage device, and determine a signal to be converted. By the method, the flexibility of server design is improved.

Example six

As shown in fig. 9, another schematic diagram of a server provided in the embodiment of the present application includes a server motherboard and a server backplane, where the server motherboard includes a processor and a first card slot, and the server backplane is connected to a storage device. The first card slot is used for connecting a switching card, the processor is connected with the first card slot, the first card slot is connected with the fifth interface 411, the fifth interface 411 is connected with the sixth interface 421 through a high-speed cable connecting line, the sixth interface 421 is connected with the third interface 431, and the third interface 431 is connected with the first storage device.

The first storage device may be NVME type storage device, SAS type storage device, SATA type storage device.

Taking the example that the first storage device is an SATA type storage device, when the first storage device accesses the third interface on the server backplane, the connection may be established with the processor through the adapter card, and a connection establishment process may refer to the method in example five, which is not described herein again.

After the access is successful, signals can be transmitted between the processor and the first storage device through the adapter card.

In the process that the processor sends a signal to the first storage device, the processor sends a first signal to the adapter card, and the adapter card converts the first signal into a third signal and sends the third signal after receiving the first signal from the processor; the third signal is of a different signal type than the first signal. The first signal may be a PCIE signal, for example, the first signal may be PCIE x1, PCIE x2, PCIE x4, PCIE x8, and PCIE x 16. The third signal may be a PCIE signal, a SAS signal, a SATA signal.

In some embodiments, the processor may transmit a PCIE signal to the adapter card, the adapter card converts the PCIE signal into an SATA signal and transmits the SATA signal to the fifth interface 511, the fifth interface 511 transmits the received SATA signal to the sixth interface 521 through the high-speed cable connection line, where the fifth interface 511 and the sixth interface 521 may be high-speed signal connectors, the sixth interface further transmits the SATA signal to the third interface 431, where the third interface 431 may be a hard disk connector, and the SATA signal is received by the SATA type storage device connected to the hard disk connector.

In the process that the first storage device sends a signal to the processor, the first storage device sends a fourth signal to the adapter card, and the adapter card converts the fourth signal into a second signal and sends the second signal after receiving the fourth signal from the first storage device; the fourth signal is of a different signal type than the second signal. The second signal may be a PCIE signal, for example, the second signal may be PCIE x1, PCIE x2, PCIE x4, PCIE x8, and PCIE x 16. The fourth signal may be a PCIE signal, a SAS signal, a SATA signal.

In some embodiments, the SATA type memory may send a SATA signal to the third interface 431, the third interface 431 then sends the received SATA signal to the sixth interface 521, the sixth interface 521 sends the SATA signal to the fifth interface 511 through the high-speed cable connection line, the fifth interface sends the received SATA signal to the adaptor card, the adaptor card converts the SATA signal into a PCIE signal and sends the PCIE signal to the processor, and the processor receives the PCIE signal.

By adopting the scheme of the application, when the storage devices of different models are connected, the unification of the interfaces can be realized. For example, when a SATA type storage device and an SAS type storage device are connected, the same type of fifth interface may be used, so that the compatibility of the connectable or expandable storage device of the server is improved, and the complexity of designing and maintaining the server is reduced.

Example seven

As shown in fig. 10, another schematic diagram of a server is provided for the embodiment of the present application, and includes a server motherboard and a server backplane, where the server motherboard includes a processor and a first card slot, the first card slot is used to connect a riser card, the processor is connected with the first card slot, the first card slot is connected with a first interface 411, the first interface 411 is connected with a second interface 421 through a high-speed cable connection line, the second interface 421 is connected with a third interface 431, the third interface 431 is connected, and a first storage device is included. Wherein the first storage device may be a SAS type storage device and a SATA type storage device.

The server backplane further comprises a fourth interface 432, the second interface 422 is configured to connect to the fourth interface, and the fourth interface 432 is configured to connect to a second storage device. Wherein the second storage device may be an NVME type storage device.

Taking the example that the first storage device is an SATA type storage device, when the first storage device accesses the third interface on the server backplane, the connection may be established with the processor through the adapter card, and a connection establishment process may refer to the method in example five, which is not described herein again. After the access is successful, signals can be transmitted between the processor and the first storage device through the adapter card. Specifically, reference may be made to the manner of example five or example six, which is not described herein again.

Taking the example that the second storage device is an NVME type storage device, when the second storage device accesses the fourth interface on the server backplane, the second storage device may establish a connection with the processor, and a connection establishment process may refer to the method in example five, which is not described herein again. After the access is successful, signals can be transmitted between the processor and the second storage device through the adapter card. Specifically, reference may be made to the method in example four, which is not described herein again.

When the storage devices of different models are connected, the server can be accessed in a plurality of modes and signals are transmitted. The compatibility of the storage device which can be connected or expanded by the server and the flexibility of the design of the server are improved.

Example eight

With reference to example four to example six, as shown in fig. 11, another schematic diagram of a server is provided for the embodiment of the present application, including a server motherboard, a server backplane, a processor on the server motherboard, a first card slot and a first interface 411, and a fifth interface 511; the server backboard is provided with a controller, a second interface 421, a sixth interface 521 and a third interface 431.

In the first path, when the first storage device accesses the third interface on the server backplane, the controller may establish a connection with the processor, and a connection establishment process may refer to the manners in examples one to three, which is not described herein again. After the access is successful, signals can be transmitted between the processor and the first storage device through the controller. Specifically, reference may be made to examples in a manner of example three, which is not described herein again.

In the second path, when the first storage device is connected to the third interface on the server backplane, the connection may be established with the processor through the adapter card, and a connection establishment process may refer to the method in example five, which is not described herein again. After the access is successful, signals can be transmitted between the processor and the first storage device through the adapter card. Specifically, reference may be made to the manner of example five or example six, which is not described herein again.

When the storage devices of different models are connected, the server can be accessed in a plurality of modes and signals are transmitted. The compatibility of the storage device which can be connected or expanded by the server and the flexibility of the design of the server are improved.

Example nine

With reference to example four to example six, as shown in fig. 12, a schematic diagram of another server is provided for the embodiment of the present application. The server mainboard comprises a processor, a first card slot, a first interface 411, a first interface 412 and a fifth interface 511; the server main board comprises a controller second interface 421, a controller second interface 422, a controller third interface 431, a controller fourth interface 432 and a controller sixth interface 521.

In the first path, taking the second storage device as an NVME type storage device as an example, when the second storage device accesses the fourth interface on the server backplane, a connection may be established with the processor, and a connection establishment process may refer to the method in example five, which is not described herein again. After the access is successful, signals can be transmitted between the processor and the second storage device through the adapter card. Specifically, reference may be made to the method in example four, which is not described herein again.

In the second path, when the first storage device accesses the third interface on the server backplane, the controller may establish a connection with the processor, and a connection establishment process may refer to the manner in examples one to three, which is not described herein again. After the access is successful, signals can be transmitted between the processor and the first storage device through the controller. Specifically, reference may be made to examples in a manner of example three, which is not described herein again.

In the third path, when the first storage device is accessed to the third interface on the server backplane, a connection may be established between the adapter card and the processor, and a connection establishment process may refer to the method in example five, which is not described herein again. After the access is successful, signals can be transmitted between the processor and the first storage device through the adapter card. Specifically, reference may be made to the manner of example five or example six, which is not described herein again.

When the storage devices of different models are connected, the server can be accessed in a plurality of modes and signals are transmitted. The compatibility of the storage device which can be connected or expanded by the server and the flexibility of the design of the server are improved.

It is noted that the terms first, second and the like in the description and in the claims of the present application are used for distinguishing between similar elements and not necessarily for describing a particular sequential or chronological order. It is to be understood that the data so used is interchangeable under appropriate circumstances such that the embodiments of the application described herein are capable of operation in sequences other than those illustrated or described herein. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with the present application. Rather, they are merely examples consistent with certain aspects of the present application, as detailed in the appended claims.

As will be appreciated by one skilled in the art, embodiments of the present application may be provided as a method, system, or computer program product. Accordingly, the present application may take the form of an entirely hardware embodiment, an entirely software embodiment or an embodiment combining software and hardware aspects. Furthermore, the present application may take the form of a computer program product embodied on one or more computer-usable storage media (including, but not limited to, disk storage, CD-ROM, optical storage, and the like) having computer-usable program code embodied therein.

The present application is described with reference to flowchart illustrations and/or block diagrams of methods, apparatus (systems), and computer program products according to the application. It will be understood that each flow and/or block of the flow diagrams and/or block diagrams, and combinations of flows and/or blocks in the flow diagrams and/or block diagrams, can be implemented by computer program instructions. These computer program instructions may be provided to a processor of a general purpose computer, special purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, create means for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.

These computer program instructions may also be stored in a computer-readable memory that can direct a computer or other programmable data processing apparatus to function in a particular manner, such that the instructions stored in the computer-readable memory produce an article of manufacture including instruction means which implement the function specified in the flowchart flow or flows and/or block diagram block or blocks.

These computer program instructions may also be loaded onto a computer or other programmable data processing apparatus to cause a series of operational steps to be performed on the computer or other programmable apparatus to produce a computer implemented process such that the instructions which execute on the computer or other programmable apparatus provide steps for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.

It will be apparent to those skilled in the art that various changes and modifications may be made in the present application without departing from the spirit and scope of the application. Thus, if such modifications and variations of the present application fall within the scope of the claims of the present application and their equivalents, the present application is intended to include such modifications and variations as well.

Claims (12)

1. A server is characterized by comprising a server mainboard and a server backplane, wherein the server mainboard comprises a processor, the server backplane comprises a controller, the server backplane is used for connecting a first storage device, and the processor is connected with the controller;

the processor is used for sending a first signal to the controller, and the controller is used for converting the first signal into a third signal and sending the third signal after receiving the first signal from the processor; the third signal is of a different signal type than the first signal;

and/or the controller is used for converting a fourth signal into a second signal after receiving the fourth signal from the first storage device and sending the second signal to the processor; the processor is configured to receive the second signal from the controller; the second signal is of the same signal type as the first signal, and the fourth signal is of a different signal type than the second signal.

2. The server according to claim 1, wherein the server motherboard further includes a first interface, the processor is connected to the first interface, the server backplane further includes a second interface and a third interface, the second interface is used to connect the first interface and the controller, the third interface is used to connect to the first storage device, and the controller is connected to the third interface.

3. The server according to claim 2, wherein the server motherboard further comprises a first interface, the processor is connected to the first interface, the server backplane further comprises a second interface and a fourth interface, the first interface is connected to the second interface, and the second interface is used for connecting to the fourth interface; the fourth interface is used for connecting with a second storage device.

4. The server of claim 3, wherein the server motherboard further comprises a first card slot; the first card slot is used for connecting a switching card, the processor is connected with the first card slot, and the first card slot is connected with the first storage device;

the processor is used for sending a first signal to the adapter card, and the adapter card is used for converting the first signal into a third signal and sending the third signal after receiving the first signal from the processor;

and/or the adapter card is used for converting a fourth signal into a second signal after receiving the fourth signal from the first storage device and sending the second signal to the processor; the processor is used for receiving the second signal from the adapter card.

5. The server according to claim 4, wherein the server motherboard further includes a fifth interface, the first card slot is connected to the fifth interface, the server backplane further includes a sixth interface, the fifth interface is connected to the sixth interface, and the sixth interface is used for connecting the first storage device.

6. A server, according to any one of claims 3 to 5, wherein said second storage means is a non-volatile memory standard, NvMe type, storage means, and said first storage means is any one of: storage devices of SAS, SATA, NvMe type.

7. The server according to any of claims 1-5, wherein the type of the first signal or the second signal is any of: PCIE x1, PCIE x2, PCIE x4, PCIE x8, PCIE x 16;

the type of the third signal or the fourth signal is any one of:

the SAS type supporting the serial small computer system interface protocol and the SAS type supporting the small computer system interface management protocol;

a SATA type supporting a SATA1.0 interface, a SATA type supporting a SATA 2.0 interface, and a SATA type supporting a SATA 3.0 interface;

support PCIE x1, PCIE x2, PCIE x4, PCIE x8, PCIE x 16.

8. The server backboard is characterized in that a server corresponding to the server backboard further comprises a server mainboard, the server backboard comprises a controller, the server backboard is used for being connected with a first storage device, and the controller is used for being connected with a processor on the server mainboard;

the controller is used for converting a first signal into a third signal after receiving the first signal from the processor, and sending the third signal to the first storage device, wherein the third signal is different from the first signal in signal type;

and/or the controller is configured to convert a fourth signal into a second signal after receiving the fourth signal from the first storage device, and send the second signal to the processor, where the second signal is of the same signal type as the first signal, and the fourth signal is of a different signal type from the second signal.

9. The server backplane of claim 8, wherein the server backplane further comprises a second interface and a third interface;

the second interface is used for connecting the processor and the controller, the third interface is used for connecting the first storage device, and the controller is connected with the third interface.

10. The server backplane of claim 8, wherein the server backplane further comprises a second interface and a fourth interface;

the second interface is used for connecting the processor and the fourth interface; the fourth interface is used for connecting with a second storage device.

11. The server backplane of claim 10, wherein the second storage device is a non-volatile memory standard (NvMe) type storage device, and the first storage device is any one of: storage devices of SAS, SATA, NvMe type.

12. A server backplane according to any of claims 8-10, wherein the type of the first signal or the second signal is any of: PCIE x1, PCIE x2, PCIE x4, PCIE x8, PCIE x 16;

the type of the third signal or the fourth signal is any one of:

the SAS type supporting the serial small computer system interface protocol and the SAS type supporting the small computer system interface management protocol;

a SATA type supporting a SATA1.0 interface, a SATA type supporting a SATA 2.0 interface, and a SATA type supporting a SATA 3.0 interface;

support PCIE x1, PCIE x2, PCIE x4, PCIE x8, PCIE x 16.

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