CN107145430A - A kind of method for realizing NVMe SSD lightings by CPLD based on I2C interfaces - Google Patents

A kind of method for realizing NVMe SSD lightings by CPLD based on I2C interfaces Download PDF

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Publication number
CN107145430A
CN107145430A CN201710267533.XA CN201710267533A CN107145430A CN 107145430 A CN107145430 A CN 107145430A CN 201710267533 A CN201710267533 A CN 201710267533A CN 107145430 A CN107145430 A CN 107145430A
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cpld
nvme ssd
interfaces
lightings
realizing
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冯葆
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Shenzhen Tong Yi Yi Information Technology Co Ltd
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Shenzhen Tong Yi Yi Information Technology Co Ltd
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    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00Error detection; Error correction; Monitoring
    • G06F11/30Monitoring
    • G06F11/32Monitoring with visual or acoustical indication of the functioning of the machine
    • G06F11/324Display of status information
    • G06F11/325Display of status information by lamps or LED's
    • G06F11/326Display of status information by lamps or LED's for error or online/offline status
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14Handling requests for interconnection or transfer
    • G06F13/20Handling requests for interconnection or transfer for access to input/output bus
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F2213/00Indexing scheme relating to interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F2213/0016Inter-integrated circuit (I2C)

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Quality & Reliability (AREA)
  • Debugging And Monitoring (AREA)

Abstract

The invention belongs to server design field, especially a kind of method for realizing NVMe SSD lightings by CPLD based on I2C interfaces;The information that the method for NVMe SSD lightings that what this programme was provided realized based on I2C interfaces by CPLD is then attached to CPLD using CPU I2C and sent to decode CPU carries out the functions of indicator light to NVMe SSD working conditions.Effectively NVMe SSD working condition can intuitively be displayed as common SATA or SAS hard disks, user interface by macroscopic appearance state can only lamp just can intuitively judge NVMe SSD working condition, it is very directly perceived convenient.The present invention is easier using CPLD scheme in follow-up maintenance in addition, can easily be realized if additional function to be increased only needs to change CPLD FW.Specific cost is low, practical, and it is convenient to safeguard, debugs flexible superiority.

Description

A kind of method for realizing NVMe SSD lightings by CPLD based on I2C interfaces
Technical field
NVMe SSD are realized by CPLD based on I2C interfaces the invention belongs to server design field, especially one kind The method of lighting.
Background technology
With the development of technology, the species of storage hard disk is also being continuously updated the replacement, the NVMe of current technology forefront SSD has also stepped into everybody visual field, and ripe with NVMe SSD technology convergence, NVMe SSD also commercially surface currents Row gets up, and can be to step into how server storage field effectively intuitively displays NVMe SSD working condition The one big difficult point in NVMe fields.SATA hard disc or SAS hard disks known to us are all to be decoded to hard disk by SGPIO Working condition, then goes to carry out the working condition that decoding SPIO removes acquisition SATA or SAS hard disks by CPLD or PIC, and What NVMe SSD were walked is PCIE bus buses, and its working condition is that CPU compares clearly in itself, therefore NVMe SSD work shape State is only shown by CPU I2C.And CPU this group of I2C is primarily used to be PCIE hot-plug's.
Existing NVMe SSD working conditions are to be connected to PIC by I2C, and NVMe is realized by PIC decoding I2C communication datas Warm connection function.What PIC was connected above is the two signals of the IFDET# and HDD_PRESENT# of SFF-8639 interfaces to sentence It is fixed whether to insert NVMe SSD hard disks.
Whether the working station indicator of NVMe SSD hard disks can intuitively embody as SATA or SAS hard disks Come, at present temporary not no good scheme, using it is most be exactly that CPU I2C signals are realized into NVMe SSD warm connection function, And NVMe movable indicator lamp is all the signal output lighting carried in itself by NVMe SSD, but how to realize NVMe SSD Report an error indicator lamp and Locate(In place)Indicator lamp combination is a big shortcoming of prior art.
For this reason, it is necessary to design a kind of new lighting system, NVMe can be realized in the case where not changing hardware SSD positions and working condition lighting.
The content of the invention
The main object of the present invention is to provide a kind of side for realizing NVMe SSD lightings by CPLD based on I2C interfaces Method, for overcoming the problem of existing Moped Scooter can not realize body-building.
The present invention is achieved in that a kind of method for realizing NVMe SSD lightings by CPLD based on I2C interfaces, Comprise the following steps:
Step A:CPLD is configured to I2C Slave equipment by initialization step, the initialization step system;
Step B:State read step, the state read step system CPU passes through the shape with the CPLD reading NVMe SSD postponed State;
Step C:Lighting step, the lighting step system cpu command matches somebody with somebody the CPLD postponed and lights corresponding wrong indicator lamp.Pass through CPLD realizes decoding lighting, eliminates the step of being decoded by PIC.
I2C(Inter-Integrated Circuit)Bus is that the twin wire developed by PHILIPS companies is serially total Line, for connecting microcontroller and its ancillary equipment.It is a kind of widely used bus standard in microelectronics Control on Communication field.It A kind of special shape of synchronous communication, few with interface line, control mode is simple, and device packing forms are small, traffic rate compared with High the advantages of.I2C buses support any IC production technologies (CMOS, ambipolar).Pass through serial data(SDA)Line and it is serial when Clock(SCL)Line transmission information between the device of bus is connected to.Each device has a unique Address Recognition(It is either micro- Controller --- MCU, LCD driver, memory or keyboard interface), and can serve as a transmitter or receiver (Determined by the function of device).LCD drivers can only be as receiver, and memory then can both be received can send number According to.In addition to transmitters and receivers, device can also be counted as main frame or slave when performing data transfer(It is shown in Table 1). Main frame is the data transfer of initialization bus and generation allow transmission clock signal device.Now, any device being addressed Part is considered as slave.
CPLD (Complex Programmable Logic Device) CPLD, be from PAL and The device that GAL device developments come out, comparatively scale is big, complicated, belongs to large scale integrated circuit scope.It is a kind of use Family voluntarily digital integrated electronic circuit of constitutive logic function according to respective need.Its basic design method is soft by Integrated Development Part platform, with methods such as schematic diagram, hardware description languages, generates corresponding file destination, passes through download cable(" in system " is compiled Journey)Code is sent in objective chip, the digital display circuit of design is realized.
The present invention further technical scheme be:Realize that CPLD is configured to I2C by state machine mechanism in the step A Slave。
The present invention further technical scheme be:The state machine mechanism is realized by VHDL language.
The full name Very-High-Speed Integrated Circuit Hardware Description of VHDL Language, is born in nineteen eighty-two.The end of the year 1987, VHDL confirms as standard hardware description language by IEEE and U.S. Department of Defense. From IEEE-1076(Referred to as 87 editions)Afterwards, each EDA companies release one after another the VHDL design environments of oneself, or announce setting for oneself Meter instrument can be with VHDL interfaces.1993, IEEE was revised to VHDL, from higher abstraction hierarchy and System describe energy VHDL content is extended in power, the 1076-1993 versions of the VHDL of redaction, i.e. ieee standard, referred to as 93 editions is disclosed.VHDL With industry standard hardware description languages of the Verilog as IEEE, obtain numerous EDA companies and support, in electronic engineering field, Common hardware description language on coming true.
The present invention further technical scheme be:The step B include it is following step by step:
Step B1:CPU reads NVMe SSD state in place by I2C interfaces from CPLD;
Step B2:CPU recognizes the working condition of NVMe SSD hard disks.
The present invention further technical scheme be:The step B1 include it is following step by step:
Step B11:CPLD obtains SFF-8639 interface signal level;
Step B12:The hard disk type that CPLD judges to connect on the SFF-8639 interfaces by level signal.
The present invention further technical scheme be:Judged in the step B12 by IFDET# and PRSENT# signal levels Grafting hard disk type.
The present invention further technical scheme be:The rule followed in the step B12 is, as IFDET# and PRSENT# When signal is all high level, represent that this SFF-8639 does not access any hard disk;When IFDET# is low and PRSENT# is high When, what expression was now accessed is NVMe SSD hard disks;When IFDET# and PRSENT# are low, what expression was now accessed is SATA or SAS hard disks.
The present invention further technical scheme be:The step C include it is following step by step:
Step C1:NVMe SSD hard disks error informations are transmitted to CPLD by BIOS by I2C interfaces;
Step C2:CPLD lights correspondence NVMe SSD wrong indicator lamp.
The present invention further technical scheme be:The step A include it is following step by step:
Step A1:I2C is resolved into some states;
Step A2:Mainboard BMC determines CPLD device addresses.
The present invention further technical scheme be:The step A2 include it is following step by step:
Step A21:Mainboard BMC sends address signal;
Step A22:CPLD reads the address signal, corresponding signal is sent if address signal address is identical with itself, if seeking Location Signal Message Address is different from itself, does not process.
The beneficial effects of the invention are as follows:What this programme was provided realizes NVMe SSD lightings based on I2C interfaces by CPLD The method information that CPLD is then attached to using CPU I2C sent to decode CPU carry out finger to NVMe SSD working conditions Show lamp function.Effectively NVMe SSD working condition can intuitively be shown as common SATA or SAS hard disks Out, user interface by macroscopic appearance state can only lamp just can intuitively judge NVMe SSD working condition, very It is directly perceived convenient.The present invention is easier using CPLD scheme in follow-up maintenance in addition, is only needed to more if to increase additional function Changing CPLD FW just can easily realize.Specific cost is low, practical, and it is convenient to safeguard, debugs flexible superiority.
Brief description of the drawings
, below will be to embodiment or existing in order to illustrate more clearly of the embodiment of the present application or technical scheme of the prior art There is the accompanying drawing used required in technology description to be briefly described, it should be apparent that, drawings in the following description are only this Some embodiments described in application, for those of ordinary skill in the art, on the premise of not paying creative work, Other accompanying drawings can also be obtained according to these accompanying drawings.
Fig. 1 is the method provided in an embodiment of the present invention for realizing NVMe SSD lightings by CPLD based on I2C interfaces Framework schematic diagram.
Fig. 2 is the method provided in an embodiment of the present invention for realizing NVMe SSD lightings by CPLD based on I2C interfaces State machine diagram.
Fig. 3 is the method provided in an embodiment of the present invention for realizing NVMe SSD lightings by CPLD based on I2C interfaces Hard disk writes analog result figure.
Fig. 4 is the method provided in an embodiment of the present invention for realizing NVMe SSD lightings by CPLD based on I2C interfaces Hard disk reads analog result figure.
Embodiment
The present invention provides a kind of method for realizing NVMe SSD lightings by CPLD based on I2C interfaces.Below in conjunction with attached The present invention is described in detail for figure and embodiment.
A kind of method for being realized NVMe SSD lightings by CPLD based on I2C interfaces, is comprised the following steps:
Step A:CPLD is configured to I2C Slave equipment by initialization step, the initialization step system;
Step B:State read step, the state read step system CPU passes through the shape with the CPLD reading NVMe SSD postponed State;
Step C:Lighting step, the lighting step system cpu command matches somebody with somebody the CPLD postponed and lights corresponding wrong indicator lamp.Pass through CPLD realizes decoding lighting, eliminates the step of being decoded by PIC.
Further, realize that CPLD is configured to I2C Slave by state machine mechanism in the step A.
Further, the state machine mechanism is realized by VHDL language.
Further, the step B include it is following step by step:
Step B1:CPU reads NVMe SSD state in place by I2C interfaces from CPLD;
Step B2:CPU recognizes the working condition of NVMe SSD hard disks.
Further, the step B1 include it is following step by step:
Step B11:CPLD obtains SFF-8639 interface signal level;
Step B12:The hard disk type that CPLD judges to connect on the SFF-8639 interfaces by level signal.
Further, grafting hard disk type is judged by IFDET# and PRSENT# signal levels in the step B12.
Further, the rule followed in the step B12 is, when IFDET# and PRSENT# signals are all high level Wait, represent that this SFF-8639 does not access any hard disk;When IFDET# is low and PRSENT# is high, represent what is now accessed It is NVMe SSD hard disks;When IFDET# and PRSENT# are low, what expression was now accessed is SATA or SAS hard disks.
Further, the step C include it is following step by step:
Step C1:NVMe SSD hard disks error informations are transmitted to CPLD by BIOS by I2C interfaces;
Step C2:CPLD lights correspondence NVMe SSD wrong indicator lamp.
Further, the step A include it is following step by step:
Step A1:I2C is resolved into some states;
Step A2:Mainboard BMC determines CPLD device addresses.
Further, the step A2 include it is following step by step:
Step A21:Mainboard BMC sends address signal;
Step A22:CPLD reads the address signal, corresponding signal is sent if address signal address is identical with itself, if seeking Location Signal Message Address is different from itself, does not process.
The information that the present invention is then attached to CPLD using CPU I2C and sent to decode CPU NVMe SSD are worked The functions of indicator light of state.Because CPU has to realize by this I2C to NVMe SSD warm connection functions, therefore from hard It is that need not increase new hardware circuit for above part circuit, it is only necessary to share this to I2C to decode.We utilize CPLD's Programmability, an I2C Slave equipment is configured to by CPLD, and CPU reads NVMe shape in place by I2C interfaces from CPLD State, its state in place is realized by SFF-8639 P4 and P10 pin IFDET# and PRSENT#, but the two signals are all When for high level, represent that this SFF-8639 does not access any hard disk, when IFDET# is low and PRSENT# is high, represent That now access is NVMe SSD, and when IFDET# and PRSENT# is low, what expression was now accessed is that SATA or SAS are hard Disk, therefore CPLD is readily recognizable by whether having access NVMe SSD using the two signals, is then transmitted to CPU by I2C, And now BIOS can be parsed smoothly very much.The movable indicator lamp that CPLD carries NVMe SSD in itself simultaneously is included in correspondence Interface position is used for recognizing NVME SSD activity instruction state.On the other hand, can to recognize NVMe SSD well hard by CPU The working condition of disk, when finding that NVMe SSD hard disks go wrong, the information that BIOS can be reported an error by this passes through I2C It is given to CPLD and goes to decode, identical also is easily identified out for Locate state instruction.
The present invention can effectively by NVMe SSD working condition as common SATA or SAS hard disks intuitively Display, user interface by macroscopic appearance state can only lamp just can intuitively judge NVMe SSD working condition, It is very directly perceived convenient.
Decode I2C communication interface standard to realize the function of lighting invention applies CPLD, BIOS is obtained by CPU NVMe PCIE SSD work is taken, when PCIE SSD operation irregularities are detected, system can be connect by Hotplug I2C Mouth passes out information to allow CPLD to remove a little corresponding wrong indicator lamp, if similarly wanting to obtain correspondence above system interface PCIE SSD Locate positions when, information can be also passed out by I2C interfaces to allow CPLD to go to a correspondence SSD positions Indicator lamp.
Connection block diagram between CPU HOTPLUG I2C and CPLD is as shown in Figure 1.
Realize that this scheme of the invention needs the technical barrier solved to be if realized by CPLD common GPIO interface Communicated with the direct I2C of CPU.CPLD is not define I2C communication interfaces, to realize I2C interface communications with mainboard, it is necessary to By CPLD as an I2C Slave equipment, we use VHDL language, and the mechanism of utilization state machine is difficult to solve this technology Topic, Fig. 2 is the state machine diagram run out after being realized using VHDL language.
I2C by being resolved into Idle states, Read Address states, Send_ACK1 states, Read_CMD by state machine State, Write_CMD states, Wait_ACK_1 states, Wait_ACK_2 states, using these states effectively the logical of I2C Letter agreement resolves into similar little module one by one, and next module can be jumped to after these little module inter-process are complete and is carried out Processing, if processing, which is completed, will jump to Idel states.Redirecting between these modules mainly follows following principle, first First CPU sends I2C address, and ack signal will be sent when when the address that the address value that CPLD is read is set with itself To CPU, if the different CPLD in address is without subsequent treatment, after CPLD, which sends ack signal, is given to CPU, CPLD according to Last position of address value is high level or low level to judge this order be read operation or write operation, is read as high level, Low level is written as, if read operation, CPU can read the desired information of CPU over there from CPLD, such as NVMe SSD's IFDET# signals, if reading this signal for low level, representative has NVMe SSD in place, otherwise not in place, and CPU can root in addition The state of corresponding hard disk indication lamp is issued into CPLD, the form solution that CPLD will can be sent according to CPU according to the working condition of hard disk The LED state of a controls easily recognized are analysed into, CPLD meeting waiting for CPU equipment sends Wait_ACk signal after the completion of data manipulation Or CPLD sends Send_ACK signals to indicate the reception of data or send whether completed.
The realization of CPLD I2C interface functions is realized by state machine, while the simulation software pair carried using CPLD The logical language write is emulated, and obtained simulation result is as follows.
Fig. 3 is the simulation result that I2C writes action, and Fig. 4 is the simulation result of I2C readings action.As can be seen from the figure lead to This method is crossed to can be very good to show NVMe SSD working condition.
What this programme was provided realizes that the method for NVMe SSD lightings uses CPU I2C based on I2C interfaces by CPLD It is then attached to CPLD and carries out functions of indicator light to NVMe SSD working conditions to decode the information that CPU sends.Can be effective Ground intuitively displays NVMe SSD working condition as common SATA or SAS hard disks, and user interface passes through Macroscopic appearance state can only lamp just can intuitively judge NVMe SSD working condition, it is very directly perceived convenient.This other hair Bright use CPLD scheme is easier in follow-up maintenance, can be light if additional function to be increased only needs to change CPLD FW Pine realizes.Specific cost is low, practical, and it is convenient to safeguard, debugs flexible superiority.
The foregoing is merely illustrative of the preferred embodiments of the present invention, is not intended to limit the invention, all essences in the present invention Any modifications, equivalent substitutions and improvements made within refreshing and principle etc., should be included in the scope of the protection.

Claims (10)

1. a kind of method for realizing NVMe SSD lightings by CPLD based on I2C interfaces, it is characterised in that including following step Suddenly:
Step A:CPLD is configured to I2C Slave equipment by initialization step, the initialization step system;
Step B:State read step, the state read step system CPU passes through the shape with the CPLD reading NVMe SSD postponed State;
Step C:Lighting step, the lighting step system cpu command matches somebody with somebody the CPLD postponed and lights corresponding wrong indicator lamp.
2. the method according to claim 1 for realizing NVMe SSD lightings by CPLD based on I2C interfaces, its feature It is:Realize that CPLD is configured to I2C Slave by state machine mechanism in the step A.
3. the method according to claim 2 for realizing NVMe SSD lightings by CPLD based on I2C interfaces, its feature It is:The state machine mechanism is realized by VHDL language.
4. the method according to claim 1 for realizing NVMe SSD lightings by CPLD based on I2C interfaces, its feature Be, the step B include it is following step by step:
Step B1:CPU reads NVMe SSD state in place by I2C interfaces from CPLD;
Step B2:CPU recognizes the working condition of NVMe SSD hard disks.
5. the method according to claim 4 for realizing NVMe SSD lightings by CPLD based on I2C interfaces, its feature It is:The step B1 include it is following step by step:
Step B11:CPLD obtains SFF-8639 interface signal level;
Step B12:The hard disk type that CPLD judges to connect on the SFF-8639 interfaces by level signal.
6. the method according to claim 5 for realizing NVMe SSD lightings by CPLD based on I2C interfaces, its feature It is:Grafting hard disk type is judged by IFDET# and PRSENT# signal levels in the step B12.
7. the method according to claim 6 for realizing NVMe SSD lightings by CPLD based on I2C interfaces, its feature It is:The rule followed in the step B12 is when IFDET# and PRSENT# signals are all high level, to represent this SFF- 8639 do not access any hard disk;When IFDET# is low and PRSENT# is high, what expression was now accessed is that NVMe SSD are hard Disk;When IFDET# and PRSENT# are low, what expression was now accessed is SATA or SAS hard disks.
8. the method according to claim 1 for realizing NVMe SSD lightings by CPLD based on I2C interfaces, its feature It is:The step C include it is following step by step:
Step C1:NVMe SSD hard disks error informations are transmitted to CPLD by BIOS by I2C interfaces;
Step C2:CPLD lights correspondence NVMe SSD wrong indicator lamp.
9. the method according to claim 3 for realizing NVMe SSD lightings by CPLD based on I2C interfaces, its feature It is:The step A include it is following step by step:
Step A1:I2C is resolved into some states;
Step A2:Mainboard BMC determines CPLD device addresses.
10. the method according to claim 9 for realizing NVMe SSD lightings by CPLD based on I2C interfaces, its feature Be, the step A2 include it is following step by step:
Step A21:Mainboard BMC sends address signal;
Step A22:CPLD reads the address signal, corresponding signal is sent if address signal address is identical with itself, if seeking Location Signal Message Address is different from itself, does not process.
CN201710267533.XA 2017-04-21 2017-04-21 A kind of method for realizing NVMe SSD lightings by CPLD based on I2C interfaces Pending CN107145430A (en)

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Application publication date: 20170908