CN103226531B - A kind of dual-port peripheral configuration interface circuit - Google Patents
A kind of dual-port peripheral configuration interface circuit Download PDFInfo
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- CN103226531B CN103226531B CN201310116577.4A CN201310116577A CN103226531B CN 103226531 B CN103226531 B CN 103226531B CN 201310116577 A CN201310116577 A CN 201310116577A CN 103226531 B CN103226531 B CN 103226531B
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Abstract
The invention belongs to embedded system field, disclose a kind of dual-port peripheral configuration interface circuit, externally only have two I/O interface: one is RCK input end of clock mouth, and another is RDA data double-way port; Have with the connectivity port of Parasites Fauna: reading and writing FPDP, read/write address signal port, reading and writing enable signal port.Interface circuit comprises: clock counter, and read-write judges register, address/data shift register, read data shift register, address register, and write enable signal produces register, and reads enable signal generation register.Interface circuit of the present invention has the change of the RCK clock rate that communication protocol is simple, outside port is few, circuit is simple, traffic rate supplies with outside and changes and do not need the advantages such as outside feed system clock.
Description
Technical field
The invention belongs to embedded system field, relate to a kind of dual-port peripheral configuration interface circuit of digital logic.
Background technology
Conventional peripheral configuration interface circuit has a variety of, but in the application of single host concerning Dan Congji, usually more loaded down with trivial details, such as conventional SPI (SerialPeripheralInterface) interface, need 4 ports such as CSN/SCK/MOSI/MISO, MOSI/MISO can not work again simultaneously, causes the waste of resource; And conventional I2C (Inter-IntegratedCircuit) interface, although the port used only has two, SCL/SDA, from speed, only have the speed that this 3 kinds of agreements of 100Kps/400Kbps/3.4Mbps provide.And according to agreement defined, all need to respond ACK after main frame sends ED from machine at every turn, to single host, single slave system, unnecessary, cause the waste on hardware resource; And another kind of conventional UART (UniversalAsynchronousReceiver/Transmitter) interface, although be also that port only has two TxD/RxD, but need both sides first to consult speed, simultaneously both sides all need oneself system clock to complete normal communication process.
Summary of the invention
For the above-mentioned problems in the prior art, when the invention provides a kind of single host, Dan Congji application, outside port is less, agreement is simpler, speed is adjustable, do not need the interface circuit of outside feed system clock.
A kind of dual-port peripheral configuration interface circuit, is characterized in that externally only having two I/O interface: one is RCK input end of clock mouth; Another is RDA port.For with outer equipment exchange information, generally with configuration initiation main frame be connected.Have with the connectivity port of Parasites Fauna: reading and writing FPDP reg_rdD [7:0] and reg_wrD [7:0], read/write address signal port reg_addr [6:0], reading and writing enable signal port reg_rd and reg_wr.Described dual-port peripheral configuration interface circuit comprises: clock counter p_cnt [3:0], read-write judges register p_r_wn, address/data shift register p_d_shift [7:0], read data shift register n_d_shift [7:0], address register p_reg_addr [6:0], write enable signal produces register n_reg_wr, reads enable signal and produces register n_reg_rd.Wherein,
Clock counter p_cnt [3:0], for counting the clock RCK of input, exports the time series pulse signals controlling whole circuit working state.This counter is a tetrad counter, and its input end of clock connects RCK input end of clock mouth, and counting exports and delivers to the front selector switch of p_r_wn, n_reg_rd, n_reg_wr and p_reg_addr [6:0] respectively.Automatically add 1 in the rising edge count value of each clock, from 0 to 15 circulation change, a count cycle is 16 bat RCK clocks, a corresponding read/write operation cycle.
Read-write judges register p_r_wn, for judging the classification (reading or writing) operated.This register is a bit register, and its input end of clock connects RCK input end of clock mouth, and data output end is connected respectively to write enable signal and produces register n_reg_wr and the selector switch read before enable signal generation register n_reg_rd.When p_cnt count down to 0, data on RDA port are sampled, judge this classification operated: if RDA port is high level, this is operating as read operation; If RDA port is low level, this is operating as write operation.
Read enable signal and produce register n_reg_rd, for generation of reading enable signal.This register is a bit register, and its input end of clock connects clock RCK input end of clock mouth, and data input pin connects the output of selector switch above, the selector switch before data output end is connected to read data shift register n_d_shift and read enable port reg_rd.When p_cnt [3:0] count down to 7, the negative edge of RCK trigger this read enable signal produce register n_reg_rd produce width be 1 bat RCK read enable signal.
Write enable signal produces register n_reg_wr, for generation of write enable signal.This register is a bit register, and its input end of clock connects clock RCK input end of clock mouth, and data input pin connects the output of selector switch above, and data output end connects writes enable port reg_wr.When p_cnt [3:0] count down to 15, the negative edge of RCK triggers this register and produces the write enable signal reg_wr that width is 1 bat RCK.
Address register p_reg_addr [6:0], for depositing the address signal of read/write data.This register is 7 bit registers, and its input end of clock connects RCK input end of clock mouth, and data output end directly links the address signal port reg_addr [6:0] to register set operation.When p_cnt [3:0] count down to 7, by low 7 bit data of p_d_shift [7:0] register stored in this address register, produce the address signal of read/write data.
Address/data shift register p_d_shift [7:0], for converting the address of serial or write data signal to parallel data.Described address/data shift register is one and seals in-and 8 bit shift register gone out, shift control termination RCK input end of clock mouth, serial input termination RDA port, 8 bit parallel output data lines connect writes FPDP reg_wrD [7:0], and low 7 position datawire p_d_shift [6:0] are also connected with the selector switch before address register.At the rising edge of each clock period RCK, p_d_shift samples to the data on RDA port and moves to left.When p_cnt [3:0] counts up to 7, this shift register parallel output 7 bit address signal p_d_shift [6:0].When 15th bat negative edge occurs, export 8 and write data to FPDP reg_wrD [7:0].
Read data shift register n_d_shift [7:0], for converting parallel transmission certificate to serial data.This register is one and be incorporated to-goes here and there 8 bit shift register, shift control termination RCK input end of clock mouth, parallel data input termination read data end reg_rdD [7:0], enable control end meets p_r_wn and n_reg_rd respectively, Serial output termination RDA port.When p_r_wn is low (this is operating as write operation), n_d_shift is failure to actuate; When p_r_wn is high (this is operating as read operation), when n_reg_rd is also high, the value (lowest order is 1) of corresponding register will be read from data reading port reg_rdD [7:0].Afterwards at each negative edge of RCK, n_d_shift can perform shift left operation, until 8 bit data all shifted out.
No matter internal circuit operationally, is read operation or write operation, is all for purposes of the invention to carry out data sampling at the rising edge of RCK input end of clock message number to RDA port, and negative edge carries out data variation.
RDA port design is become two-way IO, and object is just to save IO quantity, the action timesharing carried out is completed on same IO time different for read and write these two.
The invention has the beneficial effects as follows: communication protocol is simple; Outside port is few, can save IO resource; Circuit is simple, and chip area is little; Speed is easy to adjust, changes, do not need outside feed system clock with the change of the RCK clock rate of outside supply.
Accompanying drawing explanation
Fig. 1 is the schematic diagram of interface circuit of the present invention;
Fig. 2 is the standard time sequence figure of write operation of the present invention;
Fig. 3 is the standard time sequence figure of read operation of the present invention;
Fig. 4 is the wiring diagram of application example of the present invention.
Embodiment
A kind of dual-port peripheral configuration interface circuit described in the invention, can when connection different peripheral, and all use unified dual-port to communicate to outside, traffic rate is determined by external clock completely.
The specific embodiment of the present invention is provided below in conjunction with accompanying drawing.
Fig. 1 is the electrical schematic diagram of interface circuit of the present invention, primarily of clock counter p_cnt [3:0], read-write judges register p_r_wn, address/data shift register p_d_shift [7:0], read data shift register n_d_shift [7:0], address register p_reg_addr [6:0], write enable signal produces register n_reg_wr, reads enable signal and produces register n_reg_rd composition.
After the interface circuit design of the present embodiment is verified and is terminated, RTL (RegisterTransferLevel) code is carried out comprehensively, form net table, the process devices of company of corresponding CSMC carries out the drafting of domain, under Science and Technology Ltd. of CSMC 350nm technique, finally carry out flow success.
The work schedule of interface circuit when Fig. 2 is write operation.Carrying out the signal on temporary sample RDA port at the rising edge of the 1st clock, judge class of operation (reading or writing), is that low then this communication is for write operation in figure.Counter p_cnt [3:0] carries out from accumulating operation at the rising edge of each clock, adds 1 at every turn.A write cycles is 16 bat clocks, a count cycle of corresponding p_cnt [3:0].Address/data shift register p_d_shift [7:0], at the rising edge sampling RDA port of each clock, carries out shift left operation.It is address information that 2nd ~ 8 of RDA port claps signal, and during the 8th bat, p_d_shift [6:0] exports 7 bit address (0x06) to address register p_reg_addr [6:0], and keeps constant in this communication process; Rear 8 clap the p_d_shift [6:0] (as the high 7) serial data on RDA port being moved to left and formed, signal (as lowest order) during the negative edge clapped with the 15th on RDA port, synthesis write data and deliver to Parasites Fauna write FPDP reg_wrD [7:0].Meanwhile, at the 15th negative edge clapped to the 16th negative edge clapped, exports a write enable signal reg_wr continuing 1 bat and write data enable end, by data stored in Parasites Fauna to Parasites Fauna.So far, a write operation is completed.
The work schedule of interface circuit when Fig. 3 is read operation.Equally, a read cycle is also 16 bat clocks.Level signal on 1st rising edge clock sampling RDA port, judges class of operation (reading or writing), is that then this communicates as read operation height in figure.Read operation is clapped at 2nd ~ 8 of RCK and is obtained address information, and during the 8th bat, 7 bit address (0x06) exported by p_d_shift [6:0] deliver to address register p_d_shift [6:0], and keep constant in this communication process.Meanwhile, during the 7th negative edge clapped to the 8th negative edge clapped, formed wide be 1 bat read enable signal reg_rd, read the data (0x5A) the register of corresponding address (0x06) from the data reading port reg_rdD [7:0] of Parasites Fauna.The negative edge that these data are clapped the 8th, stored in shift register n_d_shift [7:0], at the negative edge of each RCK that 8th ~ 16 clap, this register completes left shift function (lowest order fills out 1).And main frame discharges RDA port at the end of 8 clap, make to export from the RDA port of machine to be reflected to main frame, complete the effect of the output port from machine.The RDA exported follows the most significant digit change of n_d_shift, until complete the process of transmitting of data at the negative edge of each clock.Meanwhile, main frame obtains data by carrying out sampling at the rising edge of each clock to RDA port.Like this, from the 8th negative edge clapped to the 16th negative edge clapped, the whole byte i.e. process of transmitting of 8 bit data is completed.
Provide an application example of the present invention below.Fig. 4 connects structured flowchart when another block simulates the Parasites Fauna of chip to be configured.Using the communication port of interface circuit involved in the present invention as communication in from machine, be connected with a MCU (MicroControlUnit) by the JTAG (JointTestActionGroup) of a computer, setting MSP430 chip is main frame, (one of them GPIO is used as clock port RCK to simulate above-mentioned read/write communication sequential with its GPIO (GeneralPurposeInputOutput), a GPIO is used as bidirectional data port RDA), just can complete the configuration effort between outside and analog chip register.Address space is 0 ~ 127, maximumly reaches 128bytes.
Final chip testing result shows, this interface circuit can work well, can meet the read/write requirement of Parasites Fauna to be configured.
The above, be only preferred embodiment of the present invention, be not intended to limit protection scope of the present invention, and all any amendments done within the spirit and principles in the present invention, equivalent replacement, improvement etc., all should be included within protection scope of the present invention.
Claims (3)
1. a dual-port peripheral configuration interface circuit, is characterized in that, externally only has two I/O interface: one is RCK input end of clock mouth, and another is RDA port; Have with the connectivity port of Parasites Fauna: reading and writing FPDP reg_rdD [7:0] and reg_wrD [7:0], address signal port reg_addr [6:0], reading and writing enable signal port reg_rd and reg_wr; Described dual-port peripheral configuration interface circuit comprises: clock counter p_cnt [3:0], read-write judges register p_r_wn, address/data shift register p_d_shift [7:0], read data shift register n_d_shift [7:0], address register p_reg_addr [6:0], write enable signal produces register n_reg_wr, reads enable signal and produces register n_reg_rd; Wherein,
Described clock counter p_cnt [3:0], for counting the clock RCK of input, exports the time series pulse signals controlling whole circuit working state; Described clock counter is a tetrad counter, and its input end of clock connects RCK input end of clock mouth, and counting exports and delivers to the front selector switch of p_r_wn, n_reg_rd, n_reg_wr and p_reg_addr [6:0] respectively; Automatically add 1 in the rising edge count value of each clock, from 0 to 15 circulation change, a count cycle is 16 bat RCK clocks, a corresponding read/write operation cycle;
Described read-write judges register p_r_wn, for judging the classification operated; Described read-write judges that register is a bit register, and its input end of clock connects RCK input end of clock mouth, and data output end is connected respectively to write enable signal and produces register n_reg_wr and the selector switch read before enable signal generation register n_reg_rd; When p_cnt [3:0] count down to 0, data on RDA port are sampled, judge this classification operated: if RDA port is high level, this is operating as read operation; If RDA port is low level, this is operating as write operation;
Described enable signal of reading produces register n_reg_rd, for generation of reading enable signal; Described read enable signal produce register be a bit register, its input end of clock connects RCK input end of clock mouth, data input pin connects the output of selector switch above, the selector switch before data output end is connected to read data shift register n_d_shift and read enable port reg_rd; When p_cnt [3:0] count down to 7, the negative edge of RCK trigger this read enable signal produce register n_reg_rd produce width be 1 bat RCK clock read enable signal;
Described write enable signal produces register n_reg_wr, for generation of write enable signal; It is a bit register that described write enable signal produces register, and its input end of clock connects RCK input end of clock mouth, and data input pin connects the output of selector switch above, and data output end connects writes enable port reg_wr; When p_cnt [3:0] count down to 15, the negative edge of RCK triggers this register and produces the write enable signal that width is 1 bat RCK clock;
Described address register p_reg_addr [6:0], for depositing the address signal of read/write data; Described address register is 7 bit registers, and its input end of clock connects RCK input end of clock mouth, data output end link address signal port reg_addr [6:0]; When p_cnt [3:0] count down to 7, by low 7 bit data of described address/data shift register p_d_shift [7:0] register stored in this address register, produce the address signal of read/write data;
Described address/data shift register p_d_shift [7:0], for converting the address of serial or write data signal to parallel data; Described address/data shift register is one and seals in-and 8 bit shift register gone out, shift control termination RCK input end of clock mouth, serial input termination RDA port, 8 bit parallel output data lines connect writes FPDP reg_wrD [7:0], and low 7 position datawire p_d_shift [6:0] are also connected with the selector switch before address register; At the rising edge of each clock period RCK, p_d_shift samples to the data on RDA port and moves to left; When p_cnt [3:0] counts up to 7, described address/data shift register parallel output 7 bit address signal p_d_shift [6:0]; When 15th bat negative edge occurs, export 8 and write data to FPDP reg_wrD [7:0];
Read data shift register n_d_shift [7:0], for converting parallel transmission certificate to serial data; This register is one and be incorporated to-goes here and there 8 bit shift register, shift control termination RCK input end of clock mouth, parallel data input termination read data end reg_rdD [7:0], enable control end meets p_r_wn and n_reg_rd respectively, Serial output termination RDA port; When p_r_wn is low, this is operating as write operation, and n_d_shift is failure to actuate; When p_r_wn is high, this is operating as read operation, when n_reg_rd is also high, reads the value of corresponding register from data reading port reg_rdD [7:0]; Afterwards, at each negative edge of RCK, n_d_shift can perform shift left operation, until 8 bit data all shifted out.
2. a kind of dual-port peripheral configuration interface circuit according to claim 1, is characterized in that, no matter is read operation or write operation, is all to carry out data sampling at the rising edge of RCK input end of clock message number to RDA port, and negative edge carries out data variation.
3. a kind of dual-port peripheral configuration interface circuit according to claim 1, it is characterized in that, traffic rate is easy to adjust, changes, and do not need outside feed system clock with the change of the RCK clock rate of outside supply.
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| CN108681513B (en) * | 2018-07-19 | 2023-09-19 | 上海艾为电子技术股份有限公司 | I2C slave address generating device and chip |
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| CN112114875B (en) * | 2020-08-27 | 2023-06-02 | 中国科学院计算技术研究所 | Superconducting parallel register file device |
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| CN1928878A (en) * | 2006-08-17 | 2007-03-14 | 电子科技大学 | Software and hardware synergism communication method |
| CN101127023A (en) * | 2006-08-17 | 2008-02-20 | 四川维肯电子有限公司 | Universal asynchronous serial extended chip of multi-bus interface |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN1928878A (en) * | 2006-08-17 | 2007-03-14 | 电子科技大学 | Software and hardware synergism communication method |
| CN101127023A (en) * | 2006-08-17 | 2008-02-20 | 四川维肯电子有限公司 | Universal asynchronous serial extended chip of multi-bus interface |
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