CN102147780B - Link interface circuit based on serial data transmission mode - Google Patents
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Abstract
The invention discloses a link interface circuit based on a serial data transmission mode. The link interface circuit comprises an interface circuit at the link transmitting end of a processor kernel, an interface circuit at the link receiving end of the processor kernel, an 8-bit data wire and three control wires which are linked between link ports of the link transmitting end and the link receiving end, a link port associated clock generator for generating a link transmission associated clock, a link port direct memory access (DMA) control register for setting a control signal required by link DAM transmission, a link port DMA controller for generating a time sequence required by a link transmission protocol and accessing an address of an internal memory, a link port pingpang buffer register for storing data needed to be subjected to parallel-to-serial conversion transmission and data needed to be subjected to serial-to-parallel conversion receiving during link transmission, and a parallel-to-serial conversion circuit for outputting serial data of eight channels at the same time; and the link port adopts a transmission protocol that the transmitting end transmits parameters to the receiving end so as to realize link transmission of interfaces between two digital signal processors (DSP).
Description
Technical field
The present invention relates to a kind of link interface circuit based on serial data transmission mode, be used for the high speed serialization LVDS data transmission between two DSP.
Background technology
In the system that multiprocessor forms, the mode of carrying out data transmission between the processor generally realizes by all kinds of buses or point-to-point transmission mode.Based on the data transmission architecture of bus because a plurality of processors sharing buses need to be carried out bus arbitration between each processor.Bus arbitration is unfavorable for the in real time application scenario of processing, because after application program is submitted the bus application to, the mandate that must wait bus arbitration mechanism just can take bus afterwards and carry out data transmission, and the time application programs that this section waits is difficult to predict.
Different from bus transmission model, the transmission of point-to-point transmission mode is initiated opportunity fully by application program controlling, therefore the time application programs of transmission can be predicted fully, application program just can be made accurate budget aspect the arrangement of time between exchanges data and data processing like this, meets the application demand of real-time processing.The point-to-point transmission mode is used in real-time processing domain to some extent, for example just used the point-to-point transmission mode in the bullhead shark series processors of ADI company, but the host-host protocol of the said firm regulation, must identical transmission mode, transmission length parameter be set in transmitting terminal and receiving end correspondence, need transmitting terminal and receiving end to do identical setting, this set is appointed in advance, can not change in real time.
Summary of the invention
The object of the present invention is to provide a kind of receiving end parameter configuration, transmitting terminal can simplified to change in real time transformation parameter, make transmission more flexibly based on the link interface circuit of serial data transmission mode.
Its technical scheme is: a kind of link interface circuit based on serial data transmission mode, the interface circuit that comprises processor cores Link transmitting terminal, the interface circuit of processor cores Link receiving end, and be linked at 8 position datawires and three control lines between Link transmitting terminal and the Link receiving end LI(link interface); It is characterized in that:
The interface circuit of described processor cores Link transmitting terminal has:
DMA transmits control register, is used for arranging the control signal that the link port DMA transmission needs;
According to the first control word is set, produce with the road clock with 2,4,6, the 8 different frequency division cycles of road clock generator according to system's major clock;
According to the second control word is set, the transmitting terminal dma controller produces the transmitting terminal on-chip memory and reads the address, and also produces the transfer request signal in the Link port transmission agreement simultaneously;
The transmission ping-pong buffers device of 2*8*32bit is used for the DMA data buffer storage;
8 the parallel parallel-to-serial converters that can support 16bit or 32bit bit wide are for the serial data of exporting simultaneously 8 passages;
The interface circuit of described processor cores Link receiving end has:
DMA receives control register, is used for the control signal that configuration link DMA receives to be needed;
According to the 3rd control word is set, the receiving end dma controller produces receiving end on-chip memory write address, also produces the transmission answer signal in the Link port transmission agreement simultaneously;
The reception ping-pong buffers device of 2*8*32bit is used for the DMA data buffer storage;
8 the parallel serial-parallel conversion circuits that can support 16bit or 32bit bit wide are for the serial data that receives simultaneously 8 passages;
The host-host protocol that described LI(link interface) adopts transmitting terminal to pass a parameter to receiving end is for the link transmission that realizes between two digital signal processors based on the LVDS interface;
Described host-host protocol is: in step 1, the DMA starting impulse determines that by instruction in case the DMA enabling signal is sent in instruction, then execution in step two, produces frequency division with road clock TR_CLK according to default corresponding control word value; Execution in step three simultaneously, the transmitting terminal dma controller checks whether Link mouth receiving end is ready to, and Link mouth receiving end DMA is at electrification reset or to keep the transmission responsion signal Ack after the DMA end of transmission (EOT) last time be high level, and expression stops DMA and receives work; After correct configuration Link mouth receiving end DMA reception control register juxtaposition reception transmission enable bit is effective, the transmission responsion signal Ack drags down, expression is ready for DMA and is received work, make a start and send continuously the DMA transmission request signal that yard shape is " 110011 " by transfer request signal IRQ, and execution in step four subsequently, send continuously two 32bit control words to receiving end, this moment, IRQ kept low level; Receiving end detects the laggard line control word of this IRQ code shape signal and receives preparation, and 2 32bit control word step-by-steps difference assignment will receiving are subsequently drawn high ack signal afterwards expression and can be received normal data to the corresponding control bit of DMA reception control register; In step 5, transmitting terminal is drawn high irq signal after sending control word, simultaneously the source start address being delivered to the read bus arbitration circuit arbitrates, in case obtain bus control right, execution in step six, the 32bit data are written in the corresponding transmission table tennis buffer memory in the storer that this address is accessed, then add step value with start address and calculate the address value that makes new advances, and repetition aforesaid operations, until be that 8 transmission table tennis buffer memory fills up and provide buffer memory full scale will with the degree of depth, switch to subsequently and send pang buffer memory, continue calculated address until will send 8 registers of pang buffer memory and fill up; In step 7, when transmitting terminal table tennis buffer memory is write full and is exchanged ripple signal sensing pang buffer memory, irq signal is dragged down, 8 32bit data begin to carry out parallel-serial conversion and transmission work in the transmission table tennis buffer memory, receiving end execution in step eight, begin to receive serial data and go here and there and conversion work, and the 32bit parallel data after will change deposits in and receives ping in the buffer memory;
Start parallel-serial conversion in above-mentioned seven steps and reception work and string and the conversion in transmission work and above-mentioned eight steps at the negative edge of irq signal, when a parallel-serial conversion end-of-job, provide an end of transmission (EOT) sign, whether detect simultaneously transmitting terminal buffer memory full scale will and ack signal all is high level, in this way, represent that then 8 32bit data of next group have been ready to and the buffer memory of receiving end also is ready to, can continue receive data, this moment, the buffer memory exchange ripple signal of transmitting terminal overturn, irq signal is kept low level, continues parallel-serial conversion and data transmission work; If this moment, transmitting terminal buffer memory full scale will or ack signal had one to be low level, then stop data parallel-serial conversion and transmission work, and irq signal drawn high, transmitting terminal buffer memory exchange ripple signal remains unchanged, until transmitting terminal buffer memory full scale will and ack signal are when all being ' 1 ', irq signal is dragged down again the buffer memory exchange ripple signal of the transmitting terminal that overturns simultaneously; When upset occurs in transmitting terminal buffer memory exchange ripple signal, the zero clearing of transmitting terminal buffer memory full scale will can be continued to read the address counting simultaneously, the negative edge of irq signal then can start parallel-serial conversion and the transmission work of next data; Repetitive operation is until the address counting step reaches the DMA transmission length that the programmer sets, and the Link mouth sends end-of-job and provides the transmission end mark.
Its technique effect is: the present invention adopts point-to-point data transfer mode, and in host-host protocol, adopt by the transmitting terminal of data and initiate transmission, and transmission mode, transmission length parameter send receiving end to by transmitting terminal, receiving end is the control register that automatically disposes receiving end after receiving parameter, and the application program of receiving end is simplified aspect parameter configuration; Simultaneously, during each transmission beginning, transmitting terminal sends transmission mode, transmission length information to receiving end, transmitting terminal just can be each different pattern and length parameters of transmission configuration like this, reach the effect of real-time change transmission mode and transmission length, so that data transmission is more flexible, thereby effectively solved the data transmission problems of real-time processing application scenario, for the inside of dsp processor or outside data transmission provide one fast, communication mechanism independently, this interface circuit also can use the I/O equipment connection of same protocol to communicate by letter with other.
Description of drawings
Fig. 1 is structured flowchart of the present invention;
Fig. 2 is the interface circuit structure figure of processor cores Link transmitting terminal;
Fig. 3 is the parallel-to-serial converter structural drawing of transmitting terminal;
Fig. 4 is the interface circuit structure figure of processor cores Link receiving end;
Fig. 5 is the serial-parallel conversion circuit structural drawing of receiving end;
Fig. 6 is the TR_CLK signal, the timing waveform between irq signal and the ack signal.
Embodiment
As shown in Figure 1, link interface circuit based on serial data transmission mode, the interface circuit that comprises processor cores Link transmitting terminal, the interface circuit of processor cores Link receiving end, and be linked at 8 position datawire LINK_DATA[7:0 and three control line TR_CLK between Link transmitting terminal and the Link receiving end LI(link interface), IRQ, ACK.TR_CLK wherein, IRQ and LINK_DATA[7:0] be to export to Link mouth receiving end by Link mouth transmitting terminal, ack signal then is to feed back to Link mouth transmitting terminal by Link mouth receiving end.
The interface circuit (see figure 2) of processor cores Link transmitting terminal has: DMA transmits control register, with the road clock generator, and dma controller, the table tennis data buffer storage of one group of 2*8*32bit and 8 parallel-to-serial converters, carry-out bit 8*1bit serial data.Each dma controller need to carry out correct configuration to corresponding DMA control register according to the programmer could log-on data transmission work.Data transmission length to need to determine the data volume transmitted in a data transmission procedure.
The DMA data buffer storage is the 16*32bit data register of one group of ping-pong structure, when one group of data register carries out data transmission, another group data register receives the data that send from the storer read bus, when DTD, check whether the data register that another winding is received receives, when the ready while of data register, check whether Link mouth receiving end is ready to, in case all ready, then the table tennis exchange occurs in the internal data buffer memory, and next group data transmission just begins to carry out.
In step 1, the DMA starting impulse determines that by instruction in case the DMA enabling signal is sent in instruction, then execution in step two, produces frequency division with road clock TR_CLK according to default corresponding control word value.Execution in step three simultaneously, DMA transmitting terminal controller checks whether Link mouth receiving end is ready to, and Link mouth receiving end DMA is at electrification reset or to keep receiving response signal ACK after the DMA end of transmission (EOT) last time be high level, and expression stops DMA and receives work.After correct configuration Link mouth receiving end DMA control register juxtaposition reception transmission enable bit is effective, receiving response signal ACK drags down, expression is ready for DMA and is received work, make a start and send continuously the DMA transmission request signal that yard shape is " 110011 " by transfer request signal IRQ, and execution in step four subsequently, send continuously two 32bit control words to receiving end.This moment, IRQ kept low level.Receiving end detects the laggard line control word of this IRQ code shape signal and receives preparation, and 2 32bit control word step-by-steps difference assignment will receiving are subsequently drawn high ack signal afterwards expression and can be received normal data to receiving the corresponding control bit of control register.In step 5, transmitting terminal is drawn high irq signal after sending control word, simultaneously the source start address being delivered to the read bus arbitration circuit arbitrates, in case obtain bus control right, execution in step six, 32bit data (Ram_data) are written in the corresponding transmission table tennis buffer memory in the storer that this address is accessed, then add step value with start address and calculate the address value (raddr) that makes new advances, and repetition aforesaid operations, until be that 8 transmission table tennis buffer memory fills up and provide buffer memory full scale will (reg_full) with the degree of depth, switch to subsequently and send pang buffer memory, continue calculated address until will send 8 registers of pang buffer memory and fill up.In step 7, when transmitting terminal table tennis buffer memory is write full and is exchanged ripple signal (Tr_reg_switch) sensing pang buffer memory, irq signal is dragged down, 8 32bit data (corresponding 8 serial LVDS passages) begin to carry out parallel-serial conversion and transmission work in the transmission table tennis buffer memory, receiving end execution in step eight, begin to receive serial data and go here and there and conversion work, and the 32bit parallel data after will change deposits in and receives ping in the buffer memory.All also goes here and there---and string and conversion, send and receive work are all synchronous in strict accordance with the negative edge of irq signal.When a parallel-serial conversion end-of-job, provide an end of transmission (EOT) sign, whether detect simultaneously transmitting terminal buffer memory full scale will and ack signal all is high level, in this way, represent that then 8 32bit data of next group are ready to (pang buffer memory is write full) and the buffer memory of receiving end also is ready to (pang buffer memory is for empty), can continue receive data, this moment, the buffer memory exchange ripple signal of transmitting terminal overturn, irq signal is kept low level, continues parallel-serial conversion and data transmission work.If this moment, transmitting terminal buffer memory full scale will or ack signal had one then to stop data parallel-serial conversion and transmission work, and irq signal is drawn high for low level, transmitting terminal buffer memory exchange ripple signal remains unchanged; Until transmitting terminal buffer memory full scale will and ack signal when all being ' 1 ', drag down irq signal the buffer memory exchange ripple signal of the transmitting terminal that overturns simultaneously again.When upset occurs in transmitting terminal buffer memory exchange ripple signal, transmitting terminal buffer memory full scale will zero clearing (dragging down) can be continued to read the address counting simultaneously, the negative edge of irq signal then can start parallel-serial conversion and the transmission work of next data.Repetitive operation is until the address counting step reaches the DMA transmission length that the programmer sets, and the Link mouth sends end-of-job and provides the transmission end mark.
The serial data transmission word is wide to be 32bit, these data are all transmitted according to serial data mode, for whether check data exists mistake in the middle of transmission course, each data can increase by a bit parity check code, namely increases by a bit parity check position on the basis of original data bits.If the result of data parity check is ' 1 ' after receiving end string and the conversion, show that then mistake appears in data in transmission course.
The working method of parallel-to-serial converter (see figure 3) is: at first the 32bit data (or not enough 32bit) with data buffer storage output resolve into two 16bit data (or not enough 16bit) by parity bit, two data after the decomposition begin parallel-serial conversion work simultaneously, the first low level rear high-lying of conversion output, utilizing serial clock TR_CLK to carry out parity bit data output at the conversion output terminal selects, when being high level, TR_CLK selects even number section serial output data, select odd number section output data when low, so just be equal to the rising edge and the negative edge that utilize TR_CLK and all carry out data parallel-serial conversion and output services.As being 250MHz with the road clock, then the serial ports transfer rate can reach 500MHz.
The interface circuit (see figure 4) of processor cores Link receiving end has: DMA receives control register, receiving end dma controller, the table tennis data buffer storage of one group of 2*8*32bit and 8 serial-parallel conversion circuits.Receiving dma controller needs the programmer that corresponding DMA control register is carried out the correct correctly log-on data reception work that arranges.
The DRP data reception process of Link receiving end is: 8 tunnel serial datas that receive are gone here and there first and are converted into 8 road 32bit parallel datas, data after string and the conversion are deposited in the ping-pong buffer of a 2*8*32bit, then the serial received port starts dma controller, and be written in the corresponding storer data cached according to the on-chip memory sequence of addresses that DMA calculates, judge whether simultaneously to continue to respond the transmission request of transmit port and send the ACK answer signal.Concrete sequential relationship is described below: it is low level that Link mouth receiving end DMA keeps receiving response signal ACK after the programmer correctly arranges control register, expression is ready to DMA and receives work, if this moment, transmitting terminal started the DMA transmission, to receive yard shape and be the DMA transmission request signal IRQ of " 110011 ", receiving end detects the laggard line control word of this irq signal and receives preparation, and 2 32bit control word assignment will receiving subsequently are to the receiving end control register.Transmitting terminal is drawn high irq signal after sending control word, in the time of transmitting terminal table tennis buffer memory ready (writing full) the formal transmission of beginning data, irq signal can be dragged down, 8 32bit data (corresponding 8 serial LVDS passages) begin to carry out parallel-serial conversion and transmission work in the table tennis buffer memory of transmitting terminal, receiving end enters step 8 at this moment, begin to receive serial data and go here and there and conversion work, the 32bit parallel data after will change simultaneously deposits receiving end in ping in the buffer memory.All also goes here and there---and string and conversion, send and receive work are all synchronous in strict accordance with the negative edge of irq signal.After receiving end table tennis buffer memory is finished and deposited in to a data receiver, upset occurs and points to receiving end pang buffer memory in receiving end buffer memory exchange ripple signal (Rx_reg_switch), sense data from write full table tennis buffer memory simultaneously, carry out the step 9 operation, this moment, the receiving end dma controller began to produce data-carrier store write address (waddr) in the sheet, the address is delivered to the write bus arbitration circuit and is arbitrated, in case obtain bus control right, implementation step ten, the 32bi data that the access of postponing is gone out are written in the on-chip memory appropriate address space of accessing this address, then add step value with start address and calculate the address value that makes new advances, and repetition aforesaid operations, until with the degree of depth be 8 reception table tennis cache read empty and all be written to on-chip memory after, provide and receive the empty sign of buffer memory (reg_empty) for high.In step 11, once go here and there and change when receiving end-of-job, providing a reception end mark is ' 1 ', detects simultaneously whether the empty sign of receiving end buffer memory is high level, in this way, then expression reception pang buffer memory is ready to, can continue receive data, ack signal is kept high level, the buffer memory exchange ripple signal generation once inside out of receiving end, begin the reception work of next data, simultaneously with the zero clearing of the empty sign of receiving end buffer memory.If the empty marking signal of receiving end buffer memory this moment is low level, represent the data cached sky of not yet reading of another group, can not continue receive data, drag down ack signal this moment, and it is constant to keep receiving end buffer memory exchange ripple level, and transmitting terminal stops data transmission work, until receiving end buffer memory sky is masked as when high, ack signal is set high, receiving end buffer memory exchange ripple signal overturns, and starts string and conversion and the reception work of next group data again.Repetitive operation then stops data receiver work until transmitting terminal request signal IRQ is permanent for height, then works as DMA write address counting step and reaches the DMA transmission length that prior control word sets, and Link mouth reception work finishes fully, provides the reception end mark.
Each Link receiving port is made of 8 LVDS data channel, and with serial mode input 1bit data, 8 passages are receiving the 8bit data in the beat to these 8 passages at the same time simultaneously respectively.Receive the work that will go here and there and change after the serial data, each passage has a serial-parallel conversion circuit (see figure 5), and the parallel data that the serial data that is about to a string 1bit is transformed into a 32bit deposits buffer memory in.Data transfer mode is first low level rear high-lying.String and switching rate are by determining with road clock TR_CLK that transmitting terminal provides.The serial data that receives is being done string and during conversion work, and parity checking in the control word that need to send in advance according to transmitting terminal, data word be wide, the information such as signed number is determined to operate accordingly.Its working method is: at first the 1bit serial data of input is utilized respectively the rising edge of clock TR_CLK to squeeze in the different moment with negative edge in (string and conversion) two 16bit registers, be respectively the required parity bit that obtains data.(rising edge is adopted odd data and is done string and conversion, and negative edge is adopted even data and done string and conversion.) according to the transmission of data word wide be set in receive once complete serial data after, the parity bit parallel data is merged into a complete 32bit parallel data, carry out simultaneously parity checking.Afterwards data are deposited in the ping-pong buffer.
TR_CLK signal in the present embodiment, the sequential relationship between irq signal and the ack signal is seen Fig. 6.
Claims (3)
1. link interface circuit based on serial data transmission mode, the interface circuit that comprises processor cores Link transmitting terminal, the interface circuit of processor cores Link receiving end, and be linked at 8 position datawires and three control lines between Link transmitting terminal and the Link receiving end LI(link interface); It is characterized in that:
The interface circuit of described processor cores Link transmitting terminal has:
DMA transmits control register, is used for arranging the control signal that the link port DMA transmission needs;
According to the first control word is set, produce with the road clock with 2,4,6, the 8 different frequency division cycles of road clock generator according to system's major clock;
According to the second control word is set, the transmitting terminal dma controller produces the transmitting terminal on-chip memory and reads the address, and also produces the transfer request signal in the Link port transmission agreement simultaneously;
The transmission ping-pong buffers device of 2*8*32bit is used for the DMA data buffer storage;
8 the parallel parallel-to-serial converters that can support 16bit or 32bit bit wide are for the serial data of exporting simultaneously 8 passages;
The interface circuit of described processor cores Link receiving end has:
DMA receives control register, is used for the control signal that configuration link DMA receives to be needed;
According to the 3rd control word is set, the receiving end dma controller produces receiving end on-chip memory write address, also produces the transmission answer signal in the Link port transmission agreement simultaneously;
The reception ping-pong buffers device of 2*8*32bit is used for the DMA data buffer storage;
8 the parallel serial-parallel conversion circuits that can support 16bit or 32bit bit wide are for the serial data that receives simultaneously 8 passages;
The host-host protocol that described LI(link interface) adopts transmitting terminal to pass a parameter to receiving end is for the link transmission that realizes between two digital signal processors based on the LVDS interface;
Described host-host protocol is: in step 1, the DMA starting impulse determines that by instruction in case the DMA enabling signal is sent in instruction, then execution in step two, produces frequency division with road clock TR_CLK according to default corresponding control word value; Execution in step three simultaneously, the transmitting terminal dma controller checks whether Link mouth receiving end is ready to, and Link mouth receiving end DMA is at electrification reset or to keep the transmission responsion signal Ack after the DMA end of transmission (EOT) last time be high level, and expression stops DMA and receives work; After correct configuration Link mouth receiving end DMA reception control register juxtaposition reception transmission enable bit is effective, the transmission responsion signal Ack drags down, expression is ready for DMA and is received work, make a start and send continuously the DMA transmission request signal that yard shape is " 110011 " by transfer request signal IRQ, and execution in step four subsequently, send continuously two 32bit control words to receiving end, this moment, IRQ kept low level; Receiving end detects the laggard line control word of this IRQ code shape signal and receives preparation, and 2 32bit control word step-by-steps difference assignment will receiving are subsequently drawn high ack signal afterwards expression and can be received normal data to the corresponding control bit of DMA reception control register; In step 5, transmitting terminal is drawn high irq signal after sending control word, simultaneously the source start address being delivered to the read bus arbitration circuit arbitrates, in case obtain bus control right, execution in step six, the 32bit data are written in the corresponding transmission table tennis buffer memory in the storer that this address is accessed, then add step value with start address and calculate the address value that makes new advances, and repetition aforesaid operations, until be that 8 transmission table tennis buffer memory fills up and provide buffer memory full scale will with the degree of depth, switch to subsequently and send pang buffer memory, continue calculated address until will send 8 registers of pang buffer memory and fill up; In step 7, when transmitting terminal table tennis buffer memory is write full and is exchanged ripple signal sensing pang buffer memory, irq signal is dragged down, 8 32bit data begin to carry out parallel-serial conversion and transmission work in the transmission table tennis buffer memory, receiving end execution in step eight, begin to receive serial data and go here and there and conversion work, and the 32bit parallel data after will change deposits in and receives ping in the buffer memory;
Start parallel-serial conversion in above-mentioned seven steps and reception work and string and the conversion in transmission work and above-mentioned eight steps at the negative edge of irq signal, when a parallel-serial conversion end-of-job, provide an end of transmission (EOT) sign, whether detect simultaneously transmitting terminal buffer memory full scale will and ack signal all is high level, in this way, represent that then 8 32bit data of next group have been ready to and the buffer memory of receiving end also is ready to, can continue receive data, this moment, the buffer memory exchange ripple signal of transmitting terminal overturn, irq signal is kept low level, continues parallel-serial conversion and data transmission work; If this moment, transmitting terminal buffer memory full scale will or ack signal had one to be low level, then stop data parallel-serial conversion and transmission work, and irq signal drawn high, transmitting terminal buffer memory exchange ripple signal remains unchanged, until transmitting terminal buffer memory full scale will and ack signal are when all being ' 1 ', irq signal is dragged down again the buffer memory exchange ripple signal of the transmitting terminal that overturns simultaneously; When upset occurs in transmitting terminal buffer memory exchange ripple signal, the zero clearing of transmitting terminal buffer memory full scale will can be continued to read the address counting simultaneously, the negative edge of irq signal then can start parallel-serial conversion and the transmission work of next data; Repetitive operation is until the address counting step reaches the DMA transmission length that the programmer sets, and the Link mouth sends end-of-job and provides the transmission end mark.
2. a kind of link interface circuit based on serial data transmission mode according to claim 1 is characterized in that: described LI(link interface) is bidirectional interface independently, can be from the other side's receive data when sending.
3. a kind of link interface circuit based on serial data transmission mode according to claim 1, it is characterized in that: described LI(link interface) is all carried out data transmission with rising edge and the negative edge of road clock.
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| CN103034610B (en) * | 2011-10-09 | 2018-09-04 | 南京中兴软件有限责任公司 | The method and device of AXI bus signals transmitting and receivings is carried out in seperated intermodule |
| CN107741920B (en) * | 2017-10-13 | 2020-09-29 | 肇庆市立泰电子产品有限公司 | Simplified data transmission method for needle selector |
| CN109062847B (en) * | 2018-07-31 | 2023-08-25 | 深圳职业技术学院 | System on chip, IP core for RS485 serial port communication and control method thereof |
| CN111200581B (en) * | 2018-11-19 | 2022-08-16 | 北京华航无线电测量研究所 | Data receiving and transmitting module based on LVDS bus |
| CN111475447B (en) * | 2019-01-24 | 2021-10-22 | 广州彩熠灯光股份有限公司 | High-speed serial transmission device based on LVDS and data transmission method |
| CN110442543B (en) * | 2019-08-09 | 2023-09-08 | 瓴盛科技有限公司 | Communication device and communication method |
| CN113094310A (en) * | 2019-12-23 | 2021-07-09 | 华为技术有限公司 | Memory manager, processor memory subsystem, processor and electronic equipment |
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