CN110765058A - Method, system, equipment and medium for realizing SPI slave function by GPIO - Google Patents
Method, system, equipment and medium for realizing SPI slave function by GPIO Download PDFInfo
- Publication number
- CN110765058A CN110765058A CN201910866165.XA CN201910866165A CN110765058A CN 110765058 A CN110765058 A CN 110765058A CN 201910866165 A CN201910866165 A CN 201910866165A CN 110765058 A CN110765058 A CN 110765058A
- Authority
- CN
- China
- Prior art keywords
- cpu
- slave
- mcu
- spi
- signal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000000034 method Methods 0.000 title claims abstract description 55
- 230000006870 function Effects 0.000 claims description 58
- 238000004590 computer program Methods 0.000 claims description 14
- 230000004044 response Effects 0.000 claims description 13
- 230000009471 action Effects 0.000 claims description 7
- 230000008901 benefit Effects 0.000 description 8
- 230000008569 process Effects 0.000 description 8
- 238000010586 diagram Methods 0.000 description 6
- 238000012545 processing Methods 0.000 description 5
- 230000002093 peripheral effect Effects 0.000 description 4
- 230000005540 biological transmission Effects 0.000 description 3
- 238000004891 communication Methods 0.000 description 3
- 238000012905 input function Methods 0.000 description 3
- 230000007246 mechanism Effects 0.000 description 2
- 230000001360 synchronised effect Effects 0.000 description 2
- 230000001934 delay Effects 0.000 description 1
- 230000006872 improvement Effects 0.000 description 1
- 239000004973 liquid crystal related substance Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 230000000630 rising effect Effects 0.000 description 1
- 230000001960 triggered effect Effects 0.000 description 1
Images
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
- G06F13/4282—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus
- G06F13/4291—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus using a clocked protocol
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Information Transfer Systems (AREA)
Abstract
The application relates to a method, a system, equipment and a medium for realizing the function of an SPI slave machine by GPIO, wherein the method comprises the following steps: when the MCU changes the clock signal into effective, the MCU sends an interrupt to the CPU through the GPIO3 pin, and the CPU enters an interrupt processing program; when the CPU enters an interrupt processing program and judges that the slave equipment enabling signal is effective, the MCU sends a bit data to the CPU; the CPU reads a main output slave input signal of the GPIO1 pin in an interrupt program, and reads data from the MCU; when an interrupted clock signal is generated, the CPU reads bit data sent by the MCU and sends responded bit data to the MCU; and the CPU reads the bit data of each byte, and the read bit data is combined into one byte. The method can realize the function of the SPI slave machine on the CPU which does not support the function of the SPI slave machine, has simple structure and easy realization and has low cost.
Description
Technical Field
The application relates to the field of embedded driving, in particular to a method and a system for realizing SPI slave function based on GPIO of a CPU, computer equipment and a readable storage medium.
Background
The SPI (serial Peripheral interface) serial Peripheral interface is a high-speed, full-duplex and synchronous communication bus, only four wires are occupied on the pins of a chip, the pins of the chip are saved, meanwhile, the space is saved on the layout of a PCB, and convenience is provided.
In the prior art, most main control CPUs can only have the SPI host function, and a very small number of CPUs support the SPI slave function, but the main control CPUs are all realized by hardware and have poor expansibility. If the SPI slave function is realized on a CPU which does not support the SPI slave function, the operation is very troublesome and the cost is high.
Therefore, the prior art is in need of improvement.
Disclosure of Invention
The invention aims to solve the technical problems that a method and a system for realizing the function of an SPI slave machine based on GPIO of a CPU, computer equipment and a readable storage medium are provided, and aims to solve the problems that the prior art is very troublesome and high in cost when the function of the SPI slave machine is realized on the CPU which does not support the function of the SPI slave machine.
A method for realizing SPI slave function based on GPIO of CPU includes:
the CPU is respectively processed by: a GPIO1 pin connected with a master output slave input signal, a GPIO2 pin connected with a master input slave output signal, a GPIO3 pin connected with a clock signal and a GPIO4 pin connected with a slave device enabling signal are connected with the MCU, the CPU is used as a slave in the SPI protocol, and the MCU is used as a master in the SPI protocol;
the GPIO3 pin of the selected clock signal supports sending interrupt to the CPU, and the interrupt type is set as edge trigger;
when the MCU changes the clock signal into effective, the MCU sends an interrupt to the CPU through the GPIO3 pin, and the CPU enters an interrupt processing program;
when the CPU enters an interrupt processing program and judges that the slave equipment enabling signal is effective, the MCU sends a bit data to the CPU;
the CPU reads a main output slave input signal of the GPIO1 pin in an interrupt program, and reads data from the MCU; meanwhile, data are sent to the MCU through a master input slave output signal of the GPIO2 pin;
when an interrupted clock signal is generated, the CPU reads bit data sent by the MCU and sends responded bit data to the MCU;
and the CPU reads the bit data of each byte, and the read bit data is combined into one byte.
The method for realizing the function of the SPI slave machine by the GPIO based on the CPU comprises the steps that relative to the CPU, the GPIO1 is used as a main output slave input signal MOSI and is an input signal; GPIO2 is a master-input slave-output MISO, which is an output signal; GPIO3 is used as clock signal SCLK and is an input signal; the GPIO4 is an input signal as the slave enable signal CS.
The method for realizing the function of the SPI slave machine by the GPIO based on the CPU comprises the following steps that when the MCU changes a clock signal into valid:
when the GPIO3 is pulled up to a high level from a low level, an interrupt request is immediately sent to the CPU; the CPU responds to the interrupt request.
The method for realizing the function of the SPI slave machine based on the GPIO of the CPU comprises the following steps that when the CPU enters an interrupt processing program and judges that an enabling signal of the slave equipment is valid, an MCU sends bit data to the CPU:
the CPU enters an interrupt processing program;
when the CPU enters an interrupt processing program, judging whether the slave equipment enabling signal is effective or not;
when the slave enable signal is valid, the SPI period starts, the GPIO1MOSI is read, and the MCU sends one bit of data to the CPU.
The method for realizing the function of the SPI slave machine by the GPIO based on the CPU, wherein the step of judging whether the enabling signal of the slave machine is effective further comprises the following steps:
if the slave enable signal CS is high, the SPI cycle is indicated and ended.
The method for realizing the function of the SPI slave machine by the GPIO based on the CPU comprises the following steps that when an interrupted clock signal is generated, the CPU reads bit data sent by the MCU and sends responded bit data to the MCU:
according to the actual action of the current SPI command, a main device data input signal through a GPIO2 pin is written into one bit in the response byte, and the main device data input signal is written according to the sequence of the highest bit of the byte sent first;
each CPU is interrupted, receives a bit, and sends data of the bit to the MCU until the slave equipment enabling signal is in a high level, and the SPI time sequence is ended; and sets the length of the receive and transmit bits to 0 until the next SPI cycle begins.
A system for realizing SPI slave function based on GPIO of CPU, wherein the system comprises: the MCU is used as a host in the SPI protocol, and the CPU is used as a slave in the SPI protocol;
the CPU as a host machine is respectively controlled by: a GPIO1 pin connected to an MOSI (master output slave input signal), a GPIO2 pin connected to an MISO (master input slave output signal), a GPIO3 pin connected to an SCLK (clock signal), and a GPIO4 pin connected to a CS (slave enable signal) are connected to an MCU as a host;
the GPIO3 pin of the selected clock signal supports sending interrupt to the CPU, and the interrupt type is set as edge trigger;
when the MCU changes the clock signal into effective, the MCU sends an interrupt to the CPU through the GPIO3 pin, and the CPU enters an interrupt processing program;
when the CPU enters an interrupt processing program and judges that the slave equipment enabling signal is effective, the MCU sends a bit data to the CPU;
the CPU reads a main output slave input signal of the GPIO1 pin in an interrupt program, and reads data from the MCU; meanwhile, data are sent to the MCU through a master input slave output signal of the GPIO2 pin;
when an interrupted clock signal is generated, the CPU reads bit data sent by the MCU and sends responded bit data to the MCU;
and the CPU reads the bit data of each byte, and the read bit data is combined into one byte.
The GPIO based on CPU realizes SPI from quick-witted functional system, wherein, the system still includes:
a configuration unit configured to use the GPIO1 as a master output slave input signal MOSI, which is an input signal; GPIO2 is a master-input slave-output MISO, which is an output signal; GPIO3 is used as clock signal SCLK and is an input signal; the GPIO4 is an input signal as the slave device enable signal CS;
the judgment reading unit is used for controlling the CPU to enter an interrupt processing program; when the CPU enters an interrupt processing program, judging whether the slave equipment enabling signal is effective or not; when the slave equipment enabling signal is valid, the SPI cycle starts, the GPIO1MOSI is read, and the MCU sends a bit data to the CPU;
the sending control unit is used for writing a bit in the response byte through a main equipment data input signal of the GPIO2 pin according to the actual action of the current SPI command and writing according to the sequence of the highest bit of the byte sent first;
the response control unit is used for receiving one bit and sending data of one bit to the MCU when each CPU is interrupted, and ending the SPI time sequence until the slave equipment enabling signal is in a high level; and sets the length of the receive and transmit bits to 0 until the next SPI cycle begins.
A computer device comprising a memory and a processor, the memory storing a computer program, wherein the processor comprises: a CPU as a slave and an MCU as a master; the processor, when executing the computer program, performs the steps of any of the methods.
A computer-readable storage medium, on which a computer program is stored, wherein the computer program realizes the steps of any of the methods when executed by a processor.
Compared with the prior art, the embodiment of the invention has the following advantages:
according to the method provided by the embodiment of the invention, firstly, a CPU respectively passes through: a GPIO1 pin connected with a master output slave input signal, a GPIO2 pin connected with a master input slave output signal, a GPIO3 pin connected with a clock signal and a GPIO4 pin connected with a slave device enabling signal are connected with the MCU, the CPU is used as a slave in the SPI protocol, and the MCU is used as a master in the SPI protocol; the GPIO3 pin of the selected clock signal supports sending interrupt to the CPU, and the interrupt type is set as edge trigger; when the MCU changes the clock signal into effective, the MCU sends an interrupt to the CPU through the GPIO3 pin, and the CPU enters an interrupt processing program; when the CPU enters an interrupt processing program and judges that the slave equipment enabling signal is effective, the MCU sends a bit data to the CPU; the CPU reads a main output slave input signal of the GPIO1 pin in an interrupt program, and reads data from the MCU; meanwhile, data are sent to the MCU through a master input slave output signal of the GPIO2 pin; when an interrupted clock signal is generated, the CPU reads bit data sent by the MCU and sends responded bit data to the MCU; and the CPU reads the bit data of each byte, and the read bit data is combined into one byte. The method can realize the function of the SPI slave machine on the CPU which does not support the function of the SPI slave machine, has simple structure and easy realization and has low cost.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only some embodiments described in the present invention, and for those skilled in the art, other drawings can be obtained according to the drawings without creative efforts.
Fig. 1 is a schematic block diagram of a system for implementing an SPI slave function based on a GPIO of a CPU in an embodiment of the present invention.
FIG. 2 is a schematic diagram of an SPI timing waveform in an embodiment of the present invention.
Fig. 3 is a schematic configuration flow diagram of a method for implementing an SPI slave function based on a GPIO of a CPU in an embodiment of the present invention.
Fig. 4 is a schematic diagram of an initialization process of a method for implementing an SPI slave function based on a GPIO of a CPU in an embodiment of the present invention.
Fig. 5 is a flowchart of an embodiment of a method for implementing an SPI slave function based on a GPIO of a CPU in an embodiment of the present invention.
Fig. 6 is an internal structural diagram of a computer device in an embodiment of the present invention.
Detailed Description
In order to make the technical solutions of the present invention better understood, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
Various non-limiting embodiments of the present invention are described in detail below with reference to the accompanying drawings.
The inventor finds that most of the existing main control CPUs can only have the function of the SPI master, and if the SPI slave is to be implemented on a CPU that does not support the function of the SPI slave, the implementation is very troublesome and the cost is high.
In order to solve the above problems, in the embodiment of the present invention, a system for implementing an SPI slave function based on a GPIO of a CPU is provided; as shown in fig. 1, the system for implementing an SPI slave function by a GPIO based on a CPU of this embodiment includes:
a CPU as a slave, and an MCU as a master; in the embodiment of the invention, the CPU is used as a slave in the SPI protocol, and the MCU is used as a host in the SPI protocol;
as shown in fig. 1, the CPU as a host is configured by: a GPIO1 pin connected to MOSI (master output slave input signal), a GPIO2 pin connected to MISO (master input slave output signal), a GPIO3 pin connected to SCLK (clock signal), and a GPIO4 pin connected to CS (slave enable signal) are connected to the MCU as a host.
Wherein MOSI is-Master Output Slave Input, and the Master device data is Output and the Slave device data is Input;
MISO is-Master Input Slave Output, and the data of the Master device is Input and the data of the Slave device is Output;
SCLK is a Serial Clock, the Clock signal, generated by the master device;
CS is-Chip Select, and the slave enables signals and is controlled by the master.
The SPI is an abbreviation of the english Serial Peripheral Interface and is a Serial Peripheral Interface. The SPI is a high-speed, full-duplex and synchronous communication bus, only four wires are occupied on pins of a chip, the pins of the chip are saved, and meanwhile, the space is saved on the layout of a PCB.
The communication principle of the SPI is that the SPI works in a master-slave manner, and this mode usually has a master device and one or more slave devices, and at least 4 lines are required, or 3 lines are required when unidirectional transmission is performed. Also common to all SPI-based devices are MISO (master data in), MOSI (master data out), SCLK (clock), CS (slave enable signal).
In the embodiment of the present invention, when implementing the SPI slave function system based on the GPIO of the CPU, referring to fig. 1 and 2, the GPIO3 pin of the selected SCLK can support sending an interrupt to the CPU, and the interrupt type may be set as edge trigger. Once the MCU has pulled SCLK (clock signal) high to active, the GPIO3 of the MCU issues an interrupt to the CPU, which enters an interrupt handler. Reading GPIO1MOSI in an interrupt program (standing in a slave CPU) to indicate that the slave MCU reads data; and simultaneously writing data to the GPIO2MISO, which means transmitting data to the MCU. Each time SCLK is interrupted, the CPU may read one bit and send one bit.
Based on the system for realizing the function of the SPI slave machine by the GPIO based on the CPU in the embodiment, the embodiment of the invention provides a method for realizing the SPI slave machine by the GPIO based on the CPU,
referring to fig. 1, fig. 1 shows a method for implementing an SPI slave function based on a GPIO of a CPU in an embodiment of the present invention, where the method includes:
the whole process comprises a setting step, an initialization step and a reading and writing operation step.
Wherein the setting step: referring to fig. 3, GPIO1 is set as an input function, GPIO2 is set as an output function, GPIO3 is set as an input function, GPIO4 is set as an input function, GPIO3 rising edge interrupt is set, GPIO3 interrupt processing function GPIO3_ irs () is mounted, the number of received bits is 0, and the number of transmitted bits is 0; enabling GPIO3 interrupts.
The initialization process is as shown in fig. 4, S10, entering the interrupt handling function gpio3_ irs (), and then step S11;
s11, judging whether GPIO4 is equal to 0, if yes, entering step S12, and if no, entering step S21;
i.e., determine whether the slave enable signal at the GPIO4 pin is equal to 0 (low).
S12, reading one bit of GPIO1, and proceeding to step S13;
that is, when the slave enable signal at the pin GPIO4 is equal to 0, which indicates that the number of bits read is not enough to constitute a byte, the process continues to step S12 to read one bit of GPIO 1.
S13, writing GPIO2 specific content, and proceeding to step S14;
the CPU as a slave sends a bit number to the MCU as a master through the GPIO2 pin.
S14, adding 1 to the number of received bits and 1 to the number of sent bits, and going to step S15;
s21, the read bits constitute a byte, and proceed to step S22;
that is, when the slave enable signal at the GPIO4 pin is not equal to 0, which indicates that the read bits can constitute a byte, S21 is performed, and the read bits constitute a byte.
S22, the number of receiving bits is 0, the number of sending bits is 0, and the step S15 is proceeded;
s15, interrupting an exit of the interrupt handling function gpio3_ irs ();
referring to fig. 4, the core of the present invention is an interrupt handling function gpio3_ irs (), which handles MCU-initiated SPI timing cycles as the host. When the clock signal of the GPIO3 pin is pulled up from low level to high level, an interrupt request is sent to the CPU as a slave immediately. The CPU as a slave executes the interrupt processing function gpio1_ irs () in response to the interrupt request. Each time the interrupt function is called, the CPU as the slave reads one bit from the MCU as the master through GPIO1 pin MOSI (master data out, slave data in), while transmitting one bit to the MCU as the master through GPIO2 pin MISO (master data in, slave data out).
In the read/write operation step, as shown in fig. 4, when the CPU as the slave enters the interrupt processing function through the clock signal of the GPIO3 pin, it is first determined whether the GPIO4 pin is low (0), because the CS (slave enable signal) must be low to indicate the start of the SPI cycle (see fig. 2). If the CS (slave enable signal) is high, indicating the SPI cycle and the end, it is first determined whether the CS (slave enable signal) is active, and if the CS (slave enable signal) is active, the GPIO1MOSI (master data output) is read, which is one bit of data sent by the MCU to the CPU. And writes one bit of the response byte to GPIO2MISO in the order of MSB (most significant bit of byte sent first) according to the actual action of the current SPI command.
In the embodiment of the invention, each CPU interrupt receives one bit and sends one bit of data to the MCU until the CS is in a high level, and the SPI time sequence is ended. The length of the receive and transmit bits is set to 0 until the next SPI cycle begins.
Therefore, the embodiment of the invention can realize the function of the SPI slave machine on the CPU which does not support the function of the SPI slave machine, has simple structure and easy realization and has low cost.
The GPIO based on CPU realizes the SPI slave function system, and in one embodiment, the system further includes:
a configuration unit configured to use the GPIO1 as a master output slave input signal MOSI, which is an input signal; GPIO2 is a master-input slave-output MISO, which is an output signal; GPIO3 is used as clock signal SCLK and is an input signal; the GPIO4 is an input signal as the slave device enable signal CS; as particularly described above;
the judgment reading unit is used for controlling the CPU to enter an interrupt processing program; when the CPU enters an interrupt processing program, judging whether the slave equipment enabling signal is effective or not; when the slave equipment enabling signal is valid, the SPI cycle starts, the GPIO1MOSI is read, and the MCU sends a bit data to the CPU; as particularly described above;
the sending control unit is used for writing a bit in the response byte through a main equipment data input signal of the GPIO2 pin according to the actual action of the current SPI command and writing according to the sequence of the highest bit of the byte sent first; as particularly described above;
the response control unit is used for receiving one bit and sending data of one bit to the MCU when each CPU is interrupted, and ending the SPI time sequence until the slave equipment enabling signal is in a high level; setting the length of the receiving bit and the sending bit as 0 until the next SPI period starts; as described above.
Based on the above embodiment, the present invention further provides a method for implementing the function of the SPI slave based on the GPIO of the CPU, as shown in fig. 5, the method includes:
s1, the CPU is respectively processed by: a GPIO1 pin connected with a master output slave input signal, a GPIO2 pin connected with a master input slave output signal, a GPIO3 pin connected with a clock signal and a GPIO4 pin connected with a slave device enabling signal are connected with the MCU, the CPU is used as a slave in the SPI protocol, and the MCU is used as a master in the SPI protocol;
the advantage of this step is that when the hardware SPI interface of CPU is not enough, or when the hardware wiring is convenient, the GPIO port can be used for simulating the SPI interface.
S2, selecting a GPIO3 pin of a clock signal to support sending interrupt to the CPU, wherein the interrupt type is set as edge trigger;
the steps have the advantages that an interrupt mechanism is utilized, the polling of a CPU is not needed, the CPU time is saved, and the real-time performance of the system is improved.
And S3, when the MCU changes the clock signal into effective, the MCU sends an interrupt to the CPU through the GPIO3 pin, and the CPU enters an interrupt processing program.
The advantage of this step is that when the interrupt is triggered, the chip select equivalent to the SPI is pulled low, and the process of entering data transmission is started.
S4, when the CPU enters an interrupt processing program and judges that the slave equipment enabling signal is valid, the MCU sends a bit data to the CPU;
this step is actually processed according to the SPI protocol;
s5, the CPU reads the main output slave input signal of the GPIO1 pin in the interrupt program, and reads data from the MCU; meanwhile, data are sent to the MCU through a master input slave output signal of the GPIO2 pin;
this step is also processed according to the SPI protocol;
s6, when an interrupted clock signal is generated, the CPU reads a bit data sent by the MCU and sends a response bit data to the MCU;
the step is processed according to an SPI protocol;
s7, when the CPU reads the bit data of each byte, the read bit data is grouped into one byte.
The step is processed according to an SPI protocol;
the method for realizing the function of the SPI slave machine by the GPIO based on the CPU comprises the steps that relative to the CPU, the GPIO1 is used as a main output slave input signal MOSI and is an input signal; GPIO2 is a master-input slave-output MISO, which is an output signal; GPIO3 is used as clock signal SCLK and is an input signal; the GPIO4 is an input signal as the slave enable signal CS.
The method for realizing the function of the SPI slave machine by the GPIO based on the CPU comprises the following steps that when the MCU changes a clock signal into valid:
when the GPIO3 is pulled up to a high level from a low level, an interrupt request is immediately sent to the CPU; the CPU responds to the interrupt request.
The method for realizing the function of the SPI slave machine based on the GPIO of the CPU comprises the following steps that when the CPU enters an interrupt processing program and judges that an enabling signal of the slave equipment is valid, an MCU sends bit data to the CPU:
the CPU enters an interrupt processing program;
when the CPU enters an interrupt processing program, judging whether the slave equipment enabling signal is effective or not;
when the slave enable signal is valid, the SPI period starts, the GPIO1MOSI is read, and the MCU sends one bit of data to the CPU.
The method for realizing the function of the SPI slave machine by the GPIO based on the CPU, wherein the step of judging whether the enabling signal of the slave machine is effective further comprises the following steps:
if the slave enable signal CS is high, the SPI cycle is indicated and ended.
The method for realizing the function of the SPI slave machine by the GPIO based on the CPU comprises the following steps that when an interrupted clock signal is generated, the CPU reads bit data sent by the MCU and sends responded bit data to the MCU:
according to the actual action of the current SPI command, a main device data input signal through a GPIO2 pin is written into one bit in the response byte, and the main device data input signal is written according to the sequence of the highest bit of the byte sent first;
each CPU is interrupted, receives a bit, and sends data of the bit to the MCU until the slave equipment enabling signal is in a high level, and the SPI time sequence is ended; and sets the length of the receive and transmit bits to 0 until the next SPI cycle begins.
Examples are as follows:
as shown in fig. 1, assuming that the MCU master as the master is a and the CPU slave as the slave is B, a now sends a byte 0x90 data to B, and then B replies a byte 0xAA to a; the invention discloses a method for realizing the function of an SPI slave machine based on GPIO of a CPU, which comprises the following steps:
step 1: MCU host a pulls CS (slave enable signal) low;
step 2: the MCU host A sends the level of the 7 th bit of 0x90 to a MOSI (master data output and slave data input) line, then pulls up a CLK clock line, delays for a plurality of clock cycles, then shifts the byte of 0x90 to the left by 1 bit, and finally pulls down the clock line; in the process, the CPU slave B detects that the CLK clock line is pulled high, triggers interruption, detects whether the CS line is low, receives the level on the MOSI line if the CS line is low, stores the level to the 0 th bit of a variable, and then shifts the variable by 1 bit to the left;
step 3: a cycles step2 above 8 times, while B does the corresponding operation each time the CLK line is pulled low;
step 4: after the circulation is finished, A sends 0x90, CS is pulled up, B receives 0x90, B knows that the equipment A needs to be replied by a data 0xAA according to the instruction of 0x90, and then the next step is carried out;
step 5: a, pulling down CS;
step 6: a, pulling up a CLK clock line, delaying for a plurality of clock cycles, reading the level on the MISO line, storing to the 0 th bit of a variable, and then shifting the variable left by 1 bit; during the process, B detects that the CLK clock line is pulled high, sends the 7 th bit level of 0xAA to the MISO line, and shifts the byte of 0xAA by 1 bit to the left;
step 7: a cycles step6 above 8 times, while B does the corresponding operation each time the CLK line is pulled low;
step 8: after the circulation is finished, A receives 0xAA, CS is raised, and B sends out 0xAA in the process;
step 9: the over is finished.
Therefore, the embodiment of the invention can realize the function of the SPI slave machine on the CPU which does not support the function of the SPI slave machine, has simple structure and easy realization and has low cost.
Based on the above embodiments, the present invention also provides a computer device, including a memory and a processor, where the memory stores a computer program, and the processor includes: a CPU as a slave and an MCU as a master; the processor, when executing the computer program, performs the steps of any of the methods.
In one embodiment, the present invention provides a computer device, which may be a terminal, having an internal structure as shown in fig. 6. The computer device includes a processor, a memory, a network interface, a display screen, and an input system connected by a system bus. Wherein the processor comprises: a CPU as a slave and an MCU as a master, the processor of the computer device being used to provide computing and control capabilities. The memory of the computer device comprises a nonvolatile storage medium and an internal memory. The non-volatile storage medium stores an operating system and a computer program. The internal memory provides an environment for the operation of an operating system and computer programs in the non-volatile storage medium. The network interface of the computer device is used for communicating with an external terminal through a network connection. The computer program is executed by a processor to implement a method of generating a natural language model. The display screen of the computer equipment can be a liquid crystal display screen or an electronic ink display screen, and the input system of the computer equipment can be a touch layer covered on the display screen, a key, a track ball or a touch pad arranged on the shell of the computer equipment, an external keyboard, a touch pad or a mouse and the like.
Those skilled in the art will appreciate that the illustration in fig. 6 is merely a block diagram of a portion of the structure associated with the disclosed aspects and is not intended to limit the computing devices to which the disclosed aspects apply, as particular computing devices may include more or less components than those shown, or may combine certain components, or have a different arrangement of components.
The embodiment of the invention provides computer equipment, which comprises a memory and a processor, wherein the memory stores a computer program, and the processor executes the computer program to realize the following steps:
the CPU is respectively processed by: a GPIO1 pin connected with a master output slave input signal, a GPIO2 pin connected with a master input slave output signal, a GPIO3 pin connected with a clock signal and a GPIO4 pin connected with a slave device enabling signal are connected with the MCU, the CPU is used as a slave in the SPI protocol, and the MCU is used as a master in the SPI protocol; the method has the advantages that when the hardware SPI interface of the CPU is not enough or hardware wiring is convenient, the GPIO port can be used for simulating the SPI interface;
the GPIO3 pin of the selected clock signal supports sending interrupt to the CPU, and the interrupt type is set as edge trigger; the method has the advantages that an interrupt mechanism is utilized, the CPU is not required to poll, the CPU time is saved, and the real-time performance of the system is improved;
when the MCU changes the clock signal into effective, the MCU sends an interrupt to the CPU through the GPIO3 pin, and the CPU enters an interrupt processing program; the method has the advantages that when the triggering is interrupted, the chip selection equivalent to the SPI is pulled low, and the data transmission process is started;
when the CPU enters an interrupt processing program and judges that the slave equipment enabling signal is effective, the MCU sends a bit data to the CPU; this is actually processed according to the SPI protocol;
the CPU reads a main output slave input signal of the GPIO1 pin in an interrupt program, and reads data from the MCU; meanwhile, data are sent to the MCU through a master input slave output signal of the GPIO2 pin; this is also processed according to the SPI protocol;
when an interrupted clock signal is generated, the CPU reads bit data sent by the MCU and sends responded bit data to the MCU; processing according to SPI protocol;
and the CPU reads the bit data of each byte, and the read bit data is combined into one byte.
Processing according to SPI protocol;
in summary, compared with the prior art, the embodiment of the invention has the following advantages:
according to the method and the system for realizing the SPI slave function based on the GPIO of the CPU, the computer equipment and the readable storage medium, when the MCU changes the clock signal into effective, the MCU sends an interrupt to the CPU through the GPIO3 pin, and the CPU enters an interrupt processing program; when the CPU enters an interrupt processing program and judges that the slave equipment enabling signal is effective, the MCU sends a bit data to the CPU; the CPU reads a main output slave input signal of the GPIO1 pin in an interrupt program, and reads data from the MCU; when an interrupted clock signal is generated, the CPU reads bit data sent by the MCU and sends responded bit data to the MCU; and the CPU reads the bit data of each byte, and the read bit data is combined into one byte. The method can realize the function of the SPI slave machine on the CPU which does not support the function of the SPI slave machine, has simple structure and easy realization and has low cost.
The technical features of the above embodiments can be arbitrarily combined, and for the sake of brevity, all possible combinations of the technical features in the above embodiments are not described, but should be considered as the scope of the present specification as long as there is no contradiction between the combinations of the technical features.
The above-mentioned embodiments only express several embodiments of the present application, and the description thereof is more specific and detailed, but not construed as limiting the scope of the invention. It should be noted that, for a person skilled in the art, several variations and modifications can be made without departing from the concept of the present application, which falls within the scope of protection of the present application. Therefore, the protection scope of the present patent shall be subject to the appended claims.
Claims (10)
1. A method for realizing SPI slave function based on GPIO of CPU is characterized in that the method comprises:
the CPU is respectively processed by: a GPIO1 pin connected with a master output slave input signal, a GPIO2 pin connected with a master input slave output signal, a GPIO3 pin connected with a clock signal and a GPIO4 pin connected with a slave device enabling signal are connected with the MCU, the CPU is used as a slave in the SPI protocol, and the MCU is used as a master in the SPI protocol;
the GPIO3 pin of the selected clock signal supports sending interrupt to the CPU, and the interrupt type is set as edge trigger;
when the MCU changes the clock signal into effective, the MCU sends an interrupt to the CPU through the GPIO3 pin, and the CPU enters an interrupt processing program;
when the CPU enters an interrupt processing program and judges that the slave equipment enabling signal is effective, the MCU sends a bit data to the CPU;
the CPU reads a main output slave input signal of the GPIO1 pin in an interrupt program, and reads data from the MCU; meanwhile, data are sent to the MCU through a master input slave output signal of the GPIO2 pin;
when an interrupted clock signal is generated, the CPU reads bit data sent by the MCU and sends responded bit data to the MCU;
and the CPU reads the bit data of each byte, and the read bit data is combined into one byte.
2. The method for realizing the SPI slave function based on the GPIO of the CPU according to the claim 1, wherein, relative to the CPU, the GPIO1 is used as a master output slave input signal MOSI which is an input signal; GPIO2 is a master-input slave-output MISO, which is an output signal; GPIO3 is used as clock signal SCLK and is an input signal; the GPIO4 is an input signal as the slave enable signal CS.
3. The method for implementing the SPI slave function based on the GPIO of the CPU according to claim 1, wherein when the MCU turns the clock signal to active comprises:
when the GPIO3 is pulled up to a high level from a low level, an interrupt request is immediately sent to the CPU; the CPU responds to the interrupt request.
4. The method for realizing the function of the SPI slave machine by the GPIO based on the CPU as claimed in claim 1, wherein when the CPU enters an interrupt processing program and judges that the slave device enabling signal is valid, the step that the MCU sends a bit data to the CPU comprises:
the CPU enters an interrupt processing program;
when the CPU enters an interrupt processing program, judging whether the slave equipment enabling signal is effective or not;
when the slave enable signal is valid, the SPI period starts, the GPIO1MOSI is read, and the MCU sends one bit of data to the CPU.
5. The method for implementing the SPI slave function by the CPU-based GPIO according to claim 4, wherein said step of determining whether the slave enable signal is valid further comprises:
if the slave enable signal CS is high, the SPI cycle is indicated and ended.
6. The method as claimed in claim 5, wherein the step of the CPU reading a bit data from the MCU and sending a response bit data to the MCU each time an interrupt clock signal is generated comprises:
according to the actual action of the current SPI command, a main device data input signal through a GPIO2 pin is written into one bit in the response byte, and the main device data input signal is written according to the sequence of the highest bit of the byte sent first;
each CPU is interrupted, receives a bit, and sends data of the bit to the MCU until the slave equipment enabling signal is in a high level, and the SPI time sequence is ended; and sets the length of the receive and transmit bits to 0 until the next SPI cycle begins.
7. A system for realizing SPI slave function based on GPIO of CPU is characterized in that the system comprises: the MCU is used as a host in the SPI protocol, and the CPU is used as a slave in the SPI protocol;
the CPU as a host machine is respectively controlled by: a GPIO1 pin connected to an MOSI (master output slave input signal), a GPIO2 pin connected to an MISO (master input slave output signal), a GPIO3 pin connected to an SCLK (clock signal), and a GPIO4 pin connected to a CS (slave enable signal) are connected to an MCU as a host;
the GPIO3 pin of the selected clock signal supports sending interrupt to the CPU, and the interrupt type is set as edge trigger;
when the MCU changes the clock signal into effective, the MCU sends an interrupt to the CPU through the GPIO3 pin, and the CPU enters an interrupt processing program;
when the CPU enters an interrupt processing program and judges that the slave equipment enabling signal is effective, the MCU sends a bit data to the CPU;
the CPU reads a main output slave input signal of the GPIO1 pin in an interrupt program, and reads data from the MCU; meanwhile, data are sent to the MCU through a master input slave output signal of the GPIO2 pin;
when an interrupted clock signal is generated, the CPU reads bit data sent by the MCU and sends responded bit data to the MCU;
and the CPU reads the bit data of each byte, and the read bit data is combined into one byte.
8. The CPU-based GPIO enabled SPI slave functionality system of claim 7, further comprising:
a configuration unit configured to use the GPIO1 as a master output slave input signal MOSI, which is an input signal; GPIO2 is a master-input slave-output MISO, which is an output signal; GPIO3 is used as clock signal SCLK and is an input signal; the GPIO4 is an input signal as the slave device enable signal CS;
the judgment reading unit is used for controlling the CPU to enter an interrupt processing program; when the CPU enters an interrupt processing program, judging whether the slave equipment enabling signal is effective or not; when the slave equipment enabling signal is valid, the SPI cycle starts, the GPIO1MOSI is read, and the MCU sends a bit data to the CPU;
the sending control unit is used for writing a bit in the response byte through a main equipment data input signal of the GPIO2 pin according to the actual action of the current SPI command and writing according to the sequence of the highest bit of the byte sent first;
the response control unit is used for receiving one bit and sending data of one bit to the MCU when each CPU is interrupted, and ending the SPI time sequence until the slave equipment enabling signal is in a high level; and sets the length of the receive and transmit bits to 0 until the next SPI cycle begins.
9. A computer device comprising a memory and a processor, the memory storing a computer program, the processor comprising: a CPU as a slave and an MCU as a master; the processor, when executing the computer program, realizes the steps of the method of any one of claims 1 to 6.
10. A computer-readable storage medium, on which a computer program is stored, which, when being executed by a processor, carries out the steps of the method of any one of claims 1 to 6.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201910866165.XA CN110765058A (en) | 2019-09-12 | 2019-09-12 | Method, system, equipment and medium for realizing SPI slave function by GPIO |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201910866165.XA CN110765058A (en) | 2019-09-12 | 2019-09-12 | Method, system, equipment and medium for realizing SPI slave function by GPIO |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN110765058A true CN110765058A (en) | 2020-02-07 |
Family
ID=69329573
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201910866165.XA Pending CN110765058A (en) | 2019-09-12 | 2019-09-12 | Method, system, equipment and medium for realizing SPI slave function by GPIO |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN110765058A (en) |
Cited By (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111984581A (en) * | 2020-08-14 | 2020-11-24 | 广州邦讯信息系统有限公司 | Linux-based SPI bus master-slave device communication system, method and device |
| CN112069103A (en) * | 2020-09-07 | 2020-12-11 | 歌尔科技有限公司 | Method and system for communication between multiple modules and host |
| CN112269338A (en) * | 2020-10-23 | 2021-01-26 | 阳光电源股份有限公司 | GPIO-based digital controller communication method and system |
| CN112417802A (en) * | 2020-11-12 | 2021-02-26 | 深圳市创智成科技股份有限公司 | Method, system, equipment and storage medium for simulating storage chip |
| CN113176751A (en) * | 2021-04-28 | 2021-07-27 | 青岛歌尔智能传感器有限公司 | Data transmission method, device and computer readable storage medium |
| CN113419985A (en) * | 2021-06-15 | 2021-09-21 | 珠海市一微半导体有限公司 | Control method for SPI system to automatically read data and SPI system |
| CN113590520A (en) * | 2021-06-15 | 2021-11-02 | 珠海一微半导体股份有限公司 | Control method for automatically writing data into SPI system and SPI system |
| CN114721317A (en) * | 2022-06-02 | 2022-07-08 | 中国船舶重工集团公司第七0七研究所 | Network communication control system and method based on SPI controller |
| CN115834739A (en) * | 2023-02-16 | 2023-03-21 | 石家庄科林电气股份有限公司 | Receiving method of indefinite-length data frame in platform area intelligent convergence terminal SPI communication |
Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102819512A (en) * | 2012-06-28 | 2012-12-12 | 惠州市德赛西威汽车电子有限公司 | Full-duplex communication device based on SPI and method thereof |
| CN105308585A (en) * | 2013-06-05 | 2016-02-03 | 大陆-特韦斯贸易合伙股份公司及两合公司 | Method for communicating data, communication controller and circuit arrangement |
| CN107301138A (en) * | 2017-06-01 | 2017-10-27 | 深圳震有科技股份有限公司 | A kind of universal serial bus bridging method and serial bus system |
| CN109726163A (en) * | 2018-12-30 | 2019-05-07 | 广东大普通信技术有限公司 | A kind of communication system based on SPI, method, equipment and storage medium |
| US10318179B1 (en) * | 2017-12-27 | 2019-06-11 | Nxp B.V. | Host device to embedded multi-media card device communication |
| CN109902053A (en) * | 2017-12-07 | 2019-06-18 | 厦门雅迅网络股份有限公司 | A kind of SPI communication method, terminal device and storage medium based on dual controller |
-
2019
- 2019-09-12 CN CN201910866165.XA patent/CN110765058A/en active Pending
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102819512A (en) * | 2012-06-28 | 2012-12-12 | 惠州市德赛西威汽车电子有限公司 | Full-duplex communication device based on SPI and method thereof |
| CN105308585A (en) * | 2013-06-05 | 2016-02-03 | 大陆-特韦斯贸易合伙股份公司及两合公司 | Method for communicating data, communication controller and circuit arrangement |
| CN107301138A (en) * | 2017-06-01 | 2017-10-27 | 深圳震有科技股份有限公司 | A kind of universal serial bus bridging method and serial bus system |
| CN109902053A (en) * | 2017-12-07 | 2019-06-18 | 厦门雅迅网络股份有限公司 | A kind of SPI communication method, terminal device and storage medium based on dual controller |
| US10318179B1 (en) * | 2017-12-27 | 2019-06-11 | Nxp B.V. | Host device to embedded multi-media card device communication |
| CN109726163A (en) * | 2018-12-30 | 2019-05-07 | 广东大普通信技术有限公司 | A kind of communication system based on SPI, method, equipment and storage medium |
Non-Patent Citations (2)
| Title |
|---|
| 邓彬伟: "嵌入式系统中可配置式GPIO模拟SPI总线方法的设计与实现", 《电子技术》 * |
| 郭静华等: "SPI总线从机接口实时模拟的实现", 《东北农业大学学报》 * |
Cited By (13)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111984581B (en) * | 2020-08-14 | 2022-05-10 | 广州邦讯信息系统有限公司 | Linux-based SPI bus master-slave device communication system, method and device |
| CN111984581A (en) * | 2020-08-14 | 2020-11-24 | 广州邦讯信息系统有限公司 | Linux-based SPI bus master-slave device communication system, method and device |
| CN112069103A (en) * | 2020-09-07 | 2020-12-11 | 歌尔科技有限公司 | Method and system for communication between multiple modules and host |
| CN112269338A (en) * | 2020-10-23 | 2021-01-26 | 阳光电源股份有限公司 | GPIO-based digital controller communication method and system |
| CN112417802B (en) * | 2020-11-12 | 2022-04-19 | 深圳市创智成科技股份有限公司 | Method, system, equipment and storage medium for simulating storage chip |
| CN112417802A (en) * | 2020-11-12 | 2021-02-26 | 深圳市创智成科技股份有限公司 | Method, system, equipment and storage medium for simulating storage chip |
| CN113176751A (en) * | 2021-04-28 | 2021-07-27 | 青岛歌尔智能传感器有限公司 | Data transmission method, device and computer readable storage medium |
| CN113590520A (en) * | 2021-06-15 | 2021-11-02 | 珠海一微半导体股份有限公司 | Control method for automatically writing data into SPI system and SPI system |
| CN113419985A (en) * | 2021-06-15 | 2021-09-21 | 珠海市一微半导体有限公司 | Control method for SPI system to automatically read data and SPI system |
| CN113590520B (en) * | 2021-06-15 | 2024-05-03 | 珠海一微半导体股份有限公司 | Control method for automatically writing data in SPI system and SPI system |
| CN114721317A (en) * | 2022-06-02 | 2022-07-08 | 中国船舶重工集团公司第七0七研究所 | Network communication control system and method based on SPI controller |
| CN114721317B (en) * | 2022-06-02 | 2022-09-16 | 中国船舶重工集团公司第七0七研究所 | Network communication control system and method based on SPI controller |
| CN115834739A (en) * | 2023-02-16 | 2023-03-21 | 石家庄科林电气股份有限公司 | Receiving method of indefinite-length data frame in platform area intelligent convergence terminal SPI communication |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN110765058A (en) | Method, system, equipment and medium for realizing SPI slave function by GPIO | |
| US5729683A (en) | Programming memory devices through the parallel port of a computer system | |
| KR101988260B1 (en) | EMBEDDED MULTIMEDIA CARD(eMMC), AND METHOD FOR OPERATING THE eMMC | |
| KR102111741B1 (en) | EMBEDDED MULTIMEDIA CARD(eMMC), AND METHODS FOR OPERATING THE eMMC | |
| CN106681953B (en) | Slave connected with host by using I2C bus and communication method thereof | |
| KR20140036094A (en) | Host for controlling non-volatile memory crad, system including the same and operating method there-of | |
| US10509595B2 (en) | System and method for communication in a semiconductor device | |
| TW200935234A (en) | System and method for setting access and modification for synchronous serial interface NAND | |
| CN115858431B (en) | Data transmission control method, controller and electronic equipment | |
| CN112131156B (en) | Data transmission method, system, electronic equipment and storage medium | |
| CN112559410A (en) | FPGA-based LIO bus extension UART peripheral system and method | |
| CN113849433A (en) | Bus controller execution method and device, bus controller, computer equipment and storage medium | |
| CN115309687A (en) | Serial Peripheral Interface (SPI) automatic register address increment across data frames | |
| US6366877B1 (en) | Method and device for emulation of peripheral input/output (I/O) controller of a computer system | |
| JP2000066994A (en) | Lpc/isa bridge and its bridge method | |
| JP3477306B2 (en) | Extended input / output interface | |
| CN110765060A (en) | Method, device, equipment and medium for converting MDIO bus into parallel bus | |
| KR100423017B1 (en) | Microcomputer | |
| CN113326220A (en) | Method and equipment for acquiring information of peripheral electronic tag | |
| US20050144331A1 (en) | On-chip serialized peripheral bus system and operating method thereof | |
| CN112685344B (en) | DMA programming circuit and programming method based on same | |
| US20230305816A1 (en) | Device and method for handling programming language function | |
| JP2000112878A (en) | Device and method for controlling timing of transfer request in data processor | |
| JP2009026165A (en) | Controller, electronic apparatus, and method for controlling electronic apparatus | |
| WO2016053146A1 (en) | Computer system |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| RJ01 | Rejection of invention patent application after publication | ||
| RJ01 | Rejection of invention patent application after publication |
Application publication date: 20200207 |