CN109726163A - A kind of communication system based on SPI, method, equipment and storage medium - Google Patents
A kind of communication system based on SPI, method, equipment and storage medium Download PDFInfo
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- CN109726163A CN109726163A CN201811648586.7A CN201811648586A CN109726163A CN 109726163 A CN109726163 A CN 109726163A CN 201811648586 A CN201811648586 A CN 201811648586A CN 109726163 A CN109726163 A CN 109726163A
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Abstract
The embodiment of the invention discloses a kind of communication system based on SPI, method, equipment and storage medium, which includes: a host and at least one slave configured with slave SPI interface module configured with general SPI interface module；Slave SPI interface module includes data field, serial clock pin, host input/slave output data pin, host output/slave input data pin and slave selection pin；Data field includes interrupt register, and the first interrupt bit of host triggering slave and the second interrupt bit of slave triggering host are provided in interrupt register；The default pin of host is connected to the interrupt register of slave SPI interface module, so that host carries out write operation to the first interrupt bit and carries out read operation to the second interrupt bit；The slave is set as the first interrupt bit and carries out read operation and carry out write operation to the second interrupt bit.The load of CPU processing SPI interface data is effectively reduced in the embodiment of the present invention.
Description
Technical field
The present embodiments relate to the communication technology more particularly to a kind of communication system based on SPI, method, equipment and storages
Deposit medium.
Background technique
Serial Peripheral Interface (SPI) (Serial Peripheral Interface, SPI) is a kind of synchronous serial Peripheral Interface,
The interface generally uses 4 lines: serial time clock line SCK, host input/slave output data line MISO, host output/slave are defeated
Enter data line MOSI and the effective slave selection line NSS of low level.
As shown in Figure 1, common SPI interface, needs to send data, just writes data into and send buffer area, SPI interface is just
Start to send；Data are received simultaneously to receiving in buffer area, and received data can be by way of interruption or poll by center
Processor (Central Processing Unit, CPU) processing.
But when in the prior art, data are sent, if slave receives buffer area and expires, host continues to send, and makes
At the loss of data flow.Data are sent by byte, without verification scheme, when CPU receives data by byte, because frequent interrupt is adjusted
With and lead to CPU processing capacity inefficiency.
Summary of the invention
The embodiment of the present invention provides a kind of communication system based on SPI, method, equipment and storage medium, is reduced with realizing
The load of CPU processing SPI interface data.
In a first aspect, the embodiment of the invention provides a kind of communication systems based on SPI, comprising:
One host and at least one slave configured with slave SPI interface module configured with general SPI interface module；
The slave SPI interface module includes that data field, serial clock pin, host input/slave output data pin, host are defeated
Out/slave input data pin and slave select pin；The data field includes interrupt register, main to standby buffer area and for arriving
Master cache area is provided in the interrupt register in the first interrupt bit of host triggering slave and the second of slave triggering host
Disconnected position；The general SPI interface module is connected with the slave SPI interface module corresponding pin signal；The host is preset
Pin is connected to the interrupt register of the slave SPI interface module, so that the host writes first interrupt bit
It operates and read operation is carried out to second interrupt bit；The slave is set as carrying out read operation and right to first interrupt bit
Second interrupt bit carries out write operation.
Second aspect, the embodiment of the invention also provides a kind of communication means based on SPI, comprising:
When host sends data, data frame is generated according to preset data frame structure according to data to be sent；Wherein, institute
The structure for stating data frame is frame length, the payload of 0-60 byte and the CRC check value of 2 bytes of 1 byte；
Read the interrupt register of slave SPI interface module；
If the first interrupt bit of the interrupt register is removed, to the slave SPI interface as unit of two bytes
Module sends the data frame；Wherein, previous byte is write-in data address, and latter byte is and said write data address pair
The 1st bit of the data for the data frame answered, said write data address are read-write operation marker, and are identified as and write
It operates, the master in the 2-7 bit correspondence slave SPI interface module to the address of standby buffer area；
After a data frame is sent completely, the interrupt register execution of the slave SPI interface module is write
First interrupt bit set of the interrupt register is generated interruption to trigger slave, slave executes SPI data receiver by operation
Operation.
The third aspect, the embodiment of the invention also provides a kind of communication means based on SPI, comprising:
When slave sends data, data frame is generated according to preset data frame structure according to data to be sent；Wherein, institute
The structure for stating data frame is frame length, the payload of 0-60 byte and the CRC check value of 2 bytes of 1 byte；
Read the interrupt register of slave SPI interface module；
If the second interrupt bit of the interrupt register is removed, to the slave SPI interface as unit of two bytes
Module sends the data frame；Wherein, previous byte is write-in data address, and latter byte is and said write data address pair
The 1st bit of the data for the data frame answered, said write data address are read-write operation marker, and are identified as and write
It operates, the standby address for arriving master cache area in the 2-7 bit correspondence slave SPI interface module；
After a data frame is sent completely, the interrupt register execution of the slave SPI interface module is write
Second interrupt bit set of the interrupt register is generated interruption to trigger host, host executes SPI data receiver by operation
Operation.
Fourth aspect, the embodiment of the invention also provides a kind of equipment, the equipment includes:
One or more processors；
Memory, for storing one or more programs；
General SPI interface module；
When one or more of programs are executed by one or more of processors, so that one or more of processing
Device realizes such as the communication means provided by any embodiment of the invention based on SPI.
5th aspect, the embodiment of the invention also provides a kind of equipment, the equipment includes:
One or more processors；
Memory, for storing one or more programs；
Slave SPI interface module；
When one or more of programs are executed by one or more of processors, so that one or more of processing
Device realizes such as the communication means provided by any embodiment of the invention based on SPI.
6th aspect, it is described the embodiment of the invention also provides a kind of storage medium comprising computer executable instructions
Computer executable instructions by computer processor when being executed for executing if any embodiment of that present invention offer is based on SPI
Communication means.
7th aspect, it is described the embodiment of the invention also provides a kind of storage medium comprising computer executable instructions
Computer executable instructions by computer processor when being executed for executing if any embodiment of that present invention offer is based on SPI
Communication means.
The embodiment of the present invention is SPI interface by optimizing the SPI interface module of slave and providing data exchange module
The communication mechanism based on frame is provided, by interrupt register, provides control and the data answering machine of data flow for SPI interface
System effectively reduces the load of CPU processing SPI interface data by the above mechanism.
Detailed description of the invention
Fig. 1 is the structural schematic diagram of general SPI interface module in the prior art；
Fig. 2 is the structural schematic diagram of communication system of one of the embodiment of the present invention based on SPI；
Fig. 3 is the structural schematic diagram of the slave SPI interface module 201 in the embodiment of the present invention；
Fig. 4 is the content structure figure of the address byte in the embodiment of the present invention；
Fig. 5 is the flow chart of communication means of one of the embodiment of the present invention based on SPI；
Fig. 6 is the structure chart of the data frame in the embodiment of the present invention；
Fig. 7 is the flow chart of another communication means based on SPI in the embodiment of the present invention；
Fig. 8 is the structural schematic diagram of one of embodiment of the present invention equipment；
Fig. 9 is the structural schematic diagram of another equipment in the embodiment of the present invention.
Specific embodiment
The present invention is described in further detail with reference to the accompanying drawings and examples.It is understood that this place is retouched
The specific embodiment stated is used only for explaining the present invention rather than limiting the invention.It also should be noted that in order to just
Only the parts related to the present invention are shown in description, attached drawing rather than entire infrastructure.
Embodiment
Fig. 2 is a kind of structural schematic diagram of the communication system based on SPI provided in an embodiment of the present invention, and the present embodiment can fit
It is based on the case where SPI interface is communicated for host and slave, which includes:
One host 10 configured with general SPI interface module 101 is configured with slave SPI interface module at least one
201 slave 20.In Fig. 2, by taking a host and a slave connection as an example.
As shown in figure 3, the slave SPI interface module 201 include data field, serial clock pin CLK, host input/
Slave output data pin MISO, host output/slave input data pin MOSI and slave select pin NSS.This four are drawn
Foot and the pin of the general SPI interface module 101 of host 10 connect one to one.Slave selects pin NSS effective for low level,
That is the slave selection pin of the general SPI interface module 101 of host 10 exports low level, then the slave is selected.
The data field includes interrupt register, main to standby buffer area and standby to master cache area, in the interrupt register
It is provided with the first interrupt bit of host triggering slave and the second interrupt bit of slave triggering host；In Fig. 3, indicated in first with SI
Disconnected position, indicates the second interrupt bit with MI, but the first interrupt bit and the second interrupt bit are not limited to the position the bit configured in Fig. 3.It is described logical
It is connected with SPI interface module with the slave SPI interface module corresponding pin signal；The default pin of the host is connected to institute
The interrupt register of slave SPI interface module is stated, so that the host carries out write operation to first interrupt bit and to described
Second interrupt bit carries out read operation；The slave is set as carrying out read operation to first interrupt bit and interrupt to described second
Position carries out write operation.
Wherein, host 10 and slave 20 can be written and read behaviour to the interrupt register of slave SPI interface module 201
Make.The interrupt register of slave SPI interface module 201 is read, when interruption is posted when host 10 sends data for host 10
When first interrupt bit of storage is removed, Xiang Congji SPI interface module 201 sends data, in case slave 20 is from slave SPI interface
The master of module 201 copies data to standby buffer area.When host 10 receives data, the interruption of slave SPI interface module 201 is read
Register reads the standby of slave SPI interface module 201 and arrives master cache area number if the second interrupt bit set of interrupt register
According to.The interrupt register of slave SPI interface module 201 is read, when interruption is posted when slave 20 sends data for slave 20
When second interrupt bit of storage is removed, Xiang Congji SPI interface module 201 sends data, in case host 10 is from slave SPI interface
The standby of module 201 copies data to main buffering region.When slave 20 receives data, the interruption of slave SPI interface module 201 is read
Register, if the first interrupt bit set of interrupt register, the master for reading slave SPI interface module 201 is to for buffer area number
According to.
Specifically, slave SPI interface module 201 is the IP kernel comprising SPI interface function, as shown in Figure 3.MOSI draws
Foot receiving host to slave information, while MISO pin send slave to host information.Slave SPI interface module 201 with
Two bytes are process cycle, and first character section is address, and the byte content is as shown in Figure 4.First bit are WRB, are used
To indicate that this process cycle is write operation or read operation.Seven bit next be data field address, address range is from 0
To 127.
By taking host is to slave SPI interface module 201 as an example, if WRB is 1, it is shown to be host write operation, slave SPI connects
Mouth mold block 201 can be copied the second byte data received from MOSI pin to by the address of the first byte main to standby buffer area
In.If WRB is 0, it is shown to be host read operation, slave SPI interface module 201 is by the address of the first byte from standby to host buffer
Area copies a byte data, and gives the byte data to host by MISO pin.It is understood that slave is to slave
The process that SPI interface module is written and read is similar, only between slave and slave SPI interface module sending and receiving data path
It is different.
The interrupt register for being 0 to address allows host to complete read operation or write operation to interrupt register.Reading is grasped
Make, if MOSI pin receives the address that the first byte is 0, slave SPI interface module 201 can be posted interruption in second byte
The content of storage is sent to host by MISO pin.To write operation, if receiving the first byte from MOSI pin is 0x80's
Address, slave SPI interface module 201 can will be write in interrupt register from received second byte of MOSI pin.It can manage
Solution, the process that slave is written and read slave SPI interface module is similar, only slave and slave SPI interface module
Between receive and dispatch register data path it is different.
The present embodiment also provides a kind of communication means based on SPI.As shown in figure 5, when host sends data, slave is received
When data, this method comprises:
Step 510, when host sends data, according to data to be sent, according to preset data frame structure, generate data
Frame.Wherein, as shown in fig. 6, the structure of the data frame is frame length, the payload of 0-60 byte and the school CRC of 2 bytes of 1 byte
Test value.
Step 520, the interrupt register for reading slave SPI interface module.
If the first interrupt bit of step 530, the interrupt register is removed, to the slave as unit of two bytes
SPI interface module sends the data frame.
Wherein, previous byte is write-in data address, and latter byte is the number corresponding with said write data address
According to the data of frame, the 1st bit of said write data address are read-write operation marker, and are identified as write operation, i.e., the 1st
A bit is 1, and the master in the 2-7 bit correspondence slave SPI interface module to the address of standby buffer area, i.e. data will
Write to a master to the destination register of standby buffer area.
Step 540, the interruption deposit after a data frame is sent completely, to the slave SPI interface module
Device executes write operation, by the first interrupt bit set of the interrupt register.After being arranged in this way, it can trigger in slave generation
It is disconnected, and then slave executes SPI data reception operation.
Step 550, when slave receives data, mapped by memory and read the main data frame to standby buffer area.
Step 560, after having read the data frame, carry out CRC check；
If step 570, CRC check success, save the data read；
If step 580, CRC check failure, abandon the data read；
Step 590 executes write operation to the interrupt register of the slave SPI interface module, by the interrupt register
First interrupt bit clear.
Wherein, bit clear is interrupted by first, to notify host, slave that the reception of data is completed, in this way, host next time is sent out
When sending data, the first interrupt bit for reading interrupt register is removed, and can be carried out data and be had sent.
As shown in fig. 7, when slave sends data, when host receiving data, this method comprises:
Step 710, when slave sends data, according to data to be sent, according to preset data frame structure, generate data
Frame.Wherein, the structure of the data frame is frame length, the payload of 0-60 byte and the CRC check value of 2 bytes of 1 byte.
Step 720, the interrupt register for reading slave SPI interface module.
If the second interrupt bit of step 730, the interrupt register is removed, to the slave as unit of two bytes
SPI interface module sends the data frame.
Wherein, previous byte is write-in data address, and latter byte is the number corresponding with said write data address
According to the data of frame, the 1st bit of said write data address are read-write operation marker, and are identified as write operation, 2-7
The standby address for arriving master cache area in a bit correspondence slave SPI interface module.
Step 740, the interruption deposit after a data frame is sent completely, to the slave SPI interface module
Device executes write operation, by the second interrupt bit set of the interrupt register.Interruption is generated to trigger host, host executes SPI
Data reception operation.
Step 750, when host receiving data, read slave SPI interface module interrupt register.
If the second interrupt bit set of step 760, the interrupt register, Xiang Suoshu slave SPI interface module is sent
The preset data address of one byte, to read out the frame length of data frame to be received.
Wherein, the 1st bit of the preset data address are read-write operation marker, and are identified as read operation, 2-
7 bit are standby to master cache area head register address in the slave SPI interface module.
Step 770, according to the frame length of the data frame to be received, as unit of a byte, circulation, which is read, standby arrives master cache
The remaining data in area.
Step 780, after having read the remaining data, carry out CRC check.
If step 790, CRC check success, save the data read.
If step 7100, CRC check failure, abandon the data read.
Step 7110 executes write operation to the interrupt register of the slave SPI interface module, by the interrupt register
Second interrupt bit clear.
As shown in figure 3, host can be by the corresponding bit triggering of setting SI to the interruption of slave.Slave can pass through
It is bit corresponding that MI is set, and exports GPIO pin, if host connects the GPIO pin as hard break interface, this bit
Position can be used as the interrupt bit of slave triggering host.
The technical solution of the present embodiment, by optimize slave SPI interface module and provide data exchange module, be
SPI interface provides the communication mechanism based on frame, by interrupt register, provides the control sum number of data flow for SPI interface
The load of CPU processing SPI interface data is effectively reduced by the above mechanism according to acknowledgement mechanism.
Fig. 8 is a kind of structural schematic diagram of equipment provided in an embodiment of the present invention, as shown in figure 8, the equipment includes processing
Device 810, memory 820 and general SPI interface module 830；The quantity of processor 810 can be one or more, Fig. 8 in equipment
In by taking a processor 810 as an example；Processor 810, memory 820 and general SPI interface module 830 in equipment can pass through
Bus or other modes connect, in Fig. 8 for being connected by bus.
Memory 820 is used as a kind of computer readable storage medium, can be used for storing software program, journey can be performed in computer
Sequence and module, such as the corresponding program instruction/module of the communication means based on SPI in the embodiment of the present invention.Processor 810 is logical
Cross the operation software program, instruction and the module that are stored in memory 820, thereby executing equipment various function application and
The above-mentioned communication means based on SPI applied to host is realized in data processing.
Memory 820 can mainly include storing program area and storage data area, wherein storing program area can store operation system
Application program needed for system, at least one function；Storage data area, which can be stored, uses created data etc. according to terminal.This
Outside, memory 820 may include high-speed random access memory, can also include nonvolatile memory, for example, at least one
Disk memory, flush memory device or other non-volatile solid state memory parts.In some instances, memory 820 can be into one
Step includes the memory remotely located relative to processor 810, these remote memories can pass through network connection to equipment.On
The example for stating network includes but is not limited to internet, intranet, local area network, mobile radio communication and combinations thereof.General SPI connects
Mouth mold block 830 carries out SPI communication for host and slave.
The embodiment of the present invention also provides a kind of storage medium comprising computer executable instructions, and the computer is executable
Instruction by computer processor when being executed for executing a kind of communication means based on SPI, comprising:
When host sends data, data frame is generated according to preset data frame structure according to data to be sent；Wherein, institute
The structure for stating data frame is frame length, the payload of 0-60 byte and the CRC check value of 2 bytes of 1 byte；
Read the interrupt register of slave SPI interface module；
If the first interrupt bit of the interrupt register is removed, to the slave SPI interface as unit of two bytes
Module sends the data frame；Wherein, previous byte is write-in data address, and latter byte is and said write data address pair
The 1st bit of the data for the data frame answered, said write data address are read-write operation marker, and are identified as and write
It operates, the master in the 2-7 bit correspondence slave SPI interface module to the address of standby buffer area；
After a data frame is sent completely, the interrupt register execution of the slave SPI interface module is write
First interrupt bit set of the interrupt register is generated interruption to trigger slave, slave executes SPI data receiver by operation
Operation.
Certainly, a kind of storage medium comprising computer executable instructions, computer provided by the embodiment of the present invention
The method operation that executable instruction is not limited to the described above can also be performed provided by any embodiment of the invention applied to master
Relevant operation in the communication means based on SPI of machine.
By the description above with respect to embodiment, it is apparent to those skilled in the art that, the present invention
It can be realized by software and required common hardware, naturally it is also possible to which by hardware realization, but in many cases, the former is more
Good embodiment.Based on this understanding, technical solution of the present invention substantially in other words contributes to the prior art
Part can be embodied in the form of software products, which can store in computer readable storage medium
In, floppy disk, read-only memory (Read-Only Memory, ROM), random access memory (Random such as computer
Access Memory, RAM), flash memory (FLASH), hard disk or CD etc., including some instructions are with so that a computer is set
Standby (can be personal computer, server or the network equipment etc.) executes method described in the embodiment of the present invention.
Fig. 9 is a kind of structural schematic diagram of equipment provided in an embodiment of the present invention, as shown in figure 9, the equipment includes processing
Device 910, memory 920 and slave SPI interface module 930；The quantity of processor 910 can be one or more, Fig. 9 in equipment
In by taking a processor 910 as an example；Processor 910, memory 920 and slave SPI interface module 930 in equipment can pass through
Bus or other modes connect, in Fig. 9 for being connected by bus.
Memory 920 is used as a kind of computer readable storage medium, can be used for storing software program, journey can be performed in computer
Sequence and module, such as the corresponding program instruction/module of the communication means based on SPI in the embodiment of the present invention.Processor 910 is logical
Cross the operation software program, instruction and the module that are stored in memory 920, thereby executing equipment various function application and
The above-mentioned communication means based on SPI applied to slave is realized in data processing.
Memory 920 can mainly include storing program area and storage data area, wherein storing program area can store operation system
Application program needed for system, at least one function；Storage data area, which can be stored, uses created data etc. according to terminal.This
Outside, memory 920 may include high-speed random access memory, can also include nonvolatile memory, for example, at least one
Disk memory, flush memory device or other non-volatile solid state memory parts.In some instances, memory 920 can be into one
Step includes the memory remotely located relative to processor 910, these remote memories can pass through network connection to equipment.On
The example for stating network includes but is not limited to internet, intranet, local area network, mobile radio communication and combinations thereof.Slave SPI connects
Mouth mold block 930 carries out SPI communication for host and slave.
The embodiment of the present invention also provides a kind of storage medium comprising computer executable instructions, and the computer is executable
Instruction by computer processor when being executed for executing a kind of communication means based on SPI, comprising:
When slave sends data, data frame is generated according to preset data frame structure according to data to be sent；Wherein, institute
The structure for stating data frame is frame length, the payload of 0-60 byte and the CRC check value of 2 bytes of 1 byte；
Read the interrupt register of slave SPI interface module；
If the second interrupt bit of the interrupt register is removed, to the slave SPI interface as unit of two bytes
Module sends the data frame；Wherein, previous byte is write-in data address, and latter byte is and said write data address pair
The 1st bit of the data for the data frame answered, said write data address are read-write operation marker, and are identified as and write
It operates, the standby address for arriving master cache area in the 2-7 bit correspondence slave SPI interface module；
After a data frame is sent completely, the interrupt register execution of the slave SPI interface module is write
Second interrupt bit set of the interrupt register is generated interruption to trigger host, host executes SPI data receiver by operation
Operation.
Certainly, a kind of storage medium comprising computer executable instructions, computer provided by the embodiment of the present invention
The operation of method that executable instruction is not limited to the described above, can also be performed it is provided by any embodiment of the invention be applied to from
Relevant operation in the communication means based on SPI of machine.
By the description above with respect to embodiment, it is apparent to those skilled in the art that, the present invention
It can be realized by software and required common hardware, naturally it is also possible to which by hardware realization, but in many cases, the former is more
Good embodiment.Based on this understanding, technical solution of the present invention substantially in other words contributes to the prior art
Part can be embodied in the form of software products, which can store in computer readable storage medium
In, floppy disk, read-only memory (Read-Only Memory, ROM), random access memory (Random such as computer
Access Memory, RAM), flash memory (FLASH), hard disk or CD etc., including some instructions are with so that a computer is set
Standby (can be personal computer, server or the network equipment etc.) executes method described in the embodiment of the present invention.
Note that the above is only a better embodiment of the present invention and the applied technical principle.It will be appreciated by those skilled in the art that
The invention is not limited to the specific embodiments described herein, be able to carry out for a person skilled in the art it is various it is apparent variation,
It readjusts and substitutes without departing from protection scope of the present invention.Therefore, although being carried out by above embodiments to the present invention
It is described in further detail, but the present invention is not limited to the above embodiments only, without departing from the inventive concept, also
It may include more other equivalent embodiments, and the scope of the invention is determined by the scope of the appended claims.
Claims (9)
1. a kind of communication system based on SPI characterized by comprising
One host and at least one slave configured with slave SPI interface module configured with general SPI interface module；It is described
Slave SPI interface module include data field, serial clock pin, host input/slave output data pin, host output/from
Machine input data pin and slave select pin；The data field includes interrupt register, master to standby buffer area and for slow to master
Area is deposited, the first interrupt bit of host triggering slave is provided in the interrupt register and the second of slave triggering host is interrupted
Position；The general SPI interface module is connected with the slave SPI interface module corresponding pin signal；The default of the host is drawn
Foot is connected to the interrupt register of the slave SPI interface module, so that the host carries out writing behaviour to first interrupt bit
Make and read operation is carried out to second interrupt bit；The slave is set as carrying out first interrupt bit read operation and to institute
It states the second interrupt bit and carries out write operation.
2. a kind of communication means based on SPI characterized by comprising
When host sends data, data frame is generated according to preset data frame structure according to data to be sent；Wherein, the number
Structure according to frame is frame length, the payload of 0-60 byte and the CRC check value of 2 bytes of 1 byte；
Read the interrupt register of slave SPI interface module；
If the first interrupt bit of the interrupt register is removed, to the slave SPI interface module as unit of two bytes
Send the data frame；Wherein, previous byte is write-in data address, and latter byte is corresponding with said write data address
The 1st bit of the data of the data frame, said write data address are read-write operation marker, and are identified as write operation,
Master in the 2-7 bit correspondence slave SPI interface module is to the address of standby buffer area；
After a data frame is sent completely, write operation is executed to the interrupt register of the slave SPI interface module,
By the first interrupt bit set of the interrupt register, interruption is generated to trigger slave, slave executes SPI data reception operation.
3. according to the method described in claim 2, it is characterized by further comprising:
When host receiving data, the interrupt register of slave SPI interface module is read；
If the second interrupt bit set of the interrupt register, Xiang Suoshu slave SPI interface module sends the default of a byte
Data address, to read out the frame length of data frame to be received；The 1st bit of the preset data address are read-write operation mark
Know position, and be identified as read operation, the 2-7 bit are standby to master cache area head register in the slave SPI interface module
Address；
According to the frame length of the data frame to be received, as unit of a byte, circulation reads standby to the remaining data in master cache area；
After having read the remaining data, CRC check is carried out；
If CRC check success, saves the data read；
If CRC check fails, the data read are abandoned；
Write operation is executed to the interrupt register of the slave SPI interface module, by the second interrupt bit of the interrupt register
It removes.
4. a kind of communication means based on SPI characterized by comprising
When slave sends data, data frame is generated according to preset data frame structure according to data to be sent；Wherein, the number
Structure according to frame is frame length, the payload of 0-60 byte and the CRC check value of 2 bytes of 1 byte；
Read the interrupt register of slave SPI interface module；
If the second interrupt bit of the interrupt register is removed, to the slave SPI interface module as unit of two bytes
Send the data frame；Wherein, previous byte is write-in data address, and latter byte is corresponding with said write data address
The 1st bit of the data of the data frame, said write data address are read-write operation marker, and are identified as write operation,
The standby address for arriving master cache area in the 2-7 bit correspondence slave SPI interface module；
After a data frame is sent completely, write operation is executed to the interrupt register of the slave SPI interface module,
By the second interrupt bit set of the interrupt register, interruption is generated to trigger host, host executes SPI data reception operation.
5. according to the method described in claim 4, it is characterized by further comprising:
When slave receives data, is mapped by memory and read the main data frame to standby buffer area；
After having read the data frame, CRC check is carried out；
If CRC check success, saves the data read；
If CRC check fails, the data read are abandoned；
Write operation is executed to the interrupt register of the slave SPI interface module, by the first interrupt bit of the interrupt register
It removes.
6. a kind of equipment, which is characterized in that the equipment includes:
One or more processors；
Memory, for storing one or more programs；
General SPI interface module；
When one or more of programs are executed by one or more of processors, so that one or more of processors are real
Now as claimed in claim 2 or claim 3 based on the communication means of SPI.
7. a kind of equipment, which is characterized in that the equipment includes:
One or more processors；
Memory, for storing one or more programs；
Slave SPI interface module；
When one or more of programs are executed by one or more of processors, so that one or more of processors are real
Now as described in claim 4 or 5 based on the communication means of SPI.
8. a kind of storage medium comprising computer executable instructions, which is characterized in that the computer executable instructions by
For executing communication means as claimed in claim 2 or claim 3 based on SPI when computer processor executes.
9. a kind of storage medium comprising computer executable instructions, which is characterized in that the computer executable instructions by
For executing communication means as described in claim 4 or 5 based on SPI when computer processor executes.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201811648586.7A CN109726163B (en) | 2018-12-30 | 2018-12-30 | SPI-based communication system, method, equipment and storage medium |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201811648586.7A CN109726163B (en) | 2018-12-30 | 2018-12-30 | SPI-based communication system, method, equipment and storage medium |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN109726163A true CN109726163A (en) | 2019-05-07 |
| CN109726163B CN109726163B (en) | 2020-12-11 |
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Cited By (10)
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| CN110531686A (en) * | 2019-09-28 | 2019-12-03 | 徐州可云智能科技有限公司 | A kind of devices and methods therefor based on single master mostly from the more hosts of protocol realization |
| CN110765058A (en) * | 2019-09-12 | 2020-02-07 | 深圳震有科技股份有限公司 | Method, system, equipment and medium for realizing SPI slave function by GPIO |
| CN111427815A (en) * | 2020-03-05 | 2020-07-17 | 深圳震有科技股份有限公司 | Inter-core communication method based on SPI (Serial peripheral interface), terminal and storage medium |
| CN111625281A (en) * | 2020-05-25 | 2020-09-04 | 上海载德信息科技股份有限公司 | Data processing method, device, equipment and storage medium |
| CN111984581A (en) * | 2020-08-14 | 2020-11-24 | 广州邦讯信息系统有限公司 | Linux-based SPI bus master-slave device communication system, method and device |
| CN112416832A (en) * | 2020-11-06 | 2021-02-26 | 光华临港工程应用技术研发(上海)有限公司 | Communication system based on MIPS framework processor |
| CN113176966A (en) * | 2021-03-12 | 2021-07-27 | 青芯半导体科技(上海)有限公司 | System and method for checking validity of SPI (Serial peripheral interface) received data |
| CN114338260A (en) * | 2020-09-28 | 2022-04-12 | 宝能汽车集团有限公司 | Display control system and method of vehicle digital instrument and vehicle |
| CN115543898A (en) * | 2022-09-26 | 2022-12-30 | 南京国电南自维美德自动化有限公司 | Communication bus expansion method and device |
| CN115834739A (en) * | 2023-02-16 | 2023-03-21 | 石家庄科林电气股份有限公司 | Receiving method of indefinite-length data frame in platform area intelligent convergence terminal SPI communication |
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| CN110765058A (en) * | 2019-09-12 | 2020-02-07 | 深圳震有科技股份有限公司 | Method, system, equipment and medium for realizing SPI slave function by GPIO |
| CN110531686A (en) * | 2019-09-28 | 2019-12-03 | 徐州可云智能科技有限公司 | A kind of devices and methods therefor based on single master mostly from the more hosts of protocol realization |
| CN111427815A (en) * | 2020-03-05 | 2020-07-17 | 深圳震有科技股份有限公司 | Inter-core communication method based on SPI (Serial peripheral interface), terminal and storage medium |
| CN111625281A (en) * | 2020-05-25 | 2020-09-04 | 上海载德信息科技股份有限公司 | Data processing method, device, equipment and storage medium |
| CN111984581A (en) * | 2020-08-14 | 2020-11-24 | 广州邦讯信息系统有限公司 | Linux-based SPI bus master-slave device communication system, method and device |
| CN111984581B (en) * | 2020-08-14 | 2022-05-10 | 广州邦讯信息系统有限公司 | Linux-based SPI bus master-slave device communication system, method and device |
| CN114338260A (en) * | 2020-09-28 | 2022-04-12 | 宝能汽车集团有限公司 | Display control system and method of vehicle digital instrument and vehicle |
| CN112416832A (en) * | 2020-11-06 | 2021-02-26 | 光华临港工程应用技术研发(上海)有限公司 | Communication system based on MIPS framework processor |
| CN113176966A (en) * | 2021-03-12 | 2021-07-27 | 青芯半导体科技(上海)有限公司 | System and method for checking validity of SPI (Serial peripheral interface) received data |
| CN115543898A (en) * | 2022-09-26 | 2022-12-30 | 南京国电南自维美德自动化有限公司 | Communication bus expansion method and device |
| CN115834739A (en) * | 2023-02-16 | 2023-03-21 | 石家庄科林电气股份有限公司 | Receiving method of indefinite-length data frame in platform area intelligent convergence terminal SPI communication |
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