CN111427815A - Inter-core communication method based on SPI (Serial peripheral interface), terminal and storage medium - Google Patents
Inter-core communication method based on SPI (Serial peripheral interface), terminal and storage medium Download PDFInfo
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- CN111427815A CN111427815A CN202010147463.6A CN202010147463A CN111427815A CN 111427815 A CN111427815 A CN 111427815A CN 202010147463 A CN202010147463 A CN 202010147463A CN 111427815 A CN111427815 A CN 111427815A
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/14—Handling requests for interconnection or transfer
- G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
- G06F13/24—Handling requests for interconnection or transfer for access to input/output bus using interrupt
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F15/00—Digital computers in general; Data processing equipment in general
- G06F15/16—Combinations of two or more digital computers each having at least an arithmetic unit, a program unit and a register, e.g. for a simultaneous processing of several programs
- G06F15/163—Interprocessor communication
- G06F15/17—Interprocessor communication using an input/output type connection, e.g. channel, I/O port
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F15/00—Digital computers in general; Data processing equipment in general
- G06F15/16—Combinations of two or more digital computers each having at least an arithmetic unit, a program unit and a register, e.g. for a simultaneous processing of several programs
- G06F15/177—Initialisation or configuration control
Abstract
The invention discloses an inter-core communication method, a terminal and a storage medium based on an SPI (serial peripheral interface), wherein the method comprises the following steps: setting an SPI (serial peripheral interface) of a CPU (Central processing Unit) into a loopback mode, and setting the destination of an interrupt signal of the SPI as a slave core according to a communication direction; the main core sends data to the slave core through the SPI interface in the loopback mode, and the SPI interrupt slave core is configured; the slave core responds to the interrupt configured by the master core and reads data sent by the master core. The invention sets the SPI interface of the CPU to be a loop-back mode, and interrupts the communication between the kernels by using the interrupt signal, thereby avoiding the process of copying the memory in the inter-kernel communication and meeting the requirement of the inter-kernel communication of a high-performance system.
Description
Technical Field
The invention relates to the application field of an embedded system, in particular to an inter-core communication method based on an SPI (serial peripheral interface), a terminal and a storage medium.
Background
In the field of embedded Multi-core systems, there are two technologies, one is AMP (Asymmetric Multi-Processing) Asymmetric multiprocessing technology, and the other is smp (symmetric Multi-Processing) symmetric multiprocessing technology; each CPU on the SMP system shares all resources of the system, including serial ports, and the SMP system is only enough for one console; and each CPU on the AMP system has independent running codes, the task scheduling is independent, the access to the whole system resource is mutually exclusive, and even the Operating System (OS) running on each CPU is completely different.
Two inner cores on a hardware CPU run own operating system and application software respectively; although the two cores run independent systems, there is a communication requirement between the two cores, which is inter-core communication.
To achieve inter-core communication, the following two methods are generally used:
as shown in fig. 1, in a first method, a master core and a slave core share a memory, that is, a piece of memory is allocated to the master core and the slave core, and both the master core and the slave core can access the memory, where one core writes data to be communicated into the memory, and the other core reads the data from the memory.
As shown in fig. 2, in the second method, inter-core communication is performed by using a network protocol, the master core and the slave core perform mutual communication as independent network nodes, both the master core system and the slave core system can create a socket for communication, if one party needs to send a message to another party, data needs to be written into the socket of the other party, and the other party can receive the sent message through the socket of the other party.
The above two communication methods both have the problem of memory copy for several times, and the master core system and the slave core system both need to perform memory copy, and both of these two communication methods are not suitable for a system with high performance requirement.
Accordingly, the prior art is yet to be improved and developed.
Disclosure of Invention
The technical problem to be solved by the present invention is to provide an inter-core communication method based on an SPI interface, a terminal, and a storage medium, aiming at the problem in the prior art that there are several times of memory copies in the communication between a master core and a slave core.
The technical scheme adopted by the invention for solving the technical problem is as follows:
in a first aspect, the present invention provides an inter-core communication method based on an SPI interface, wherein the inter-core communication method based on the SPI interface includes the following steps:
setting an SPI (serial peripheral interface) of a CPU (Central processing Unit) into a loopback mode, and setting the destination of an interrupt signal of the SPI as a slave core according to a communication direction;
the main core sends data to the slave core through the SPI interface in the loopback mode, and the SPI interrupt slave core is configured;
the slave core responds to the interrupt configured by the master core and reads data sent by the master core.
Preferably, the SPI interface-based inter-core communication method further includes:
when the interrupt is led to the slave core through the SPI interface, the master core sends data to the SPI interface, the slave core is interrupted by a receiving event of the SPI interface, the slave core reads the data sent by the master core from the receiving register, and the communication is successful.
Preferably, the SPI interface-based inter-core communication method further includes:
when the interrupt is led to the main core through the SPI interface, the auxiliary core sends data to the SPI interface, the main core is interrupted by a receiving event of the SPI interface, the main core reads the data sent from the auxiliary core from the receiving register, and the communication is successful.
Preferably, the inter-core communication method based on the SPI interface, wherein the SPI interface of the CPU is set to a loopback mode, and a destination of an interrupt signal of the SPI interface is set to a slave core according to a communication direction, specifically includes:
setting an SPI interface as a loopback mode, and setting a bit of a designated register as a fixed value;
and determining the communication direction between the inner cores in the CPU, and setting the destination of the interrupt signal of the SPI interface as a slave core according to the communication destination address.
Preferably, the SPI interface-based inter-core communication method further includes:
the SPI interface interrupts the response function on the slave core and stores the received character into the cache;
when the whole cached data meets a preset condition, acquiring effective data sent to a slave core by a master core;
and the slave core sends the valid data to the corresponding module for processing.
Preferably, the SPI interface-based inter-core communication method further includes:
setting the SPI interface as a loop-back mode, and setting a bit in a designated register to be equal to a fixed value;
setting the destination of an interrupt signal of the SPI interface as a slave core;
writing data sent from the slave core to the master core into a register;
the SPI interface sends and loops data back to its own receive buffer.
Preferably, the SPI interface-based inter-core communication method further includes:
the SPI interface interrupts the response function on the main core and stores the received characters into a cache;
when the whole cached data meets a preset condition, obtaining effective data sent from the slave core to the master core;
and the main core sends the valid data to a corresponding module for processing.
Preferably, the inter-core communication method based on the SPI interface is described, wherein the fixed value is 1.
In a second aspect, the present invention further provides a terminal, which includes a processor, and a memory connected to the processor, where the memory stores an SPI interface-based inter-core communication program, and the SPI interface-based inter-core communication program is executed by the processor to implement the operation of the SPI interface-based inter-core communication method according to the first aspect.
In a third aspect, the present invention further provides a storage medium, where the storage medium stores an SPI interface based inter-core communication program, and when the SPI interface based inter-core communication program is executed by a processor, the SPI interface based inter-core communication method according to the first aspect is implemented.
The invention adopts the technical scheme and has the following effects:
the method comprises the steps that an SPI (serial peripheral interface) of a CPU (central processing unit) is set to be in a loopback mode, and the destination of an interrupt signal of the SPI is set to be a slave core according to the communication direction; the main core sends data to the slave core through the SPI interface in the loopback mode, and the SPI interrupt slave core is configured; the slave core responds to the interrupt configured by the master core and reads data sent by the master core. The invention sets the SPI interface of the CPU to be a loop-back mode, and interrupts the communication between the kernels by using the interrupt signal, thereby avoiding the process of copying the memory in the inter-kernel communication and meeting the requirement of the inter-kernel communication of a high-performance system.
Drawings
FIG. 1 is a schematic diagram illustrating a conventional kernel communication method for sharing a memory;
FIG. 2 is a communication diagram illustrating a virtual network port constructed in a conventional kernel communication manner;
FIG. 3 is a flowchart of an inter-core communication method based on an SPI interface according to an embodiment of the present invention;
FIG. 4 is a communication diagram illustrating a master core sending data to a slave core in an embodiment of the present invention;
FIG. 5 is a communication diagram illustrating the sending of data from a core to a master core in accordance with an embodiment of the present invention;
FIG. 6 is a flowchart illustrating a master core sending data to a slave core in a preferred embodiment of the SPI based inter-core communication method according to an embodiment of the present invention;
fig. 7 is a flowchart illustrating a process of receiving SPI data sent from a master core in a preferred embodiment of an SPI interface-based inter-core communication method according to an embodiment of the present invention;
FIG. 8 is a flowchart illustrating an exemplary method for inter-core communication based on SPI interface according to an embodiment of the present invention;
fig. 9 is a flowchart illustrating a process of receiving SPI data transmitted from a core by a master core in a preferred embodiment of the SPI interface-based inter-core communication method according to the present invention;
fig. 10 is a functional schematic diagram of a terminal in an embodiment of the present invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention clearer and clearer, the present invention is further described in detail below with reference to the accompanying drawings and examples. It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention.
Example one
To solve the problem of the conventional system kernel communication method, this embodiment provides an inter-kernel communication method based on an SPI interface to avoid the process of memory copy in inter-kernel communication, thereby meeting the inter-kernel communication requirement of a high-performance system.
As shown in fig. 3, in an implementation manner of this embodiment, the inter-core communication method based on the SPI interface includes the following steps:
step S10, setting the SPI interface of the CPU to be a loop-back mode, and setting the interrupt signal destination of the SPI interface to be a slave core according to the communication direction;
step S20, the main core sends data to the slave core through the SPI interface of the loop mode, and configures the SPI to interrupt the slave core;
in step S30, the slave core responds to the interrupt configured by the master core and reads the data sent by the master core.
Specifically, the invention utilizes one of the SPI interfaces of the CPU to set the SPI interface as a loopback mode (loopback), and the data sent by the SPI is received by the SPI; after receiving data, the SPI triggers an interrupt to the CPU, and in a dual core system, the interrupt signal may be configured to be sent to the master core or the slave core.
The dual-core communication principle is as follows: the master core sends data through a loopback SPI interface, then the SPI is configured to interrupt the slave core, and then the slave core responds to the interrupt and reads the data sent by the master core. Since the interruption can only be given to one CPU core at a time, the communication is in Half-Duplex mode, where Half-Duplex (Half Duplex) data transmission indicates that data can be transmitted in both directions of a signal carrier, but not simultaneously; for example, using a technique with half-duplex transmission over a local area network, a workstation can send data on the line and then immediately receive data on the line, the data coming from the direction in which the data was just transmitted; like full duplex transmission, half duplex contains a bi-directional line (a line can carry data in both directions).
After setting the L OOP bit in the spmode (espi mode register) register (i.e., the designated register), the data written into the register spitf (espi transmit FIFO access register) can be read from the spirf (espi receive FIFO access register) register.
Further, as shown in fig. 4, the interrupt of the SPI1 is directed to the slave core, the CPU of the master core sends data to the SPI1, the slave core is immediately interrupted by the reception event of the SPI1 due to the internal loop of the SPI, the slave core reads the data sent by the master core from the reception register, and the communication is successful.
Further, as shown in fig. 5, the interrupt of the SPI1 is directed to the master core, the slave core CPU sends data to the SPI1, and since the SPI loops back internally, the master core is immediately interrupted by the reception event of the SPI1, and the master core reads the data sent from the slave core from the reception register, so that the communication is successful.
Further, as shown in fig. 6, the flow of the master core sending data to the slave core:
the method comprises the steps of firstly setting SPI1 as a loopback mode, setting a bit L OOP in an SPMODE register to be equal to 1, setting an interrupt signal IRQ0 destination of a serial port SPI1 as a slave core, firstly increasing start signals 0xaa and 0xbb of data, writing the start signals into a register data sending register SPITF, then writing the data into the SPITF register, finally increasing end signals 0xbb and 0xaa of the data, writing the end signals into the register SPITF, sending the data into a receiving buffer area of the SPI1 hardware, and sending the data back to the receiving buffer area of the SPI1 hardware successfully after the sending is finished.
Further, as shown in fig. 7, the processing flow of receiving the SPI data sent by the master core from the slave core is as follows:
interrupt response function of SPI1 on the slave core; storing the received characters in a cache; when the data of the whole cache meets 0xaa,0xbb, 0xbb and 0xaa, the data of the ellipsis part is valid data sent to the slave core by the master core; sending the valid data to a corresponding module for processing; and successfully receiving and processing the data of the slave core.
Further, as shown in fig. 8, the flow of sending data from the slave core to the master core:
the method comprises the steps of firstly setting SPI1 as a loopback mode, setting a bit L OOP in an SPMODE register to be equal to 1, setting an interrupt signal IRQ0 destination of a serial port SPI1 as a slave core, firstly increasing start signals 0xaa and 0xbb of data, writing the start signals into a register data sending register SPITF, then writing the data into the SPITF register, finally increasing end signals 0xbb and 0xaa of the data, writing the end signals into the register SPITF, sending the data into a receiving buffer area of the SPI1 hardware, and sending the data back to the receiving buffer area of the SPI1 hardware successfully after the sending is finished.
Further, as shown in fig. 9, the processing flow of the master core receiving the SPI data sent from the core is as follows:
interrupt response function of SPI1 on the master core; storing the received characters in a cache; when the data of the whole cache meets 0xaa,0xbb, 0xbb and 0xaa, the data of the ellipsis part is valid data sent from the core to the main core; sending the valid data to a corresponding module for processing; and successfully receiving and processing the data of the slave core.
In this embodiment, the inter-core communication method based on the SPI interface is applied to a terminal, which includes but is not limited to a mobile terminal and a computer; the system used by the terminal is an AMP embedded multi-core system.
In this embodiment, the SPI interface of the CPU is set to the loopback mode, thereby avoiding the process of memory copy in inter-core communication, and meeting the inter-core communication requirement of the high-performance system.
Example two
Further, as shown in fig. 10, the present invention also provides a terminal based on the inter-core communication method of the SPI interface, and the terminal includes a processor 10, a memory 20, and a display 30. Fig. 10 shows only some of the components of the terminal, but it is to be understood that not all of the shown components are required to be implemented, and that more or fewer components may be implemented instead.
The memory 20 may in some embodiments be an internal storage unit of the terminal, such as a hard disk or a memory of the terminal. The memory 20 may also be an external storage device of the terminal in other embodiments, such as a plug-in hard disk, a Smart Media Card (SMC), a Secure Digital (SD) Card, a Flash memory Card (Flash Card), and the like, which are provided on the terminal. Further, the memory 20 may also include both an internal storage unit and an external storage device of the terminal. The memory 20 is used for storing application software installed in the terminal and various types of data, such as program codes of the installation terminal. The memory 20 may also be used to temporarily store data that has been output or is to be output. In an embodiment, the memory 20 stores an SPI interface based inter-core communication program 40, and the SPI interface based inter-core communication program 40 can be executed by the processor 10, so as to implement the SPI interface based inter-core communication method in the present application.
The processor 10 may be a Central Processing Unit (CPU), a microprocessor or other data Processing chip in some embodiments, and is configured to run program codes stored in the memory 20 or process data, such as executing the SPI interface-based inter-core communication method.
The display 30 may in some embodiments be an L ED display, a liquid crystal display, a touch-sensitive liquid crystal display, an O L ED (Organic light-Emitting Diode) touch-sensitive display, etc. the display 30 is used for displaying information at the terminal and for displaying a visual user interface the components 10-30 of the terminal communicate with each other over a system bus.
In one embodiment, when the processor 10 executes the SPI interface based inter-core communication program 40 in the memory 20, the following steps are implemented:
setting an SPI (serial peripheral interface) of a CPU (Central processing Unit) into a loopback mode, and setting the destination of an interrupt signal of the SPI as a slave core according to a communication direction;
the main core sends data to the slave core through the SPI interface in the loopback mode, and the SPI interrupt slave core is configured;
the slave core responds to the interrupt configured by the master core and reads data sent by the master core.
The inter-core communication method based on the SPI interface further comprises the following steps:
when the interrupt is led to the slave core through the SPI interface, the master core sends data to the SPI interface, the slave core is interrupted by a receiving event of the SPI interface, the slave core reads the data sent by the master core from the receiving register, and the communication is successful.
The inter-core communication method based on the SPI interface further comprises the following steps:
when the interrupt is led to the main core through the SPI interface, the auxiliary core sends data to the SPI interface, the main core is interrupted by a receiving event of the SPI interface, the main core reads the data sent from the auxiliary core from the receiving register, and the communication is successful.
The setting of the SPI interface of the CPU to the loopback mode and the setting of the destination of the interrupt signal of the SPI interface according to the communication direction as the slave core specifically include:
setting an SPI interface as a loopback mode, and setting a bit of a designated register as a fixed value;
and determining the communication direction between the inner cores in the CPU, and setting the destination of the interrupt signal of the SPI interface as a slave core according to the communication destination address.
The inter-core communication method based on the SPI interface further comprises the following steps:
the SPI interface interrupts the response function on the slave core and stores the received character into the cache;
when the whole cached data meets a preset condition, acquiring effective data sent to a slave core by a master core;
and the slave core sends the valid data to the corresponding module for processing.
The inter-core communication method based on the SPI interface further comprises the following steps:
setting the SPI interface as a loop-back mode, and setting a bit in a designated register to be equal to a fixed value;
setting the destination of an interrupt signal of the SPI interface as a slave core;
writing data sent from the slave core to the master core into a register;
the SPI interface sends and loops data back to its own receive buffer.
The inter-core communication method based on the SPI interface further comprises the following steps:
the SPI interface interrupts the response function on the main core and stores the received characters into a cache;
when the whole cached data meets a preset condition, obtaining effective data sent from the slave core to the master core;
and the main core sends the valid data to a corresponding module for processing.
The fixed value is 1.
EXAMPLE III
The embodiment provides a storage medium, wherein the storage medium stores an SPI interface based inter-core communication program, and the SPI interface based inter-core communication program is used for implementing the operation of the SPI interface based inter-core communication method according to the first embodiment when being executed by a processor; as described above.
In summary, the present invention provides an inter-core communication method, a terminal and a storage medium based on an SPI interface, the method including: setting an SPI (serial peripheral interface) of a CPU (Central processing Unit) into a loopback mode, and setting the destination of an interrupt signal of the SPI as a slave core according to a communication direction; the main core sends data to the slave core through the SPI interface in the loopback mode, and the SPI interrupt slave core is configured; the slave core responds to the interrupt configured by the master core and reads data sent by the master core. The invention sets the SPI interface of the CPU to be a loop-back mode, and interrupts the communication between the kernels by using the interrupt signal, thereby avoiding the process of copying the memory in the inter-kernel communication and meeting the requirement of the inter-kernel communication of a high-performance system.
Of course, it will be understood by those skilled in the art that all or part of the processes of the methods of the above embodiments may be implemented by a computer program instructing relevant hardware (such as a processor, a controller, etc.), and the program may be stored in a computer readable storage medium, and when executed, the program may include the processes of the above method embodiments. The storage medium may be a memory, a magnetic disk, an optical disk, etc.
It is to be understood that the invention is not limited to the examples described above, but that modifications and variations may be effected thereto by those of ordinary skill in the art in light of the foregoing description, and that all such modifications and variations are intended to be within the scope of the invention as defined by the appended claims.
Claims (10)
1. An inter-core communication method based on an SPI (serial peripheral interface) is characterized by comprising the following steps of:
setting an SPI (serial peripheral interface) of a CPU (Central processing Unit) into a loopback mode, and setting the destination of an interrupt signal of the SPI as a slave core according to a communication direction;
the main core sends data to the slave core through the SPI interface in the loopback mode, and the SPI interrupt slave core is configured;
the slave core responds to the interrupt configured by the master core and reads data sent by the master core.
2. The SPI interface based inter-core communication method according to claim 1, wherein the SPI interface based inter-core communication method further comprises:
when the interrupt is led to the slave core through the SPI interface, the master core sends data to the SPI interface, the slave core is interrupted by a receiving event of the SPI interface, the slave core reads the data sent by the master core from the receiving register, and the communication is successful.
3. The SPI interface based inter-core communication method according to claim 1, wherein the SPI interface based inter-core communication method further comprises:
when the interrupt is led to the main core through the SPI interface, the auxiliary core sends data to the SPI interface, the main core is interrupted by a receiving event of the SPI interface, the main core reads the data sent from the auxiliary core from the receiving register, and the communication is successful.
4. The SPI interface-based inter-core communication method according to claim 1, wherein the setting of the SPI interface of the CPU to the loopback mode and the setting of the destination of the interrupt signal of the SPI interface according to the communication direction is a slave core specifically comprises:
setting an SPI interface as a loopback mode, and setting a bit of a designated register as a fixed value;
and determining the communication direction between the inner cores in the CPU, and setting the destination of the interrupt signal of the SPI interface as a slave core according to the communication destination address.
5. The SPI interface based inter-core communication method according to claim 1, wherein the SPI interface based inter-core communication method further comprises:
the SPI interface interrupts the response function on the slave core and stores the received character into the cache;
when the whole cached data meets a preset condition, acquiring effective data sent to a slave core by a master core;
and the slave core sends the valid data to the corresponding module for processing.
6. The SPI interface based inter-core communication method according to claim 1, wherein the SPI interface based inter-core communication method further comprises:
setting the SPI interface as a loop-back mode, and setting a bit in a designated register to be equal to a fixed value;
setting the destination of an interrupt signal of the SPI interface as a slave core;
writing data sent from the slave core to the master core into a register;
the SPI interface sends and loops data back to its own receive buffer.
7. The SPI interface based inter-core communication method according to claim 1, wherein the SPI interface based inter-core communication method further comprises:
the SPI interface interrupts the response function on the main core and stores the received characters into a cache;
when the whole cached data meets a preset condition, obtaining effective data sent from the slave core to the master core;
and the main core sends the valid data to a corresponding module for processing.
8. The SPI-interface-based inter-core communication method of claim 4 or 6, wherein the fixed value is 1.
9. A terminal, comprising a processor, and a memory connected to the processor, wherein the memory stores an SPI interface based inter-core communication program, and the SPI interface based inter-core communication program is executed by the processor to implement the operation of the SPI interface based inter-core communication method according to any one of claims 1 to 8.
10. A storage medium storing an SPI interface-based inter-core communication program, which when executed by a processor, is configured to implement the operation of the SPI interface-based inter-core communication method according to any one of claims 1 to 8.
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| CN112000608A (en) * | 2020-09-02 | 2020-11-27 | 展讯通信（上海）有限公司 | System-level chip, inter-core communication method thereof and intelligent wearable device |
| CN112000608B (en) * | 2020-09-02 | 2021-10-01 | 展讯通信（上海）有限公司 | System-level chip, inter-core communication method thereof and intelligent wearable device |
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