CN113742269B

CN113742269B - Data transmission method, processing device and medium for EPA device

Info

Publication number: CN113742269B
Application number: CN202111291245.0A
Authority: CN
Inventors: 陈建飞; 张豪敏; 王迎; 罗丁元
Original assignee: Zhejiang Guoli Xin'an Technology Co ltd
Current assignee: Zhejiang Guoli Xin'an Technology Co ltd
Priority date: 2021-11-03
Filing date: 2021-11-03
Publication date: 2022-02-22
Anticipated expiration: 2041-11-03
Also published as: CN113742269A

Abstract

The invention provides a data transmission method, a processing device and a computer readable storage medium for an EPA device. The EPA device is connected to a host via the PCIe bus. The data transmission method includes, at a host: during driver initialization of a host, allocating a receive buffer in a memory and determining a first PCIe bus address corresponding to the receive buffer; allocating a transmit buffer in the memory and determining a second PCIe bus address corresponding to the transmit buffer; reading device data from the EPA device from a receive buffer before the driver performs the drive release, wherein the device data is written to the receive buffer by the EPA device based on the first PCIe bus address; and writing host data to be sent to the EPA device to the send buffer to enable the EPA device to read the host data from the send buffer based on the second PCIe bus address.

Description

Data transmission method, processing device and medium for EPA device

Technical Field

The present invention relates generally to the field of communications, and more particularly, to a data transmission method, a processing device, and a computer-readable storage medium for an EPA device.

Background

At present, products based on EPA (Ethernet for Plant Automation, industrial Ethernet) protocol standards are more and more abundant, and some products have been used in the fields of industrial production, vehicle control, and the like. An EPA system is composed of a plurality of EPA devices which are connected through an EPA bus. The EPA bus is a real-time Ethernet bus realized based on an Ethernet physical layer, and has the characteristics of strong real-time performance and fixed transmission delay. The EPA device may be mounted on a computer system as an external communication device to a computer device (also referred to herein as a host).

Data transfers between the EPA device and the computer device may use the PCIe bus. PCIe (Peripheral Component Interconnect express) is a high-speed serial computer expansion bus standard, originally named "3 GIO", and proposed by intel in 2001, and is intended to replace the old PCI (Peripheral Component Interconnect), PCI-x (Peripheral Component Interconnect extended), and AGP (Accelerated Graphics Port) bus standards. PCIe bus can provide high-speed serial point-to-point double-channel high-bandwidth transmission, connected devices are distributed with independent channel bandwidth and do not share bus bandwidth, and the functions of active power management, error reporting, end-to-end reliable transmission, hot plug, quality of service (QOS) and the like are mainly supported.

Using conventional PCIe interface design methods, data transfer from the EPA device to the host (also referred to herein as device data) and data transfer from the host to the EPA device (also referred to herein as host data) need to go through a complex process.

For example, for device data, when an EPA device is to send an EPA message containing device data, it writes the length of this message in a predefined length register, and then sends an interrupt instruction to the host to notify the host that a new EPA message is coming; after the host receives the interrupt instruction, the driver reads the length of the EPA message from the length register, applies for a memory space to the operating system according to the required length, and maps the allocated memory space to obtain the PCIe bus address of the memory space; the driver of the host then writes this PCIe bus address into a defined register to inform the EPA device and writes a start command to the control register of the EPA device. After receiving the start command, the EPA device packages the stored EPA Packet into a write memory TLP (Transaction Layer Packet) conforming to the PCIe protocol. After the sending of the EPA packet is completed, the EPA device sends an interrupt instruction to the host again, notifying the driver that the TLP sending is completed and has been stored in the allocated memory space. When the user program module needs to process the TLP, a driver read function may be called to copy the TLP from the kernel mode to the user mode, and the memory space in the kernel mode is released.

For another example, for host data, when the host needs to send host data to the EPA device, a driver of the host applies for allocation to the kernel to obtain a buffer, then maps the buffer to obtain a corresponding PCIe bus address, writes the PCIe bus address to a register corresponding to a PCIe interface configuration space of the EPA device, then starts a PCIe interface DMA (Direct Memory Access) engine on the EPA device, initiates a read request for the PCIe bus address by the EPA device, and then returns a completion message by the host, thereby completing transmission of the host data.

It can be seen that the allocation, writing, interrupt notification, etc. from the memory space, for either device data or host data, requires a complex interaction flow, and thus the data transfer latency between the EPA device and the host is inevitably high.

On the other hand, the EPA bus transmission has strong real-time performance and fixed transmission delay, so the high delay between the EPA device and the host causes the whole transmission delay of the device data and the host data to be higher, and does not meet the high real-time requirement of the EPA protocol.

Disclosure of Invention

In view of the above problems, the present invention provides a data transmission method for an EPA device, which pre-allocates a buffer for data transmission between the EPA device and a host at a driver initialization stage of the host, and caches device data and host data using the allocated buffer during a lifetime of the driver, thereby avoiding a complex interaction process between the EPA device and the host every time data is received and transmitted, increasing a data transmission speed, and reducing a data transmission delay.

According to an aspect of the present invention, there is provided a data transmission method for an EPA device. The EPA device is connected with a host through a PCIe bus. The data transmission method includes, at the host: during a driver initialization process of the host, allocating a receive buffer in a memory and determining a first PCIe bus address corresponding to the receive buffer; allocating a transmit buffer in the memory and determining a second PCIe bus address corresponding to the transmit buffer; reading device data from the EPA device from the receive buffer before the driver performs a drive release, wherein the device data is written to the receive buffer by the EPA device based on the first PCIe bus address; and writing host data to be sent to the EPA device to the send buffer to enable the EPA device to read the host data from the send buffer based on the second PCIe bus address.

In some embodiments, the method further comprises: registering an interrupt handling function in an operating system during initialization of a driver of the host; and receiving a notification of the interrupt handling function, the notification notifying a drive of the host that the device data has been written to the receive buffer.

In some embodiments, the method further comprises: the driver writes the first PCIe bus address and the second PCIe bus address into a PCIe interface configuration space of the EPA device through an input output interface write function.

In some embodiments, allocating a receive buffer in memory and determining a first PCIe bus address corresponding to the receive buffer comprises: allocating one or more receiving memory pages in the memory as the receiving buffer; acquiring a page structure pointer of each received memory page; and mapping the page structure pointer of each received memory page to a first PCIe bus address through a DMA mapping from the EPA device to the host.

In some embodiments, allocating a transmit buffer in the memory and determining a second PCIe bus address corresponding to the transmit buffer comprises: allocating one or more other sending memory pages in the memory as the sending buffer; acquiring a page structure pointer of each sending memory page; and mapping the page structure address of each send memory page to a second PCIe bus address through a DMA mapping, the direction of the DMA mapping being from the host to the EPA device.

In some embodiments, reading device data from the EPA device from the receive buffer comprises: receiving a notification of an interrupt handling function of an operating system after the device data is written to the receive buffer by the EPA device via a memory write request message, wherein a destination address of the memory write request message is the first PCIe bus address, valid data of the memory write request message is the device data, and a size of the device data is smaller than one memory page; and reading the device data from the receive buffer in response to receiving the notification of the interrupt handling function.

In some embodiments, the receive buffer comprises a receive memory page, and wherein reading the device data from the receive buffer in response to receiving the notification of the interrupt handling function comprises: reading the device data from the receive buffer if another device data is not received from the EPA device prior to reading the device data; and if another device data is received from the EPA device before reading the device data, reading the another device data from the receive buffer.

In some embodiments, the receive buffer comprises a plurality of receive memory pages, and wherein reading the device data from the receive buffer in response to receiving the notification of the interrupt handling function comprises: reading the device data from one of the receive memory pages in the receive buffer if another device data is not received from the EPA device prior to reading the device data; and if another device data is received from the EPA device before reading the device data, reading the device data from one receive memory page in the receive buffer and reading the another device data from another receive memory page in the receive buffer.

In some embodiments, writing host data to be sent to the EPA device to the send buffer to enable the EPA device to read the host data from the send buffer based on the second PCIe bus address comprises: copying the host data to the send buffer; writing a start flag to a PCIe interface configuration space of the EPA device; receiving a memory read request message from the EPA device, the destination address of the memory read request message being the second PCIe bus address; and sending a completion message to the EPA device, the valid data of the completion message being the host data and the size of the host data being smaller than one memory page.

In some embodiments, the transmit buffer comprises a transmit memory page, and wherein copying the host data to the transmit buffer further comprises: if another host data is received from a user program module of the host before sending the completion message, copying the another host data into the send buffer to overwrite the host data.

In some embodiments, the transmit buffer comprises a plurality of transmit memory pages, and wherein copying the host data to the transmit buffer further comprises: if another host data is received from the user program module of the host before the completion packet is sent, copying the another host data to another sending memory page in the sending buffer.

According to another aspect of the present invention, there is provided a processing apparatus comprising: a processor and a memory, the memory storing instructions executable by the processor, the processor being configured to cause the processing device to perform any of the methods described above.

According to yet another aspect of the invention, a computer-readable storage medium is provided, having stored thereon computer program code, which, when executed by a processor, performs any of the methods described above.

Drawings

The invention will be better understood and other objects, details, features and advantages thereof will become more apparent from the following description of specific embodiments of the invention given with reference to the accompanying drawings.

Fig. 1 shows a schematic diagram of an exemplary EPA device and host according to an embodiment of the present invention.

Fig. 2 illustrates a flow diagram of a data transmission method for an EPA device according to some embodiments of the present invention.

FIG. 3 illustrates a flowchart of steps for determining a first PCIe bus address in accordance with some embodiments of the invention.

FIG. 4 illustrates a flowchart of steps for determining a second PCIe bus address in accordance with some embodiments of the invention.

FIG. 5 illustrates a flow diagram of a host data transfer process according to some embodiments of the invention.

FIG. 6 illustrates a block diagram of a processing device suitable for implementing embodiments of the present invention.

Detailed Description

Preferred embodiments of the present invention will be described in more detail below with reference to the accompanying drawings. While the preferred embodiments of the present invention are shown in the drawings, it should be understood that the present invention may be embodied in various forms and should not be limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art.

In the following description, for the purposes of illustrating various inventive embodiments, certain specific details are set forth in order to provide a thorough understanding of the various inventive embodiments. One skilled in the relevant art will recognize, however, that the embodiments may be practiced without one or more of the specific details. In other instances, well-known devices, structures and techniques associated with this application may not be shown or described in detail to avoid unnecessarily obscuring the description of the embodiments.

Throughout the specification and claims, the word "comprise" and variations thereof, such as "comprises" and "comprising," are to be understood as an open, inclusive meaning, i.e., as being interpreted to mean "including, but not limited to," unless the context requires otherwise.

Reference throughout this specification to "one embodiment" or "some embodiments" means that a particular feature, structure, or characteristic described in connection with the embodiments is included in at least one embodiment. Thus, the appearances of the phrases "in one embodiment" or "in some embodiments" in various places throughout this specification are not necessarily all referring to the same embodiment. Furthermore, the particular features, structures, or characteristics may be combined in any suitable manner in one or more embodiments.

Furthermore, the terms first, second, third and the like in the description and in the claims, are used for distinguishing between various objects for clarity of description only and do not limit the size, other order and the like of the objects described therein unless otherwise specified.

Fig. 1 shows a schematic diagram of an exemplary EPA device 10 and host 20 according to an embodiment of the invention. As shown in fig. 1, EPA device 10 may include a transmit engine 12, a receive engine 14, and a PCIe interface configuration space module 16. The transmit engine 12 is used to construct a memory write request message for device data to be transmitted and to perform a write operation of the message. The receive engine 14 is configured to, upon receiving a PCIe bus address from the host, initiate a read request to the PCIe bus address to read host data from the PCIe bus address. The transmit engine 12 and the receive engine 14 may also be collectively referred to herein as a DMA engine.

The PCIe interface configuration space module 16 may include control and status registers of the transmit engine 12 and control and status registers of the receive engine 14. The control and status registers of the transmit engine 12 may include control signals for DMA start, end, etc., status information for the transmit engine 12, PCIe bus addresses corresponding to transmit buffers of the host 20, etc. The control and status registers of the receive engine 14 may include control signals for DMA start, end, etc., status information of the receive engine 14, PCIe bus addresses corresponding to receive buffers of the host 20, etc. Further, the EPA device 10 may also include a user module 18 for implementing various functions defined by the user in the EPA device 10. The user module 18 may be part of the EPA device 10 described herein or may be separate from the EPA device 10. Note that the EPA device 10 shown and described herein focuses only on the portion used to enable its communication with the host 20, and other portions are omitted. In some embodiments, the functions of the EPA device 10 described herein may be implemented on an FPGA (Field Programmable Gate Array) chip that can read configuration files from an external FLASH memory (FLASH) when powered up to program the FPGA chip to implement the functions of the EPA device 10 described herein.

Host 20 may include a drive 22 and a memory 24. Herein, during the initialization process of the drive 22, the host 20 may pre-allocate a transmit buffer and a receive buffer in the memory 24, which may be utilized during the lifetime of the driver to buffer received device data and host data to be transmitted. In addition, host 20 may also include a user program module 26 for implementing various functions defined by a user in host 10. The user program module 26 may be part of the host 20 as described herein or may be separate from the host 20.

EPA device 10 and host 20 are coupled via PCIe bus 30 to enable the transfer of device data from EPA device 10 to host 20 and the transfer of host data from host 20 to EPA device 10.

Fig. 2 shows a flow diagram of a data transmission method 200 for EPA device 10 according to some embodiments of the present invention. Method 200 may be cooperatively implemented by EPA device 10 and host 20 shown in fig. 1, for example. Before the method 200 starts, for powering on the EPA device 10 and the host 20, a BIOS (Basic Input Output System) of the host 20 may probe and enumerate devices (including the EPA device 10) on the PCIe bus 30, obtain PCIe node information of each device, and mount the information to a PCIe bus tree.

As shown in FIG. 2, during initialization of the driver 22 of the host 20, a receive buffer is allocated in the memory 24 and a first PCIe bus address corresponding to the receive buffer is determined, step 210.

FIG. 3 illustrates a flowchart of step 210 for determining a first PCIe bus address in accordance with some embodiments of the invention.

As shown in fig. 3, in sub-step 212, the host 20 allocates one or more memory pages in the memory 24 as receive buffers. For example, the driver 22 of the host 20 may call a memory allocation function (e.g., a get _ user _ page function) to allocate one or more memory pages as receive buffers. Currently, the size of a memory page is 4KB, and the starting address of the memory page is 4KB aligned. In this context, for the purpose of distinguishing from the memory pages used as transmission buffers hereinafter, the memory pages contained in the reception buffers are also referred to as reception memory pages, and the memory pages contained in the transmission buffers are referred to as transmission memory pages. However, those skilled in the art will appreciate that any memory page in the memory 24 is not itself dedicated to receiving or transmitting.

In sub-step 214, a page structure pointer for each received memory page may be obtained. For example, the driver 22 may call a memory allocation function to allocate the receive buffer, and after allocation is complete the function returns a page structure pointer for each received memory page. The page structure pointer of a memory page is used to address the memory page in the memory 24, and may also be referred to as a page address.

In sub-step 216, the page structure pointer for each received memory page is mapped to a PCIe bus address via DMA mapping. Here, in order to distinguish from the PCIe bus address to which the sending memory page is mapped, which will be described below, the PCIe bus address to which the receiving memory page is mapped is also referred to as a first PCIe bus address, and the PCIe bus address to which the sending memory page is mapped is also referred to as a second PCIe bus address. Here, the DMA mapping includes a streaming DMA mapping. In the case of streaming DMA mapping, it is necessary to indicate that the direction of the DMA mapping (i.e. the direction of the data in the DMA channel) is FROM EPA DEVICE 10 to host 20 (e.g. DMA _ FROM _ DEVICE).

In this way, during initialization of the driver 22, the driver pre-allocates a receive buffer in the memory 24 and establishes a mapping to PCIe bus addresses for the receive buffer.

The driver 22 may then write the first PCIe bus address mapped by the receive buffer (more specifically, each receive memory page of the receive buffer) to the PCIe interface configuration space module 16 of the EPA device 10 via an input output interface write function (e.g., an iowrite function). In this way, EPA device 10 may access the receive buffer based on the first PCIe bus address.

Returning to FIG. 2, also during initialization of the driver 22 of the host 20, a transmit buffer is allocated in the memory 24 and a second PCIe bus address corresponding to the transmit buffer is determined, step 220.

FIG. 4 shows a flowchart of step 220 for determining a second PCIe bus address in accordance with some embodiments of the invention.

As shown in fig. 4, in sub-step 222, the host 20 allocates another one or more memory pages (also referred to herein as transmit memory pages) in the memory 24 as a transmit buffer. For example, the driver 22 of the host 20 may call a memory allocation function (e.g., a get _ user _ page function) to allocate one or more memory pages as a send buffer.

In sub-step 224, a page structure pointer for each sent memory page may be obtained. For example, the driver 22 may call a memory allocation function to allocate the send buffers, and after allocation is complete the function returns a page structure pointer for each sent memory page.

In sub-step 226, the page structure pointer for each send memory page is mapped to a PCIe bus address (also referred to as a second PCIe bus address) through DMA mapping. Here, the DMA mapping includes a streaming DMA mapping. In the case of a streaming DMA map, it is necessary TO indicate that the direction of the DMA map (i.e., the direction of the data in the DMA channel) is from the host 20 TO the EPA DEVICE 10 (e.g., DMA _ TO _ DEVICE).

In this way, during initialization of the driver 22, the driver pre-allocates a send buffer in the memory 24 and establishes a mapping to PCIe bus addresses for the send buffer.

The driver 22 may then write the second PCIe bus address mapped by the send buffer (more specifically, each send memory page of the send buffer) to the PCIe interface configuration space module 16 of the EPA device 10 via an input output interface write function (e.g., an iowrite function). In this way, EPA device 10 may access the send buffer according to the second PCIe bus address.

Here, in order to avoid obscuring the focus of the present invention, the buffer resource allocation during initialization of the driver 22 of the host 20 is described with emphasis in the description of

steps

210 and 220 above. In fact, driver initialization is a complex process that may be triggered by the user program module 26 of the host 20 calling an initialization interface function provided by a driver, and the PCIe node of the EPA device 10 is configured by the driver software, and the driver software configures the configuration space of the PCIe node through the operating system function, including configuring the PCIe link speed, bus width, PCIe order, and the like. In addition, before performing the buffer resource allocation described in

steps

210 and 220, a device description structure needs to be established and initialized to describe the device structure of each device connected to the PCIe bus 30, and a PCIe BAR (Base Address Register) space is mapped into a kernel space of the operating system by a resource mapping function (e.g., a pci _ resource _ start, a pci _ resource _ len function) of the PCIe bus, so that a driver of the driver 22 of the host 20 can directly operate the PCIe interface configuration space module 16 of the EPA device 10 using an input output interface function (e.g., including an input output interface write function iowrite and an input output interface read function ioread).

In addition, an interrupt handling function is registered in the operating system of the host 20 as part of the initialization process of the drive 22 prior to the allocation of buffer resources during the initialization process of the drive 22 as described in

steps

210 and 220. Unlike interrupt processing in the prior art, only one interrupt is required in the present invention to inform the driver of the host 20 that device data has been written to the allocated receive buffer, as described in more detail below.

In the present invention, the above-mentioned receive buffer and transmit buffer are both valid during the lifetime of the driver, and thus, before the host 20 performs the driver release (i.e., releases the resources allocated by the driver), both the EPA device 10 and the host 20 can continuously transmit the device data and the host data using the pre-allocated transmit buffer and receive buffer without performing a complicated interrupt and resource allocation procedure before each data transmission. In addition, according to the EPA bus specification, the size of data transferred in the EPA system is smaller than one memory page, and thus such pre-allocated transmit and receive buffers can satisfy the transfer of device data and host data between EPA systems.

As shown in fig. 2, at step 230, before the driver 22 performs the drive release, the driver 22 of the host 20 reads device data from the EPA device 10 from the receive buffer to which the EPA device 10 writes based on the first PCIe bus address.

Specifically, for example, when the user module 18 of the EPA device 10 receives a new EPA message, the user module 18 may parse out from the EPA message the valid data (i.e., device data) that needs to be transmitted to the host 20, and deliver it to the sending engine 12 of the EPA device 10. The sending engine 12 may construct a memory write request message based on the device data, where a header of the message indicates that a destination address of the message is the first PCIe bus address, and the valid data is the device data. Here, the memory write request packet may be a TLP constructed according to the PCIe bus protocol and including a header, valid data, and a check portion (e.g., a Cyclic Redundancy Check (CRC)). According to the PCIe bus protocol, a TLP may be transmitted between the transaction layer at the sender (here EPA device 10) and the transaction layer at the receiver (here host 20).

The transmit engine 12 executes the memory write request message to write the device data to the receive buffer over the PCIe bus 30.

After writing the device data into the receive buffer, the transmit engine 12 may also send an interrupt notification to the host 20, for example, according to interrupt register information in the PCIe interface configuration space module 16, to indicate to the host 20 that new device data exists.

From the perspective of the host 20, after the device data is written to the receive buffer, a notification of an interrupt handling function of the operating system is received, and the device data is read from the receive buffer in response to receiving the notification of the interrupt handling function.

Here, the notification of the interrupt handling function of the operating system may be triggered by an interrupt notification sent by the sending engine 12 to the host 20 as described above, and the reading of the device data from the receive buffer may be performed by the user program module 26 of the host 20. Reading the device data from the receive buffer by the user program module 26 includes copying the data content (i.e., the device data) in the receive buffer to the user program module 26.

However, if EPA device 10 has performed another memory write request to the receive buffer of host 20 before copying the data content in the receive buffer to user program module 26 (i.e. not copied to user program module 26 in time), different operations may be performed at host 20 depending on whether the receive buffer contains one or more receive memory pages.

In some embodiments, the receive buffer comprises one receive memory page. In this case, there is only one first PCIe bus address corresponding to the receive buffer, and therefore the EPA device 10 may continue to construct and execute the memory write request message with the first PCIe bus address as the destination address to write different device data.

If the host 20 does not receive another device data from the EPA device 10 before reading the device data in the received memory page, the host 20 may read the device data directly from the receive buffer.

If host 20 receives another device data from EPA device 10 before reading the device data in the received memory page, host 20 will read the other device data from the receive buffer. That is, the device data in the reception buffer is overwritten by another device data newly written by the EPA device 10, so that the host 20 reads the newly written another device data and cannot read the overwritten device data. According to the characteristics of the EPA protocol, the data transmitted in the EPA system has higher real-time performance, so the other device data may be more real-time data, and the use of only one receiving memory page may be allowed.

In other embodiments, the receive buffer may include a plurality of receive memory pages. In this case, there are multiple first PCIe bus addresses corresponding to the receiving buffer, that is, one receiving memory page, so the EPA device 10 may construct and execute the memory write request message to write different device data by using different first PCIe bus addresses as destination addresses.

In this case, host 20 may read the device data from one of the receiving memory pages in the receive buffer, regardless of whether it received another device data from EPA device 10 before reading the device data. Host 20 may also read another device data from another receive memory page in the receive buffer if the other device data is also received from EPA device 10 before reading the device data. In this case, the EPA device 10 and the host 20 may perform the above-described operations for the other device data separately, so that the EPA device 10 can read the other device data based on the first PCIe bus address corresponding to the other received memory page. That is, independent transmission processes are respectively performed for different device data.

For host device transmission, as shown in fig. 2, at step 240, before the drive 22 performs drive release, the host 20 writes host data to be sent to the EPA device 10 to the send buffer to enable the EPA device 10 to read the host data from the send buffer based on the second PCIe bus address.

As shown in fig. 5, at sub-step 242, the host 20 (e.g., user program module 26 of host 20) copies host data to the send buffer.

In sub-step 244, the driver 22 of the host 20 writes the start flag to the PCIe interface configuration space module 16 of the EPA device 10.

The PCIe interface configuration space module 16, in response to the start flag, notifies the receive engine 14 to enable the receive engine 14 to initiate a memory read request message to the send buffer according to the second PCIe bus address. And indicating that the destination address of the message is the second PCIe bus address in the message header of the memory read request message.

In some embodiments, the send buffer includes only one send memory page whose corresponding second PCIe bus address may be written to the PCIe interface configuration space module 16 by the driver 22 after the determination in step 220. In this case, the PCIe interface configuration space module 16 initiates a memory read request message to the send buffer according to the second PCIe bus address in response to the start flag.

In other embodiments, the send buffer includes a plurality of send memory pages, and the second PCIe bus address corresponding to each send memory page may be written to the PCIe interface configuration space module 16 by the driver 22 after the determination in step 220. In this case, in sub-step 244, the drive 22 should write address information for the send memory page in which the host data is located, in addition to writing the enable flag to the PCIe interface configuration space module 16. Here, the address information may include a particular second PCIe bus address of the send memory page where the host data is located, or may include an offset of the send memory page where the host data is located relative to a head address of the send buffer. The PCIe interface configuration space module 16 responds to the start flag and the address information, and initiates a memory read request message to the send buffer with the corresponding second PCIe bus address as a destination address.

In the above embodiment, the memory read request message does not include the length of the data to be read, in which case the driver 22 will read the entire transmission memory page, which may cause waste of resources. In this regard, in some embodiments, in sub-step 244, the driver 22 of the host 20 may write the data length of the host data to the PCIe interface configuration space module 16 of the EPA device 10 in addition to the start flag. The PCIe interface configuration space module 16, in response to the start flag and the data length, initiates a memory read request message to the sending buffer according to the second PCIe bus address, where the memory read request message includes the data length of the host data. In this way, the driver 22 can read the host data of the data length only at the corresponding sending memory page in response to the memory read request message.

In sub-step 246, the driver 22 of the host 20 may receive the memory read request message from the receive engine 14 of the EPA device 10. Here, the memory read request message may be transmitted to the drive 22 via a root complex (root complex) of the host 20, for example.

In sub-step 248, the driver 22 of the host 20 sends a completion message to the EPA device 10 in response to the memory read request message. Wherein the valid data of the completion message is the host data. Here, similarly, the memory read request packet and the completion packet may be TLPs constructed according to the PCIe bus protocol, and each of the TLPs includes a packet header, valid data and a check part.

The receive engine 14 of the EPA device 10, upon receiving the completion message, may parse the completion message to extract the valid data (i.e., host data) therein. Further, the host data may also be sent to the user module 18 for processing by the EPA device 10 or further transmitted over the EPA bus to other EPA devices in the EPA system.

Similarly, if another host data is received from the user program module 26 before the data content in the send buffer is sent to the EPA device 10, different operations may be performed at the host 20 depending on whether the send buffer contains one or more send memory pages.

In some embodiments, the transmit buffer comprises one transmit memory page. In this case, if another host data is received from the user program module 26 of the host 20 before sending the completion message, the drive 22 may copy the other host data into the send buffer to overwrite the previous host data. At this point, the valid data contained in the completion message will be the other host data rather than the previous host data.

In other embodiments, the transmit buffer may include multiple transmit memory pages. In this case, if another host data is received from the user program module 26 of the host 20 before sending the completion message, the drive 22 may copy the other host data to another send memory page in the send buffer. In this case, the drive 22 may perform the operations of the above sub-steps 244 to 248 for the other host data separately, so that the EPA device 10 can read the other host data based on the second PCIe bus address corresponding to the other send memory page. That is, independent transmission processes are performed for different host data, respectively.

The data transmission method 200 for the EPA device according to the embodiment of the present invention is described above with reference to fig. 2 to 5. It will be appreciated by persons skilled in the art that the order of the various steps shown and described above is merely exemplary and is not intended to limit the scope of the present invention. For example, step 220 may be performed before, after, or simultaneously with step 210, and step 240 may be performed before, after, or simultaneously with step 230.

Fig. 6 illustrates a block diagram of a processing device 600 suitable for implementing embodiments of the present invention. Processing device 600 may be used to implement EPA device 10 or host 20 as shown in fig. 1.

As shown, the processing device 600 may include a processor 610. The processor 610 controls the operation and functions of the processing device 600. For example, in some embodiments, the processor 610 may perform various operations by way of instructions 630 stored in a memory 620 coupled thereto. The memory 620 may be of any suitable type suitable to the local technical environment and may be implemented using any suitable data storage technology, including but not limited to semiconductor-based memory devices, magnetic memory devices and systems, optical memory devices and systems. Although only one memory 620 is shown in fig. 6, those skilled in the art will appreciate that the processing device 600 may include many more physically distinct memories 620.

The processor 610 may be of any suitable type suitable to the local technical environment, and may include, but is not limited to, one or more of general purpose computers, special purpose computers, microprocessors, Digital Signal Processors (DSPs), and processor-based multi-core processor architectures. The processing device 600 may also include a plurality of processors 610. The processor 610 is coupled to a transceiver 640, and the transceiver 640 may enable receiving and transmitting information by way of a communication interface and/or other components.

When the processing device 600 performs the various functions described above, the processor 610 and the transceiver 640 may operate cooperatively under the control of instructions 630 in the memory 620 to implement the functions of the EPA device 10 or the host 20 in the methods described above with reference to fig. 2 to 5. All features described above with reference to fig. 1 to 5 apply to the processing device 600 and are not described in detail here.

The present invention may be embodied as methods, apparatus, systems, and/or computer program products. The computer program product may include a computer-readable storage medium having computer-readable program instructions embodied therein for carrying out aspects of the present invention.

In one or more exemplary designs, the functions described herein may be implemented in hardware, software, firmware, or any combination thereof. For example, if implemented in software, the functions may be stored on or transmitted over as one or more instructions or code on a computer-readable medium.

The units of the apparatus disclosed herein may be implemented using discrete hardware components, or may be integrally implemented on a single hardware component, such as a processor. For example, the various illustrative logical blocks, modules, and circuits described in connection with the invention may be implemented or performed with a general purpose processor, a Digital Signal Processor (DSP), an Application Specific Integrated Circuit (ASIC), a Field Programmable Gate Array (FPGA) or other programmable logic device, discrete gate or transistor logic, discrete hardware components, or any combination thereof designed to perform the functions described herein.

Those of skill would further appreciate that the various illustrative logical blocks, modules, circuits, and algorithm steps described in connection with the embodiments disclosed herein may be implemented as electronic hardware, computer software, or combinations of both.

The previous description of the invention is provided to enable any person skilled in the art to make or use the invention. Various modifications to the disclosure will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other variations without departing from the spirit or scope of the disclosure. Thus, the present invention is not intended to be limited to the examples and designs described herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A data transfer method for an EPA device connected to a host over a PCIe bus, the data transfer method comprising, at the host:

during a driver initialization process of the host, allocating a receive buffer in a memory and determining a first PCIe bus address corresponding to the receive buffer;

allocating a transmit buffer in the memory and determining a second PCIe bus address corresponding to the transmit buffer;

reading device data sent from the EPA device to the host from the receive buffer before the driver performs a drive release, wherein the device data is written by the EPA device to the receive buffer based on the first PCIe bus address; and

writing host data to be sent from the host to the EPA device to the send buffer to enable the EPA device to read the host data from the send buffer based on the second PCIe bus address.

2. The method of claim 1, further comprising:

registering an interrupt handling function in an operating system during initialization of a driver of the host; and

receiving a notification of the interrupt handling function, the notification notifying a drive of the host that the device data has been written to the receive buffer.

3. The method of claim 1, further comprising:

the driver writes the first PCIe bus address and the second PCIe bus address into a PCIe interface configuration space of the EPA device through an input output interface write function.

4. The method of claim 1, wherein allocating a receive buffer in memory and determining a first PCIe bus address corresponding to the receive buffer comprises:

allocating one or more receiving memory pages in the memory as the receiving buffer;

acquiring a page structure pointer of each received memory page; and

the page structure pointer for each received memory page is mapped to a first PCIe bus address by a DMA mapping from the EPA device to the host.

5. The method of claim 1, wherein allocating a transmit buffer in the memory and determining a second PCIe bus address corresponding to the transmit buffer comprises:

allocating one or more other sending memory pages in the memory as the sending buffer;

acquiring a page structure pointer of each sending memory page; and

mapping the page structure address of each send memory page to a second PCIe bus address through a DMA map directed from the host to the EPA device.

6. The method of claim 1, wherein reading device data from the EPA device from the receive buffer comprises:

receiving a notification of an interrupt handling function of an operating system after the device data is written to the receive buffer by the EPA device via a memory write request message, wherein a destination address of the memory write request message is the first PCIe bus address, valid data of the memory write request message is the device data, and a size of the device data is smaller than one memory page; and

in response to receiving the notification of the interrupt handling function, reading the device data from the receive buffer.

7. The method of claim 6, wherein the receive buffer comprises a receive memory page, and wherein reading the device data from the receive buffer in response to receiving the notification of the interrupt handling function comprises:

reading the device data from the receive buffer if another device data is not received from the EPA device prior to reading the device data; and

if another device data is received from the EPA device before reading the device data, reading the another device data from the receive buffer.

8. The method of claim 6, wherein the receive buffer comprises a plurality of receive memory pages, and wherein reading the device data from the receive buffer in response to receiving the notification of the interrupt handling function comprises:

reading the device data from one of the receive memory pages in the receive buffer if another device data is not received from the EPA device prior to reading the device data; and

if another device data is received from the EPA device before reading the device data, reading the device data from one receive memory page in the receive buffer and reading the another device data from another receive memory page in the receive buffer.

9. The method of claim 1, wherein writing host data to be sent to the EPA device to the send buffer to enable the EPA device to read the host data from the send buffer based on the second PCIe bus address comprises:

copying the host data to the send buffer;

writing a start flag to a PCIe interface configuration space of the EPA device;

receiving a memory read request message from the EPA device, the destination address of the memory read request message being the second PCIe bus address; and

and sending a completion message to the EPA device, wherein the valid data of the completion message is the host data and the size of the host data is smaller than one memory page.

10. The method of claim 9, wherein the transmit buffer comprises a transmit memory page, and wherein copying the host data to the transmit buffer further comprises:

if another host data is received from a user program module of the host before sending the completion message, copying the another host data into the send buffer to overwrite the host data.

11. The method of claim 9, wherein the transmit buffer comprises a plurality of transmit memory pages, and wherein copying the host data to the transmit buffer further comprises:

if another host data is received from the user program module of the host before the completion packet is sent, copying the another host data to another sending memory page in the sending buffer.

12. A processing device, comprising:

a processor and a memory, the memory storing instructions executable by the processor, the processor configured to cause the processing device to perform the method of any of claims 1-11.

13. A computer readable storage medium having stored thereon computer program code which, when executed by a processor, performs the method of any of claims 1 to 11.