CN112000608B - System-level chip, inter-core communication method thereof and intelligent wearable device - Google Patents

System-level chip, inter-core communication method thereof and intelligent wearable device Download PDF

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CN112000608B
CN112000608B CN202010909850.9A CN202010909850A CN112000608B CN 112000608 B CN112000608 B CN 112000608B CN 202010909850 A CN202010909850 A CN 202010909850A CN 112000608 B CN112000608 B CN 112000608B
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main control
sent
subsystem
message
address
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CN112000608A (en
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饶国明
张慧敏
陈波
肖正飞
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Spreadtrum Communications Shanghai Co Ltd
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Spreadtrum Communications Shanghai Co Ltd
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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/16—Combinations of two or more digital computers each having at least an arithmetic unit, a program unit and a register, e.g. for a simultaneous processing of several programs
    • G06F15/163—Interprocessor communication
    • G06F15/167—Interprocessor communication using a common memory, e.g. mailbox
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
    • G06F13/24—Handling requests for interconnection or transfer for access to input/output bus using interrupt
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

The invention discloses a system-level chip, a method for inter-core communication of the system-level chip and intelligent wearable equipment. The system-level chip comprises an SRAM, a main control end and a plurality of functional subsystems, wherein the main control end and the functional subsystems are connected with the SRAM through buses, and the main control end is connected with the functional subsystems through interrupt lines. The inter-core communication method in the system level chip comprises the following steps: the main control end writes a first message to be sent into a first address of the SRAM and sends a first interrupt signal to a target function subsystem, wherein the first interrupt signal carries the first address; and the target function subsystem reads the first message to be sent from the first address of the SRAM according to the first interrupt signal. The invention provides two inter-core communication methods, which can classify the message flow and the data flow transmitted between a main control end and a functional subsystem, thereby reducing the power consumption of a system-level chip.

Description

System-level chip, inter-core communication method thereof and intelligent wearable device
Technical Field
The invention relates to the technical field of chips, in particular to a System on Chip (SoC), a method for inter-core communication of the SoC and intelligent wearing equipment.
Background
In computer system architecture, the inter-core communication problem of multi-core computers is an important consideration. For a symmetric multiprocessor system, a structure adopting a time-sharing bus is a solution for supporting memory sharing and message passing. In such a shared bus architecture, multiple CPU (Central Processing Unit) cores may access the same block of main memory address space. If communication between the CPU1 and the CPU2 needs to be realized, a shared memory space can be allocated in the main memory, and when the CPU1 writes data to be communicated and then the CPU2 reads the data, an inter-core communication function can be realized.
The inter-core communication of the shared memory type is simple and easy to implement, but when a plurality of CPUs simultaneously access the shared memory, the problems of mutual exclusion access control and Cache (high-speed buffer memory) consistency exist, and a Cache writing mechanism needs to be specially designed so as to avoid the generation of dirty data.
Disclosure of Invention
The invention provides a system-level chip, a method for communication among cores of the system-level chip and intelligent wearing equipment, and aims to overcome the defect that a Cache writing mechanism needs to be specially designed when a plurality of CPUs (central processing units) simultaneously access a shared memory in the prior art.
The invention solves the technical problems through the following technical scheme:
a first aspect of the present invention provides a method for inter-core communication in a system-on-chip, where the system-on-chip includes an SRAM (Static Random-Access Memory), a main control end and a plurality of functional subsystems, where the main control end and the functional subsystems are both connected to the SRAM through a bus, and the main control end is connected to the functional subsystems through interrupt lines;
the method comprises the following steps:
the main control end writes a first message to be sent into a first address of the SRAM and sends a first interrupt signal to a target function subsystem, wherein the first interrupt signal carries the first address;
and the target function subsystem reads the first message to be sent from the first address of the SRAM according to the first interrupt signal.
Preferably, the system-on-chip further includes a DRAM (Dynamic Random Access Memory), and the main control terminal and the functional subsystem are both connected to the DRAM through a bus; the method further comprises the following steps:
the main control end writes first data to be sent into a first buffer of the DRAM;
and the target function subsystem reads the first to-be-sent data from a first buffer of the DRAM according to the first to-be-sent message, wherein the first to-be-sent message comprises the address of the first buffer.
Preferably, the method further comprises:
the target function subsystem writes a second message to be sent into a second address of the SRAM and sends a second interrupt signal to the main control terminal, wherein the second interrupt signal carries the second address;
and the main control terminal reads the second message to be sent from the second address of the SRAM according to the second interrupt signal.
Preferably, the system-on-chip further comprises a DRAM, and the main control terminal and the functional subsystem are connected with the DRAM through a bus; the method further comprises the following steps:
the target function subsystem writes second data to be sent into a second buffer of the DRAM;
and the master control terminal reads the second data to be sent from a second buffer of the DRAM according to the second message to be sent, wherein the second message to be sent comprises the address of the second buffer.
Preferably, the method further comprises: and sending the address of the message to be sent in the SRAM by utilizing a virtual channel established between the main control end and the target function subsystem.
A second aspect of the present invention provides a system-on-chip, including an SRAM, a main control end, and a plurality of functional subsystems, where the main control end and the functional subsystems are both connected to the SRAM through a bus, and the main control end is connected to the functional subsystems through interrupt lines;
the main control end is used for writing a first message to be sent into a first address of the SRAM and sending a first interrupt signal to a target function subsystem, wherein the first interrupt signal carries the first address;
the target function subsystem is used for reading the first message to be sent from the first address of the SRAM according to the first interrupt signal.
Preferably, the system-on-chip further comprises a DRAM, and the main control terminal and the functional subsystem are connected with the DRAM through a bus;
the main control end is also used for writing first data to be sent into a first buffer of the DRAM;
the target function subsystem is further configured to read the first to-be-transmitted data from a first buffer of the DRAM according to the first to-be-transmitted message, where the first to-be-transmitted message includes an address of the first buffer.
Preferably, the target function subsystem is further configured to write a second message to be sent into a second address of the SRAM, and send a second interrupt signal to the main control end, where the second interrupt signal carries the second address;
the main control terminal is further configured to read the second message to be sent from the second address of the SRAM according to the second interrupt signal.
Preferably, the system-on-chip further comprises a DRAM, and the main control terminal and the functional subsystem are connected with the DRAM through a bus;
the target function subsystem is also used for writing second data to be sent into a second buffer of the DRAM;
the main control terminal is further configured to read the second to-be-sent data from a second buffer of the DRAM according to the second to-be-sent message, where the second to-be-sent message includes an address of the second buffer.
A third aspect of the present invention provides an intelligent wearable device, comprising the system-on-chip as described in the second aspect.
The positive progress effects of the invention are as follows: the main control end writes a first message to be sent into a first address of the SRAM through the bus, and sends a first interrupt signal to the target function subsystem through the interrupt line, and the target function subsystem reads the first message to be sent from the SRAM according to the first address carried by the first interrupt signal, so that the inter-core communication between the main control end and the function subsystem in the system-level chip is realized.
Furthermore, the main control end writes the first to-be-sent data into a first buffer of the DRAM through the bus, writes the first to-be-sent message into a first address of the SRAM, and sends a first interrupt signal to the target function subsystem through the interrupt line, the target function subsystem reads the first to-be-sent message from the SRAM according to the first address carried by the first interrupt signal, and reads the first to-be-sent data from the DRAM according to the address of the first buffer included in the first to-be-sent message, so that another type of inter-core communication between the main control end and the function subsystem in the system-level chip is realized.
The two inter-core communication methods provided by the invention can realize the classification of the message flow and the data flow transmitted between the main control end and the functional subsystem, and realize the coexistence of low-delay message transmission and high-bandwidth multi-concurrent data transmission by sharing the space of the SRAM and the DRAM, thereby reducing the power consumption of a system-level chip.
Drawings
Fig. 1 is a schematic structural diagram of a system-on-chip according to embodiment 1 of the present invention.
Fig. 2 is a schematic diagram of the connection relationship between subsystems and SRAM in the system-on-chip shown in fig. 1.
Fig. 3 is a flowchart of a method for inter-core communication in a system-on-chip according to embodiment 1 of the present invention.
Fig. 4 is a schematic diagram of message transmission between a master control end and a bluetooth subsystem according to embodiment 1 of the present invention.
Fig. 5 is a schematic structural diagram of a system-on-chip according to embodiment 2 of the present invention.
Fig. 6 is a schematic diagram of the connection relationship between subsystems, SRAM, and DRAM in the system-on-chip shown in fig. 5.
Fig. 7 is a flowchart of a method for inter-core communication in a system-on-chip according to embodiment 2 of the present invention.
Detailed Description
The invention is further illustrated by the following examples, which are not intended to limit the scope of the invention.
Example 1
Fig. 1 is a schematic diagram for illustrating a system-level chip. Fig. 2 is a schematic diagram for illustrating a connection relationship between subsystems and an SRAM in the system on chip shown in fig. 1. The method for inter-core communication in a system-on-chip provided by this embodiment can be applied to the system-on-chip shown in fig. 1.
As shown in fig. 1 and 2, the system-on-chip includes an SRAM, a main control end, and a plurality of functional subsystems, where the main control end and the functional subsystems are connected to the SRAM through a bus, and the main control end is connected to the functional subsystems through interrupt lines.
The main control end and the functional subsystems both include processors, and the inter-core communication in this embodiment refers to communication between the processors in the subsystems. In a specific example, the processors in each subsystem are MCUs (Microcontroller units), which may be RISC-architecture processors such as ARM Cortex-M/R series, MIPS (Microprocessor with Interlocked Pipelined microprocessors), RISC-V, MCS8051, and the like.
In an optional implementation manner, the master control end includes a master control subsystem and a slave control subsystem. And if the main control subsystem is in the working mode, the main control subsystem responds to the interrupt signals sent by the functional subsystems, and the auxiliary control subsystem is forbidden to respond to the interrupt signals sent by the functional subsystems. And if the main control subsystem is in a sleep mode or is powered off, the auxiliary control subsystem responds to the interrupt signals sent by the functional subsystems and forbids the main control subsystem to respond to the interrupt signals sent by the functional subsystems.
In an optional implementation manner, the main control subsystem and the sub-control subsystem are connected by an interrupt line, and the main control subsystem can respond to an interrupt signal sent by the sub-control subsystem no matter the main control subsystem is in a working mode or a sleep mode.
In one specific example, the main control subsystem can complete complex multimedia system applications, can completely respond to user operations, and can even execute complex user applications. The secondary control subsystem is mainly used for AOD (Always On Display, information screen Display technology) Display when the main control subsystem is in sleep and controlling various external sensors. Therefore, the master frequency, the memory consumption and the power consumption of the MCU in the master control subsystem are higher than those of the MCU in the auxiliary control subsystem. Each functional subsystem respectively realizes independent functions, is turned on to work only when needed, and enters a dormant state when not needed, even needs to be powered off, so that the power consumption is thoroughly saved.
In this embodiment, different functional subsystems are used to implement different functions. For example, the wireless Modem subsystem comprises a wireless Modem and is used for realizing functions of answering/dialing a call, a mobile data network and the like. The wireless Modem generally comprises baseband processing, modulation and demodulation, signal amplification and filtering, equalization, and the like, and is used for wirelessly transmitting digital signals of data communication on an analog channel with limited bandwidth. The Bluetooth subsystem is used for realizing the function of wireless communication with external equipment in short distance. The Wi-Fi subsystem is used for realizing a wireless internet function. The GPS subsystem is used for realizing the functions of real-time positioning and navigation in the global range. The camera subsystem includes a camera for capturing still images or video.
As shown in fig. 3, the method for inter-core communication in a system-on-chip provided in this embodiment includes the following steps:
step S101, the main control end writes a first message to be sent into a first address of the SRAM, and sends a first interrupt signal to a target function subsystem, wherein the first interrupt signal carries the first address.
The main control end and each functional subsystem are in a point-to-point message transmission mode. The target functional subsystem in step S101 is any one of all functional subsystems.
In step S101, the main control end writes a first message to be sent into the SRAM through the bus, and sends a first interrupt signal to the target functional subsystem through the interrupt line.
And step S102, the target function subsystem reads the first message to be sent from the first address of the SRAM according to the first interrupt signal.
In step S102, the target function subsystem reads a first message to be sent written by the main control terminal from the SRAM according to the first address carried by the first interrupt signal.
In this embodiment, the master control end sends the first message to be sent to the target functional subsystem.
In an alternative embodiment, the interrupt between the main control end and the target function subsystem is bidirectional, that is, in addition to the main control end being capable of sending the first message to be sent to the target function subsystem, the target function subsystem is also capable of sending the second message to be sent to the main control end. Specifically, the method further comprises the following steps:
step S201, the target function subsystem writes a second message to be sent into a second address of the SRAM, and sends a second interrupt signal to the main control end, where the second interrupt signal carries the second address.
In step S201, the target function subsystem writes a second message to be sent into the SRAM through the bus, and sends a second interrupt signal to the main control end through the interrupt line.
Step S202, the main control terminal reads the second message to be sent from the second address of the SRAM according to the second interrupt signal.
In step S202, the main control end reads a second to-be-sent message written in the target function subsystem from the SRAM according to a second address carried by the second interrupt signal.
In an optional embodiment, the method further includes: and sending the address of the message to be sent in the SRAM by utilizing a virtual channel established between the main control end and the target function subsystem. In a specific implementation, the main control end establishes virtual channels for communicating with each functional subsystem respectively in an initialization stage, and each subsystem also needs to establish a virtual channel for communicating with the main control end in the initialization stage. In one example, the virtual Channel established between the main control end and the wireless Modem subsystem is Channel 1. And calling a sending function corresponding to the virtual Channel1 to send when the main control end needs to send a message to the wireless Modem subsystem, wherein the sending function comprises the address of the message to be sent in the SRAM. In another example, the virtual Channel established between the master control end and the bluetooth subsystem is Channel 2. When the Bluetooth subsystem needs to send a message to the main control end, the Bluetooth subsystem calls a sending function corresponding to the virtual Channel2 to send the message,
in an optional embodiment, the method further includes: and aiming at a virtual channel established between a main control end and a target function subsystem, creating a bidirectional annular queue, and transmitting the address of a message to be transmitted in the SRAM by using the bidirectional annular queue. In this embodiment, a bidirectional ring queue is created for each virtual channel to accommodate bidirectional message transmission between the host and the functional subsystem.
Fig. 4 is a schematic diagram for illustrating the transmission of messages between the master control and the bluetooth subsystem. As shown in fig. 4, the master control end is connected to the bluetooth subsystem through an interrupt line, and the bidirectional ring queue is used for transmitting an address of a message a sent by the master control end to the bluetooth subsystem in the SRAM and an address of a message B sent by the bluetooth subsystem to the master control end in the SRAM, respectively.
Because the memory capacity of the SRAM is small, the inter-core communication method in the system-on-chip provided in this embodiment is suitable for a message with small transmission capacity between the main control end and the functional subsystem.
Example 2
Fig. 5 is a schematic diagram for illustrating a structure of a system-on-chip. Fig. 6 is a schematic diagram for illustrating the connection relationship between the subsystems and the SRAM and DRAM in the system-on-chip shown in fig. 5. The method for inter-core communication in a system-on-chip provided by this embodiment can be applied to the system-on-chip shown in fig. 5.
As shown in fig. 5 and 6, the system-on-chip includes an SRAM, a DRAM, a main control terminal, and a plurality of functional subsystems, where the main control terminal and the functional subsystems are connected to the SRAM and the DRAM through buses, and the main control terminal is connected to the functional subsystems through interrupt lines.
In an optional implementation manner, the master control end includes a master control subsystem and a slave control subsystem. And if the main control subsystem is in the working mode, the main control subsystem responds to the interrupt signals sent by the functional subsystems, and the auxiliary control subsystem is forbidden to respond to the interrupt signals sent by the functional subsystems. And if the main control subsystem is in a sleep mode or is powered off, the auxiliary control subsystem responds to the interrupt signals sent by the functional subsystems and forbids the main control subsystem to respond to the interrupt signals sent by the functional subsystems.
In an optional implementation manner, the main control subsystem and the sub-control subsystem are connected by an interrupt line, and the main control subsystem can respond to an interrupt signal sent by the sub-control subsystem no matter the main control subsystem is in a working mode or a sleep mode.
In one specific example, the main control subsystem can complete complex multimedia system applications, can completely respond to user operations, and can even execute complex user applications. The secondary control subsystem is mainly used for AOD display and control of various external sensors when the main control subsystem is in a dormant state. Therefore, the master frequency, the memory consumption and the power consumption of the MCU in the master control subsystem are higher than those of the MCU in the auxiliary control subsystem. Each functional subsystem respectively realizes independent functions, is turned on to work only when needed, and enters a dormant state when not needed, even needs to be powered off, so that the power consumption is thoroughly saved.
On the basis of embodiment 1, the method for inter-core communication in a system-on-chip provided in this embodiment further includes the following steps, as shown in fig. 7:
step S701, the main control end writes the first to-be-transmitted data into the first buffer of the DRAM.
The main control end and each functional subsystem are in a point-to-point message transmission mode. The target functional subsystem in step S701 is any one of all the functional subsystems.
In order to avoid the problem of address out-of-range when a plurality of subsystems access the DRAM simultaneously, a protection mechanism of a special memory area is adopted to realize effective isolation of addresses. In an alternative embodiment, the main control end is provided with a first IOMMU (input/output memory management unit), and the first IOMMU is configured with an address range accessible by each functional subsystem in the DRAM; step S701 specifically includes: and the main control end writes first data to be transmitted into a first buffer of the DRAM according to an address interval which can be accessed by the target function subsystem in the DRAM. In this embodiment, the first IOMMU is configured to prevent the non-communicating functional subsystem from accessing the memory area shared by both communicating parties beyond the boundary.
Step S702, the main control end writes a first message to be sent into a first address of the SRAM, and sends a first interrupt signal to a target function subsystem, wherein the first message to be sent comprises the address of the first buffer, and the first interrupt signal carries the first address.
In step S702, the main control end writes a first message to be sent into the SRAM through the bus, and sends a first interrupt signal to the target functional subsystem through the interrupt line.
In an alternative embodiment, the first message to be sent includes, in addition to the address of the first buffer, other contents, such as a control instruction and the like, sent by the main control end to the target function subsystem.
Step S703, the target function subsystem reads the first message to be transmitted from the first address of the SRAM according to the first interrupt signal, and reads the first data to be transmitted from the first buffer of the DRAM according to the first message to be transmitted.
In step S703, the target function subsystem reads the first to-be-transmitted message written by the main control terminal from the SRAM according to the first address carried by the first interrupt signal, and reads the first to-be-transmitted data from the DRAM according to the address of the first buffer included in the first to-be-transmitted message.
In this embodiment, the master control end sends the first message to be sent and the first data to be sent to the target functional subsystem.
In an optional embodiment, the interrupt between the main control end and the target function subsystem is bidirectional, that is, in addition to that the main control end can send the first message to be sent and the first data to be sent to the target function subsystem, the target function subsystem can also send the second message to be sent and the second data to be sent to the main control end. Specifically, the method further comprises the following steps:
step S801, the target function subsystem writes the second data to be sent into the second buffer of the DRAM.
In an alternative embodiment, the target functional subsystem is provided with a second IOMMU, and the second IOMMU is configured with an address range accessible by the master controller in the DRAM; step S801 specifically includes: and the target function subsystem writes second data to be sent into a second buffer of the DRAM according to an address interval which can be accessed by the main control terminal in the DRAM.
Step S802, the target function subsystem writes a second message to be sent into a second address of the SRAM, and sends a second interrupt signal to the main control terminal, wherein the second message to be sent comprises the address of the second buffer, and the second interrupt signal carries the second address.
In step S802, the target function subsystem writes a second message to be sent into the SRAM through the bus, and sends a second interrupt signal to the main control terminal through the interrupt line.
In an optional embodiment, the second message to be sent includes, in addition to the address of the second buffer, other contents, such as a current state and the like, fed back to the main control end by the target function subsystem.
Step S803, the main control terminal reads the second to-be-sent message from the second address of the SRAM according to the second interrupt signal, and reads the second to-be-sent data from the second buffer of the DRAM according to the second to-be-sent message.
In step S803, the main control end reads a second to-be-sent message written by the target function subsystem from the SRAM according to a second address carried by the second interrupt signal, and reads second to-be-sent data from the DRAM according to an address of a second buffer included in the second to-be-sent message.
In this embodiment, different inter-core communication methods may be executed according to different contents transmitted between the main control end and the functional subsystem, specifically, if a message stream with a small transmission capacity is transmitted, inter-core communication is realized by sharing the SRAM, that is, the above steps S101 to 102 or steps S201 to 202 are executed; if the data stream with large transmission capacity is large, the inter-core communication is realized by sharing the SRAM and the DRAM, that is, the step 701-703 or the step 801-803 is executed.
The SRAM has the characteristics of low power consumption, high speed, small memory capacity and high price, and the DRAM has the characteristics of large memory capacity and high power consumption. In order to avoid excessive use of the high-power-consumption DRAM, the embodiment classifies the message flow and the data flow transmitted between the main control end and the functional subsystem, and realizes coexistence of low-latency message transmission and high-bandwidth and multi-concurrent data transmission by sharing the space of the SRAM and the DRAM, thereby reducing the power consumption of the system-on-chip.
Example 3
The embodiment provides a system-on-chip, which includes an SRAM, a main control end, and a plurality of functional subsystems, where the main control end and the functional subsystems are connected to the SRAM through buses, and the main control end is connected to the functional subsystems through interrupt lines.
The main control end is used for writing a first message to be sent into a first address of the SRAM and sending a first interrupt signal to a target function subsystem, wherein the first interrupt signal carries the first address;
the target function subsystem is used for reading the first message to be sent from the first address of the SRAM according to the first interrupt signal.
The main control end and the functional subsystem comprise processors. In one specific example, the processors in each subsystem are MCUs, such as RISC-architecture processors like ARM Cortex-M/R series, MIPS, RISC-V, MCS8051, and so on.
In an optional implementation manner, the master control end includes a master control subsystem and a slave control subsystem. And if the main control subsystem is in the working mode, the main control subsystem responds to the interrupt signals sent by the functional subsystems, and the auxiliary control subsystem is forbidden to respond to the interrupt signals sent by the functional subsystems. And if the main control subsystem is in a sleep mode or is powered off, the auxiliary control subsystem responds to the interrupt signals sent by the functional subsystems and forbids the main control subsystem to respond to the interrupt signals sent by the functional subsystems.
In an optional implementation manner, the main control subsystem and the sub-control subsystem are connected by an interrupt line, and the main control subsystem can respond to an interrupt signal sent by the sub-control subsystem no matter the main control subsystem is in a working mode or a sleep mode.
In one specific example, the main control subsystem can complete complex multimedia system applications, can completely respond to user operations, and can even execute complex user applications. The secondary control subsystem is mainly used for AOD display and control of various external sensors when the main control subsystem is in a dormant state. Therefore, the master frequency, the memory consumption and the power consumption of the MCU in the master control subsystem are higher than those of the MCU in the auxiliary control subsystem. Each functional subsystem respectively realizes independent functions, is turned on to work only when needed, and enters a dormant state when not needed, even needs to be powered off, so that the power consumption is thoroughly saved.
In an optional implementation manner, the system-on-chip further includes a DRAM, and the main control terminal and the functional subsystem are both connected to the DRAM through a bus.
In an optional embodiment, the master control terminal is further configured to write first data to be transmitted into a first buffer of the DRAM; the target function subsystem is further configured to read the first to-be-transmitted data from a first buffer of the DRAM according to the first to-be-transmitted message, where the first to-be-transmitted message includes an address of the first buffer.
In an optional implementation manner, the target function subsystem is further configured to write a second message to be sent into a second address of the SRAM, and send a second interrupt signal to the main control end, where the second interrupt signal carries the second address;
the main control terminal is further configured to read the second message to be sent from the second address of the SRAM according to the second interrupt signal.
In an alternative embodiment, the target functional subsystem is further configured to write second data to be sent to a second buffer of the DRAM; the main control terminal is further configured to read the second to-be-sent data from a second buffer of the DRAM according to the second to-be-sent message, where the second to-be-sent message includes an address of the second buffer.
In an optional embodiment, the system-on-chip further includes a ROM (Read-Only Memory) and a power management chip. In a specific example, the SRAM, the main control subsystem, the sub-control subsystem, and the plurality of functional subsystems are integrated into one chip, and are packaged with the DRAM, the ROM, and the power management chip by SIP, so as to obtain the system-on-chip of the present embodiment. The SIP package is an electronic device package scheme, and integrates a plurality of functional chips, including functional chips such as a processor, a memory and the like, into one package, thereby realizing a basically complete function.
In a specific example, an ePoP packaging process is first adopted, the ROM and the DRAM are stacked on a Chip integrating the SRAM, the main control subsystem, the sub-control subsystem, and all the functional subsystems, and then an FCCSP (Chip Scale Package) packaging process is adopted to integrate the ROM and the DRAM with a power management Chip, thereby obtaining a system-on-Chip of the present embodiment.
In the above example, since the SRAM is integrated with the main control subsystem, the sub-control subsystem and the plurality of functional subsystems in one chip, the SRAM may also be referred to as an on-chip SRAM, and the DRAM may also be referred to as an off-chip DRAM.
The DRAM may be LPDDR2, LPDDR3, etc. The LPDDR (low Power Double Data Rate SDRAM) is one of DDR SDRAM (Double Data Rate SDRAM) and is a communication standard established for low Power consumption memory, LPDDR2 is a second generation low Power consumption memory technology, and LPDDR3 is a third generation low Power consumption memory technology. The ROM includes but is not limited to EMMC, NAND Flash, NOR Flash and other memories.
Example 4
The embodiment provides an intelligent wearable device, which comprises a system-on-chip as described in embodiment 3.
In some optional embodiments, the smart wearable device further includes a touch screen and a plurality of sensors, wherein the touch screen and the sensors are electrically connected to the system on chip respectively. In the embodiment, the user can operate the content displayed by the intelligent wearable device through the touch screen, and the intelligent wearable device makes different responses based on different operations of the user.
In alternative embodiments, the sensor includes a heart rate sensor, an acceleration sensor, a gyroscope sensor, and the like. The secondary control subsystem in the system-on-chip is used for realizing the function of a Sensor Hub (Sensor control center), and specifically comprises the functions of controlling the sensors in real time, fusing data of different types of sensors, realizing the function which can be realized only by combining data of various sensors and the like.
In an optional implementation manner, the smart wearable device is a smart watch, such as an adult smart watch, a child smart watch, an elderly smart watch, and the like.
In some optional embodiments, the smart wearable device may further be a smart band, smart glasses, smart clothes, or the like.
While specific embodiments of the invention have been described above, it will be appreciated by those skilled in the art that this is by way of example only, and that the scope of the invention is defined by the appended claims. Various changes and modifications to these embodiments may be made by those skilled in the art without departing from the spirit and scope of the invention, and these changes and modifications are within the scope of the invention.

Claims (10)

1. The method for inter-core communication in the system-on-chip is characterized in that the system-on-chip comprises an SRAM, a main control end and a plurality of functional subsystems, wherein the main control end and the functional subsystems are connected with the SRAM through buses, and the main control end is connected with the functional subsystems through interrupt lines;
the method comprises the following steps:
the main control end writes a first message to be sent into a first address of the SRAM, and sends a first interrupt signal to a target functional subsystem through the interrupt line, wherein the first interrupt signal carries the first address, a point-to-point message transmission mode is adopted between the main control end and each functional subsystem, and the target functional subsystem is any one of all functional subsystems;
and the target function subsystem reads the first message to be sent from the first address of the SRAM according to the first interrupt signal.
2. The method of claim 1, wherein the system-on-chip further comprises a DRAM, the master control terminal and the functional subsystem are connected to the DRAM through a bus; the method further comprises the following steps:
the main control end writes first data to be sent into a first buffer of the DRAM;
and the target function subsystem reads the first to-be-sent data from a first buffer of the DRAM according to the first to-be-sent message, wherein the first to-be-sent message comprises the address of the first buffer.
3. The method of claim 1, wherein the method further comprises:
the target function subsystem writes a second message to be sent into a second address of the SRAM and sends a second interrupt signal to the main control terminal, wherein the second interrupt signal carries the second address;
and the main control terminal reads the second message to be sent from the second address of the SRAM according to the second interrupt signal.
4. The method of claim 3, wherein the system-on-chip further comprises a DRAM, the main control terminal and the functional subsystem are connected with the DRAM through a bus; the method further comprises the following steps:
the target function subsystem writes second data to be sent into a second buffer of the DRAM;
and the master control terminal reads the second data to be sent from a second buffer of the DRAM according to the second message to be sent, wherein the second message to be sent comprises the address of the second buffer.
5. The method of any one of claims 1-4, further comprising: and sending the address of the message to be sent in the SRAM by utilizing a virtual channel established between the main control end and the target function subsystem.
6. A system-on-chip is characterized by comprising an SRAM, a main control end and a plurality of functional subsystems, wherein the main control end and the functional subsystems are connected with the SRAM through buses, and the main control end is connected with the functional subsystems through interrupt lines;
the main control end is used for writing a first message to be sent into a first address of the SRAM and sending a first interrupt signal to a target functional subsystem through the interrupt line, wherein the first interrupt signal carries the first address, a point-to-point message transmission mode is adopted between the main control end and each functional subsystem, and the target functional subsystem is any one of all functional subsystems;
the target function subsystem is used for reading the first message to be sent from the first address of the SRAM according to the first interrupt signal.
7. The system-on-chip of claim 6, wherein the system-on-chip further comprises a DRAM, the main control terminal and the functional subsystem are connected to the DRAM through a bus;
the main control end is also used for writing first data to be sent into a first buffer of the DRAM;
the target function subsystem is further configured to read the first to-be-transmitted data from a first buffer of the DRAM according to the first to-be-transmitted message, where the first to-be-transmitted message includes an address of the first buffer.
8. The system-on-chip of claim 6,
the target function subsystem is further configured to write a second message to be sent into a second address of the SRAM, and send a second interrupt signal to the main control end, where the second interrupt signal carries the second address;
the main control terminal is further configured to read the second message to be sent from the second address of the SRAM according to the second interrupt signal.
9. The system-on-chip of claim 8 further comprising a DRAM, the master control and the functional subsystem each being connected to the DRAM via a bus;
the target function subsystem is also used for writing second data to be sent into a second buffer of the DRAM;
the main control terminal is further configured to read the second to-be-sent data from a second buffer of the DRAM according to the second to-be-sent message, where the second to-be-sent message includes an address of the second buffer.
10. Intelligent wearable device, comprising a system-on-chip according to any of claims 6-9.
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