CN113590520A - Control method for automatically writing data into SPI system and SPI system - Google Patents
Control method for automatically writing data into SPI system and SPI system Download PDFInfo
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Abstract
The invention discloses a control method for automatically writing data into an SPI system and the SPI system, wherein the method comprises the following steps: the SPI system starts to write the data of the data buffer area into the TX FIFO according to the enabling signal and sends the data in the TX FIFO; the SPI system determines whether to send data cache region refresh interrupt according to the relation between the total amount of written data and the capacity of the data cache region and the number of times of sending the data cache region refresh interrupt, the CPU responds to the data cache region refresh interrupt and fills the next batch of data to be sent to the data cache region, and the SPI system continues to execute the process after receiving a signal that the CPU refresh completes the interrupt; or the SPI system writes the data in the data buffer area into the TX FIFO and finishes the work after the data in the TX FIFO is sent. In the whole data writing process, the CPU only needs to respond to the data cache region with lower interrupt frequency to refresh the interrupt, thereby greatly reducing the occupancy rate of the CPU.
Description
Technical Field
The invention relates to the technical field of data transmission, in particular to a control method for automatically writing data into an SPI system and the SPI system.
Background
The SPI protocol is a widely used peripheral interface protocol, and is used for reading/writing data of Flash devices, data of gyroscope devices, data exchange between master and slave SPI chips, and the like. Different from other applications, in the process of reading/writing data of the Flash device, the corresponding data volume is very large, and the consumed hardware resources are the most.
In the existing Flash device written in a hardware mode, after a CPU responds to an interrupt bit of an SPI controller, data is written to a TX FIFO or written to the TX FIFO by operating a DMA controller, and a command to be sent and data to be written are written into the TX FIFO together. The disadvantage of this method is obvious, when the data volume to be written into the Flash device is very large, but the TX FIFO depth of the SPI controller is very limited, the CPU or dma will frequently respond to the state interruption of the SPI controller to carry out data transfer, and the efficiency of the system will be greatly lost.
Disclosure of Invention
In order to solve the problems, the invention discloses a control method for automatically writing data into an SPI system and the SPI system, wherein the data to be written into the SPI system is cached by setting a data cache region, so that in the whole data writing process, a CPU only needs to respond to the data cache region with lower interrupt frequency to refresh interrupt, and the occupancy rate of the CPU is greatly reduced. The specific technical scheme is as follows:
a control method for automatically writing data in an SPI system comprises the following steps: s1: the SPI system starts to write the data of the data buffer area into the TX FIFO according to the enable signal, records the total amount of the written data, then sends the data in the TX FIFO, and proceeds to step S2; s2: the SPI system determines whether to send out the refresh interruption of the data cache area according to the relation between the total amount of written data and the capacity of the data cache area and the number of times of sending out the refresh interruption of the data cache area, if the data cache area meets the requirement, the SPI system goes to step S3, and if the data cache area does not meet the requirement, the SPI system goes to step S4; s3: the SPI system sends out the data buffer area to refresh and interrupt, makes the CPU respond to the data buffer area to refresh and interrupt, fills the data into the data buffer area, and enters step S1 after receiving the signal that the CPU finishes refreshing and finishes interrupting; s4: and if the data in the TX FIFO is not in line with the requirement, the SPI system writes the data in the data buffer area into the TX FIFO and finishes the work after the data in the TX FIFO is sent.
Compared with the prior art, the SPI system of this scheme is in data transmission process, constantly from the data buffer area transport data to TX FIFO that will send, because the capacity of data buffer area can greatly exceed the TX FIFO degree of depth of SPI system itself, in whole data write-in process, CPU only need respond to the lower data buffer area of interrupt frequency refresh interrupt can, the occupation rate of CPU that has significantly reduced alleviates CPU's burden, improves the operating efficiency of system.
Further, before the SPI system starts to write data, the CPU divides a data buffer, fills data to be transmitted into the data buffer, and configures the SPI system enable after configuring the read data start address, the data buffer capacity, and the number of times the data buffer needs to be refreshed of the SPI system through the ahb slave module. The size of the data cache area is divided by the CPU before the SPI system starts working, the size of the data cache area can be changed according to actual conditions, and the flexibility is high.
Further, the CPU fills the data to be transmitted into the data buffer area and configures the number of times of refreshing the data buffer area of the SPI system according to the relation between the total amount of the data to be transmitted and the capacity of the data buffer area.
Further, in step S1, the control module in the SPI system turns on the ahb master module enable according to the enable signal, so that the ahb master module reads the data in the data buffer according to the data start address and then writes the data into the TX FIFO, and records the total amount of the written data.
Further, in steps S1 and S4, during the process of transmitting the data of the TX FIFO, if the remaining data in the TX FIFO is less than or equal to the set value, the TX FIFO sends a water level trigger interrupt to trigger the ahb master module to continuously write the data in the data buffer into the TX FIFO. When the residual data in the TX FIFO is at a set value, the water level trigger interrupt is sent out, so that the SPI system writes data into the TX FIFO again, and the situation that the effective data are lost due to the fact that the capacity in the TX FIFO is small, all the effective data read by the ahb master module cannot be received is prevented.
Further, the SPI system converts the data in the TX FIFO into a corresponding SPI protocol stimulus through the SPI interface module to complete transmission.
Further, in step S2, when the total amount of the read data is equal to the capacity of the data buffer, the SPI determines the relationship between the number of times of the refresh interrupt of the sent data buffer and the number of times of the refresh interrupt of the data buffer, and if the number of times of the refresh interrupt of the sent data buffer is less than the number of times of the refresh interrupt of the data buffer, step S3 is performed; if the number of times of interruption for refreshing the data cache is equal to the number of times of interruption for refreshing the data cache, the process proceeds to step 4.
Further, in step S3, after the SPI system receives the signal of the refresh completion interrupt from the CPU, the recorded ahb master module reads the total amount of data and sets the total amount of data to zero, and then the process proceeds to step S1.
The SPI system executes the control method for the SPI system to automatically write in data, the SPI system comprises two SPI controllers, a CPU and a data cache region which are connected in pairs, the SPI controllers are used for converting the data in the data cache region into excitation conforming to an SPI protocol, the CPU is used for filling the data to be written in the data cache region, and the data cache region is used for storing the data. The SPI system caches the data to be written in by the SPI system through the data cache region, so that in the whole data writing process, a CPU only needs to respond to the data cache region with lower interrupt frequency to refresh interrupt, the occupancy rate of the CPU is greatly reduced, and the operating efficiency of the system is improved.
Further, the SPI controller comprises: the control module is connected with the ahb master module and the ahb slave module and used for controlling the SPI controller to read data in the cache region; the ahb master module is connected with the control module and the TX FIFO and is used for reading data in the data buffer area and writing the data into the TX FIFO; the ahb slave module is connected with the control module, the SPI interface module, the TX FIFO and the RX FIFO and is used for configuring an internal register of the SPI system; the SPI interface module is connected with the ahb slave module, the TX FIFO and the RX FIFO and is used for converting data in the TX FIFO into corresponding SPI protocol excitation and storing data received by the SPI interface module in the RX FIFO; the TX FIFO is used for storing data to be sent; the RX FIFO is used to store accepted data.
Drawings
Fig. 1 is a flowchart of a control method for automatically writing data in the SPI system according to an embodiment of the present invention;
FIG. 2 is a diagram illustrating the effect of the SPI system automatically writing data according to an embodiment of the present invention;
fig. 3 is a schematic structural diagram of an SPI controller according to an embodiment of the present invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the present application more apparent, the present application will be described and illustrated below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the present application. All other embodiments obtained by a person of ordinary skill in the art based on the embodiments provided in the present application without any inventive step are within the scope of protection of the present application.
SPI is an abbreviation for Serial Peripheral Interface (Serial Peripheral Interface). The SPI is a high-speed, full-duplex and synchronous communication bus, only four wires are occupied on pins of a chip, the pins of the chip are saved, and meanwhile, the space is saved on the layout of a PCB, and convenience is provided. The communication principle of SPI is simple and it works in a master-slave mode, which usually has a master device and one or more slave devices, requiring at least 4 wires, and in fact 3 wires (in case of unidirectional transmission). Also common to all SPI-based devices are MISO (master data in), MOSI (master data out), SCLK (clock), CS (chip select). MISO-Master Input Slave Output, the Master device data Input and the Slave device data Output; MOSI-Master Output Slave Input, Master device data Output, Slave device data Input; SCLK-Serial Clock, a Clock signal, generated by a master device; CS-Chip Select, slave enable signal, controlled by the master. CS is a control signal indicating whether the slave chip is selected by the master chip, that is, only when the chip select signal is a predetermined enable signal (high or low), the master chip is enabled to operate the slave chip. This makes it possible to connect multiple SPI devices on the same bus. Data transmission between SPI devices is also referred to as data exchange because the SPI protocol specifies that an SPI device cannot act as only a "sender" or "Receiver" during data communication. In each Clock cycle, the SPI device sends and receives data of one bit size, which is equivalent to the device having one bit size exchanged. FIFO is the abbreviation of English First In First Out, is a First In First Out data buffer, and the difference with the ordinary memory is that there is no external read-write address line, so the use is very simple, but the disadvantage is that only data can be written In sequence, the data address of the data read Out In sequence is completed by adding 1 to the internal read-write pointer automatically, and the address line can not be used to read or write a certain designated address as the ordinary memory. The TX FIFO is a transmission first-in-first-out queue, and the RX FIFO is a receiving first-in-first-out queue.
As shown in fig. 1, a control method for automatically writing data in an SPI system includes the following steps: s1: the SPI system starts to write the data of the data buffer area into the TX FIFO according to the enable signal, records the total amount of the written data, then sends the data in the TX FIFO, and proceeds to step S2; s2: the SPI system determines whether to send out the refresh interruption of the data cache area according to the relation between the total amount of written data and the capacity of the data cache area and the number of times of sending out the refresh interruption of the data cache area, if the data cache area meets the requirement, the SPI system goes to step S3, and if the data cache area does not meet the requirement, the SPI system goes to step S4; s3: the SPI system sends out a data cache area refreshing interrupt, the CPU responds to the data cache area refreshing interrupt and fills the next batch of data to be sent to the data cache area, and the SPI system enters step S1 after receiving a signal that the CPU completes the refreshing interrupt; s4: and if the data in the TX FIFO is not in line with the requirement, the SPI system writes the data in the data buffer area into the TX FIFO and finishes the work after the data in the TX FIFO is sent. Compared with the prior art, the SPI system of this scheme constantly takes out the data that will send from the data buffer area and writes into and send at data transmission in-process, because the capacity of data buffer area can greatly surpass the TX FIFO degree of depth of SPI system itself, at whole data write-in-process, CPU only need respond the lower data buffer area of interrupt frequency refresh interrupt can, the occupation rate of CPU that has significantly reduced alleviates CPU's burden, improves the operating efficiency of system.
Further, before the SPI system starts to write data, the CPU divides a data buffer, fills data to be transmitted into the data buffer, and configures the SPI system enable after configuring the read data start address, the data buffer capacity, and the number of times the data buffer needs to be refreshed of the SPI system through the ahb slave module. The data buffer area is divided by the CPU before the SPI system starts working, the size of the data buffer area can be changed according to actual conditions, and the flexibility is high. And the CPU fills the data to be transmitted into the data cache region and configures the number of times of refreshing the data cache region of the SPI system according to the relationship between the total amount of the data to be transmitted and the capacity of the data cache region.
As one embodiment, in step S1, the control module in the SPI system turns on the ahb master module enable according to the enable signal, so that the ahb master module reads the data in the data buffer according to the data start address and then writes the data into the TX FIFO, and records the total amount of the written data. In steps S1 and S4, during the process of transmitting the data of the TX FIFO, if the remaining data in the TX FIFO is less than or equal to the set value, the TX FIFO sends a water level trigger interrupt to make the SPI system continuously write the data in the data buffer into the TX FIFO. When the residual data in the TX FIFO is at a set value, the water level trigger interrupt is sent out, so that the SPI system writes data into the TX FIFO again, and the situation that the effective data are lost due to the fact that the capacity in the TX FIFO is small, all the effective data read by the ahb master module cannot be received is prevented. And the SPI system converts the data in the TX FIFO into corresponding SPI protocol excitation through a SPI interface module to complete transmission.
As one embodiment, in step S2, when the total amount of written data is equal to the capacity of the data buffer, the SPI determines that the number of data buffer refresh interrupts has been issued, and if the number of data buffer refresh interrupts has been issued is less than the number of data buffer refresh interrupts, then step S3 is performed; if the number of times of interruption for refreshing the data cache is greater than or equal to the number of times of interruption for refreshing the data cache, the process proceeds to step 4. In step S3, after receiving the signal of the interrupt of completion of refresh from the CPU, the SPI system sets the total amount of data recorded as having been read by the ahb master module to zero, and then proceeds to step S1. In step S4, the SPI system may determine that the data in the data buffer has been completely read when the total amount of written data is equal to the capacity of the data buffer, or may determine whether the data in the data buffer has been completely read according to whether the SPI system can read data from the data buffer.
The SPI system executes the control method for automatically writing data into the SPI system, the SPI system comprises two SPI controllers, a CPU and a data cache region which are connected in pairs, the SPI controllers are used for converting the data in the data cache region into excitation conforming to an SPI protocol, the CPU is used for filling the data to be written into the data cache region, the data cache region is used for storing the data, and the CPU develops and refreshes a larger storage region from a ddr or sram region to serve as the data cache region. The SPI system caches the data to be written in by the SPI system through the data cache region, so that in the whole data writing process, a CPU only needs to respond to the data cache region with lower interrupt frequency to refresh interrupt, the occupancy rate of the CPU is greatly reduced, and the operating efficiency of the system is improved. The SPI controller comprises: the control module is connected with the ahb master module and the ahb slave module and used for controlling the SPI controller to read data in the cache region; the ahb master module is connected with the control module and the TX FIFO and is used for reading data in the data buffer area and writing the data into the TX FIFO; the ahb slave module is connected with the control module, the SPI interface module, the TX FIFO and the RX FIFO and is used for configuring an internal register of the SPI system; the SPI interface module is connected with the ahb slave module, the TX FIFO and the RX FIFO and is used for converting data in the TX FIFO into corresponding SPI protocol excitation and storing data received by the SPI interface in the RX FIFO; the TX FIFO is used for storing data to be sent; the RX FIFO is used to store accepted data.
As shown in fig. 2, the total amount of data to be transmitted is 4K, taking the TX FIFO depth as 64 layers. Assuming that the data to be written by the SPI system is 4K and the capacity of the data buffer is 2K, the number of times that the CPU needs to respond to the data buffer to refresh the interrupt is 4/2-1 in the process of writing the data. Before data writing is started, a CPU in the SPI system fills 2K of 4K data to be written into a data buffer area, then three variables of a read data starting address, the capacity of the data buffer area and the refreshing time of the data buffer area of the SPI system are configured, a water level trigger value of a TX FIFO is configured to be 32, and then SPI enabling is started. Firstly, a control module in an SPI system starts an ahb master module to enable, the ahb master module reads the first 64 data of a data cache area according to a data starting address and writes the data into a TX FIFO, and then starts an SPI interface module to enable, so that the SPI interface module converts 64 data in the TX FIFO into corresponding SPI protocol excitation according to a clock signal. When the data in the TX FIFO only has 32 or less than 32 frames, a watermark triggering interrupt is generated, in this process, the ahb master module records the total amount of the data read from the data buffer area, and when the control module judges that the total amount of the data read from the data buffer area by the ahb master module is not equal to the capacity of the data buffer area, it indicates that the ahb master module has not yet read all the data in the data buffer area, and at this time, the control module responds to the watermark triggering interrupt sent by the TX FIFO, so that the ahb master module reads 32 frames of data from the data buffer area and writes the data into the TX FIFO. When the control module judges that the total amount of data read from the data buffer by the ahb master module is equal to the capacity of the data buffer, it is indicated that the ahb master module has read all the data of the data buffer, at this time, the control module will determine whether the number of times of refreshing the data buffer is equal to the number of times of refreshing the configured data buffer, if the number of times of the data cache area refreshed does not reach the number of times of the data cache area required to be refreshed, namely the CPU needs to respond to the number of times of interruption of the data cache area required to be refreshed, the control module controls the ahb master module to send out interruption of a data cache area refreshing request, and the total counter of the read or written data in the ahb master module is cleared to enter the next cycle judgment, the refreshing time of the current data cache region is increased by 1, and after the data in the TX FIFO is completely converted by the spi interface module, waiting for the refresh interrupt of the CPU response data buffer area. And after receiving the interruption of the data cache region refreshing request, the CPU fills the remaining 2K data into the data cache region and sends a data cache region refreshing completion interruption to the SPI controller. The SPI receives the interrupt and then automatically enters the next round of data writing cycle. When the control module judges that the number of times of refreshing the data buffer area is equal to the number of times of refreshing the configured data buffer area, the control module indicates that the data to be transmitted is completely loaded into the data buffer area, and the residual data in the TX FIFO is the last data to be transmitted. And after the control module waits for the spi interface module to send the last data, the control module closes the enabling of the ahb master module and the spi interface module, and the automatic writing process is finished.
As shown in fig. 3, the ahb slave module is used for the CPU to configure internal registers of the SPI system, such as a read data start address, a data buffer capacity, and a data buffer refresh rate in the control module. The control module is used for judging whether the ahb master module reads the complete data cache region and whether the current data cache region refreshing frequency reaches the configured required refreshing frequency when the TX FIFO water level triggers the interrupt generation, and controlling the ahb master module to read data from the data cache region, or sending the data cache region refreshing interrupt, or ending the process and closing the enabling of each module; and the SPI interface module converts the data in the TX FIFO into corresponding SPI protocol excitation according to the configuration value in the ahb slave module.
The features of the above embodiments may be arbitrarily combined, and for the sake of brevity, all possible combinations of the above embodiments are not described, but should be considered as within the scope of the present specification as long as there is no contradiction between the combinations of the features.
The above embodiments only express a few embodiments of the present invention, and the description thereof is specific and detailed, but not construed as limiting the scope of the invention. It should be noted that, for a person skilled in the art, several variations and modifications can be made without departing from the concept of the present application, which falls within the scope of protection of the present application.
Claims (10)
1. A control method for automatically writing data in an SPI system is characterized by comprising the following steps:
s1: the SPI system starts to write the data of the data buffer area into the TX FIFO according to the enable signal, records the total amount of the written data, then sends the data in the TX FIFO, and proceeds to step S2;
s2: the SPI system determines whether to send out the refresh interruption of the data cache area according to the relation between the total amount of written data and the capacity of the data cache area and the number of times of sending out the refresh interruption of the data cache area, if the data cache area meets the requirement, the SPI system goes to step S3, and if the data cache area does not meet the requirement, the SPI system goes to step S4;
s3: the SPI system sends out the data buffer area to refresh and interrupt, makes the CPU respond to the data buffer area to refresh and interrupt, fills the data into the data buffer area, and enters step S1 after receiving the signal that the CPU finishes refreshing and finishes interrupting;
s4: and if the data in the TX FIFO is not in line with the requirement, the SPI system writes the data in the data buffer area into the TX FIFO and finishes the work after the data in the TX FIFO is sent.
2. The method as claimed in claim 1, wherein before the SPI system starts writing data, the CPU divides the data buffer and fills the data buffer with data to be transmitted, and then configures the SPI system enable after configuring the read data start address, the data buffer capacity, and the number of times the data buffer needs to be refreshed of the SPI system through the ahb slave module.
3. The method as claimed in claim 2, wherein the CPU fills the data buffer with the data to be transmitted and configures the number of times the data buffer of the SPI system needs to be refreshed according to the relationship between the total amount of the data to be transmitted and the capacity of the data buffer.
4. The SPI system automatic write data control method according to claim 1, wherein in step S1, the control module in the SPI system turns on ahb master module enable according to the enable signal, causes the ahb master module to read data in the data buffer according to the data start address, then writes into the TX FIFO, and records the total amount of written data.
5. The SPI system automatic data writing control method according to claim 1, wherein in steps S1 and S4, during the process of transmitting the data of the TX FIFO, if the remaining data in the TX FIFO is less than or equal to the set value, the TX FIFO sends a water level trigger interrupt to trigger the ahb master module to continuously write the data of the data buffer into the TX FIFO.
6. The SPI system control method of automatically writing data according to claim 5, wherein the SPI system completes transmission by converting data in a TX FIFO into corresponding SPI protocol excitation through a SPI interface module.
7. The SPI system control method of automatically writing data of claim 1, wherein in step S2, when the total amount of data read equals the capacity of the data buffer, the SPI system determines the relationship between the number of data buffer refresh interrupts issued and the number of data buffer refresh interrupts required, and if the number of data buffer refresh interrupts issued is less than the number of data buffer refresh interrupts required, then step S3 is entered; if the number of times of interruption for refreshing the data cache is equal to the number of times of interruption for refreshing the data cache, the process proceeds to step 4.
8. The SPI system control method of automatic data writing according to claim 1, wherein in step S3, the SPI system resets the total amount of data recorded as read by the ahb master module to zero after receiving the signal that the CPU has completed the refresh completion interrupt, and then proceeds to step S1.
9. An SPI system, characterized in that it executes the control method of automatically writing data by the SPI system according to any one of claims 1 to 8, said SPI system comprising: the system comprises two SPI controllers, a CPU and a data cache region which are connected in pairs, wherein the SPI controllers are used for converting data in the data cache region into excitation conforming to an SPI protocol, the CPU is used for filling data to be written into the data cache region, and the data cache region is used for storing the data.
10. The SPI system according to claim 1, wherein the SPI controller comprises: a control module, an ahb master module, a spi interface module, a TX FIFO, an RX FIFO, and an ahb slave module, wherein,
the control module is connected with the ahb master module and the ahb slave module and is used for controlling the SPI controller to read data in the cache region;
the ahb master module is connected with the control module and the TX FIFO and is used for reading data in the data buffer area and writing the data into the TX FIFO;
the ahb slave module is connected with the control module, the SPI interface module, the TX FIFO and the RX FIFO and is used for configuring an internal register of the SPI system;
the SPI interface module is connected with the ahb slave module, the TX FIFO and the RX FIFO and is used for converting data in the TX FIFO into corresponding SPI protocol excitation and storing data received by the SPI interface module in the RX FIFO;
the TX FIFO is used for storing data to be sent;
the RX FIFO is used to store received data.
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